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Ingenic JZ4780 Design Manual

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Ingenic
JZ4780
Board Design Guide
Revision: 1.1
Date: Sept. 2013

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Summary of Contents for Ingenic JZ4780

  • Page 1 ® Ingenic JZ4780 Board Design Guide Revision: 1.1 Date: Sept. 2013...
  • Page 3 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.

  • Page 5: Table Of Contents

    USB Overview ........................19 6.1.1 USB Power ........................ 19 OTG Overview ........................19 6.2.1 OTG Power ....................... 19 Guidelines for the USB and OTG interface ................ 20 Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 17.1 SSI Design Guideline ....................... 36 17.2 UART ..........................37 17.2.1 UART Implementation ....................37 17.3 I2C BUS ........................38 17.4 PWM ..........................38 Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 7 JTAG/Debug Port ......................38 18 Platform Clock Guidelines ..............40 19 Platform Power Guidelines ............... 41 19.1 Overview .......................... 41 19.2 Power Delivery and Decoupling..................41 Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 9: Overview

    Overview Overview JZ4780 is a mobile application processor targeting for multimedia rich and mobile devices like tablet computer, smartphone, mobile digital TV, and GPS. This SOC introduces a kind of innovative architecture to fulfill both high performance mobile computing and high quality video decoding requirements addressed by mobile multimedia devices.

  • Page 10: Reference Platform

    Overview Reference Platform Figure 1-1 shows the JZ4780 Development Board Architecture. Figure 1-1 JZ4780 Development Board Architecture Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 11: Platform Stack-Up And Placement

    Figure 2-1. Nominal 6-Layer Board Stack-Up The JZ4780 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. Recommendations in this design guide are based on the following a 6-layer board stack-up:...

  • Page 12: Pcb Technology Considerations

    1.0 mils From top of trace PCB Technology Considerations The following recommendation aids in the design of a JZ4780 based platform. Simulations and reference platform are based on the following technology, and we recommend that designers adhere to these guidelines.

  • Page 13: 4-Layer Board Stack-Up

    1. The Cu Thickness is just a reference value. It is calculated by the PCB board producers for impedance matching. 4-Layer Board Stack-Up The JZ4780 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If a 4-layer board is used, the stack-up should be: Signal...

  • Page 14: 8-Layer Hdi Board Stack-Up

    Platform Stack-Up and Placement 8-Layer HDI Board Stack-Up The JZ4780 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If a 8-layer HDI board is used, the stack-up should be: Placement Layer 1 Prepreg...

  • Page 15: Static Memory Interface Design Guidelines

    The static memory controller provides a glueless interface to NOR Flash ,NAND Flash and Toggle NAND flash. It supports 6 chips selection CS6~CS1 and each bank can be configured separately. JZ4780 supports most types of NAND flashes, including SLC and MLC/TLC, 8-bit data access, 512B/2K/4K/8KB page size. It also support boot from NAND flash.

  • Page 16: Nand Flash Connection

    8-bit NAND Flash Interconnection Example JZ4780 NAND Flash CS[n]# FRE# FWE# FRB# R/B# NDQS SD[7:0] I/O [7:0] Figure 3-2 8-bit Toggle NAND Flash Interconnection Example Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 17: Ddr3 Sdram

    DDR3 SDRAM DDR3 SDRAM Overview JZ4780 contain a DDR Controller which is a general IP that provide an interface to DDR2, DDR3, LPDDR and LPDDR2 memory. The following figures give examples on the connection to external DDR3 SDRAM devices. Connection to two 2Gb x 16 DDR3 SDRAM device...

  • Page 18: Connection To Four 1Gb X 8 Ddr3 Sdram Device

    DQS/DQS# signals are within ¼ of a clock period of the rising edge of the differential clock, CK/CK#. 4) Route all Vref and support signals (JTAG etc. if implemented) Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 This will interrupt the return currents that flow beneath the conductor and can lead to crosstalk with neighboring traces. This will also increase emissions from the board. Figure 4-3 GND Joined Together Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 20 Using many capacitors, rather than a large one, will reduce the inductance. The inductance of a capacitor is dependent on its size. The capacitor Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 21 +1.5V power plane should cover the entire keep out region.  Bypassing capacitors should be close to the devices, or positioned for the shortest connections to pins, with wide traces to reduce impedance. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 22: Audio Codec Design Guidelines

    The device provides protection for contact discharges to greater than +/-15KV. Board Design Guide for JZ4780, Revision 1.0 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 23: Mic In

    SB_MICBIAS to 1 will close MICBIAS stage and the MICBIAS output voltage will be zero. MICBIAS output voltage scales with AVDCDC, equals to 5/6*AVDCDC (typical 2.08V). MICBIAS output current is 4mA max. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 24: Speaker

    The device provides protection for contact discharges to greater than +/-15KV. Note: The single input port AIP1/AIN1 and single input port AIP2/AIP3 can be configure to microphone input or line input by software. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 25: Ditigal Mic

    EMI emissions and degrading the analog and digital signal quality.  Analog power and signal traces should be routed over the analog ground plane. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 26 Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 27: Usb And Otg Design Guidelines

    An OTG device can plays the role of both host and device. JZ4780 also Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement to the USB 2.0 specification. Operates either as the function controller of a...

  • Page 28: Guidelines For The Usb And Otg Interface

    The DP/DM signal traces should also be the same length, which will minimize the effect of common mode current on EMI. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 29 USB and OTG Design Guidelines Motherboard Trace Driver 45  90  Driver Motherboard Trace 45  JZ4780 Transmission Line USB Twisted-pair Cable Figure 6-1 Recommend USB Schematic Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 30: Lcd

    The JZ4780 integrated LCD controller has the capabilities to driving the latest TFT LCD panels. It also supports some special TFT panels used in consuming electronic products. The controller performs the basic memory based frame buffer and palette buffer to LCD panel data transfer through use of a dedicated DMA controller.
  • Page 31 Lcd_spl UART4_TxD PC10 LCD_R7 Lcd_dat17 PC27 LCD_R6 Lcd_dat16 PC26 LCD_R5 Lcd_dat15 PC25 LCD_R4 Lcd_dat14 PC24 LCD_R3 Lcd_dat13 PC23 LCD_R2 Lcd_dat12 PC22 LCD_G7 Lcd_dat11 PC17 Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 32 0 (NC for panel) LCD_R1 Lcd_lo6_o[5] PC21 LCD_R0 LCD_CLS Lcd_lo6_o[4] UART4_RxD PC20 LCD_G1 Lcd_lo6_o[3] PC11 LCD_G0 LCD_SPL Lcd_lo6_o[2] UART4_TxD PC10 LCD_B1 LCD_PS Lcd_lo6_o[1] LCD_B0 Lcd_lo6_o[0] LCD_REV Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 33: Lvds

    LVDS link. It support full HDTV display up to 1920x1080p @ 60 Hz. The values of C165,C167,C172,C174 and R167,R171,R172,R173 are based on the datasheet of LCD. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 34: Hdmi

    HDMI HDMI HDMI Overview The JZ4780 support regular HDMI transmitter. The Interface conforms to the HDMI 1.4a standard。 9.1.1 HDMI Power AVDHDMI should be connected to a cleaned +1.1V power. AVDHDMI25 should be connected to a cleaned +2.5V power. For a correct working, it is required to connect decoupling capacitors (22μF and 100nF ceramic) between the pins AVDHDMI，AVDHDMI25 and AVSHDMI.

  • Page 35: Camera

    10.1 Overview The CIM (Camera Interface Module) of JZ4780 connects to a CMOS or CCD type image sensor. The CIM source the digital image stream through a common 8-bit parallel common digital protocol. The CIM can directly connect to external CMOS image sensors and ITU656 standard video decoders.

  • Page 36: Msc

    The Multi Media Card (MMC) is a universal low cost mass storage and communication media that is designed to cover a wide area of applications such as electronic toys, organizers, PDAs, smart phones, and so on. JZ4780 support SD Specification 3.0 and fully compatible with the MMC System Specification version 4.2.

  • Page 37: Ps/2 And Keyboard

    12.1 Overview The JZ4780 processor integrate PS/2 keyboard controller (KBC) to provide the functions to a keyboard or to a PS/2 mouse. KBC receives serial data from the keyboard or mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The KBC is compatible with 8042.

  • Page 38: Sar A/D Controller

    13.2 Touch Screen The JZ4780 can support 5-wire resistive touch screen. There is needed a decouple capacitor for every channel to avoid the crosstalk from LCD. The value is decided by the touch screen and can be from 100pF to 1000pF.

  • Page 39: Battery Voltage Measurement

    Users who already deployed divider resistors on board level can use VBAT to direct measure the battery value. The following figure is the approach we recommend. Use the recommended resistance, you can control the power consumption easier. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 40: Otp Efuse

    Maximum accumulative time for AVDEFUSE pin exposed under 2.5V+/-10% should be less than 1sec.  In read mode, leave AVDEFUSE to 0V or floating. Board Design Guide for JZ4780, Revision 1.0 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 41: Ethernet Design Guidelines

    Ethernet Design Guidelines Ethernet Design Guidelines 15.1 Overview As the JZ4780 processor not contains Ethernet media access controller (MAC), so it need external Ethernet MAC controller. This section describes design guidelines for the LAN on board based JZ4780. Magnetic Ethernet MAC...

  • Page 42: Rtc

    RTC power is still on. In this case, the RTC power domain consumes only a few micro watts power. The JZ4780 Need external 32768Hz oscillator for 32k clock generation RTCLK selectable from the oscillator or from the divided clock of EXCLK, so that 32k crystal can be absent if the hibernating mode is not needed.
  • Page 43 +3.3V RESET CIRCUITS VRTC18 RST_N 200k PPRST_N Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 44: Miscellaneous Peripheral Design Guidelines

    The following figures show the connection example: JZ4780 Microwire Device SSI_CE# SSI_DR SSI_DT SSI_CLK Figure 17-1 Microwire Interconnection JZ4780 SSP Device SSI_CE# SSI_DR SSI_DT SSI_CLK SCLK Figure 17-2 SSP Interconnection Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 45: Uart

    17.2 UART The JZ4780 processor has four UARTs: All UARTs use the same programming model. Each of the serial ports can operate in interrupt based mode or DMA-based mode. The Universal asynchronous receiver/transmitter (UART) is compatible with the 16550 industry standard and can be used as slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) serial infrared specification 1.1.0...

  • Page 46: I2C Bus

    The period comparator causes the output pin to be set and the free-running counter to reset when it matches the period value. The width comparator causes the output pin to reset when the counter value matches. JZ4780 contains eight pulse width modulators: PWM0 ~ PWM7.
  • Page 47 Miscellaneous Peripheral Design Guidelines Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 48: Platform Clock Guidelines

    4. EPLL mainly is used to AUDIO and other special clocks The following is the recommended circuit for main clock. When layout the board, you should keep the distance between Y1 and JZ4780 as short as possible. The 48MHz crystal should be +/-20ppm, CL≤12pF, ESR≤80ohm...

  • Page 49: Platform Power Guidelines

    Platform Power Guidelines 19.1 Overview The JZ4780 processor needs four voltages: +3.3V, +1.5V for memory, +1.1V for core,+2.5V for USB OTG and HDMI. The following figure is a typical power circuit in the tablet and smart phone application. The +1.1V need a power chip which can supply at least 1A, 1.2A is recommended.
  • Page 50 The power of LVDS should be as the following circuit. The power of CIM should be as the following circuit. The power of GPIO should be as the following circuit. Board Design Guide for JZ4780, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

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