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Ingenic X1000E Programming Manual

Iot application processor
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X1000/E
IoT Application Processor
Programming Manual
Release Date: Jul. 6, 2020

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Summary of Contents for Ingenic X1000E

  • Page 1 X1000/E IoT Application Processor Programming Manual Release Date: Jul. 6, 2020...
  • Page 2 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.
  • Page 3 VDMA status (STAT) ...................... 20 3.2.3 Global control information ..................... 20 3.2.4 JPGC trigger ........................21 3.2.5 JPGC Status ........................22 3.2.6 Bitstream buffer address ....................22 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 4 Frame ID Registers (LCDFIDx) ..................42 4.4.15 DMA Command Registers (LCDCMDx) ................ 42 4.4.16 DMA OFFSIZE Registers (LCDOFFSx) ................ 43 4.4.17 DMA Page Width Registers (LCDPWx) ................. 43 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 5 CIM Control Register 2 (CIMCR2) ................67 5.2.4 CIM Status Register (CIMST) ..................68 5.2.5 CIM Interrupt Mask Register (CIMIMR) ................. 69 5.2.6 CIM Interrupt ID Register (CIMIID) ................70 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 I2S and MSB-justified serial audio format ..............99 6.3.2 Audio sample data placement in SDATA_IN/SDATA_OUT ......... 101 6.3.3 SPDIF Protocol ......................102 I2S Operation ........................103 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 7 8.2.2 Block Diagram ......................133 8.2.3 Application schematic ....................134 Mapped Register Descriptions .................... 134 8.3.1 CODEC internal register access control (RGADW) ............ 135 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 8 8.20 Requirements on outputs and inputs selection and power-down modes ......192 8.20.1 Initialization and configuration ..................192 8.21 Circuits design suggestions ....................193 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 9 AUTOSR_CNT ......................230 9.2.19 AUTOSR_EN....................... 231 9.2.20 CLKSTP_CFG ......................231 9.2.21 DDRC_STATUS ......................232 9.2.22 PHYRET_CFG ......................232 9.2.23 PHYRST_CFG ......................233 9.2.24 CPM_DRCG ........................ 233 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 10 11.8.5 Meters of slave mode operation need attention ............273 11.8.6 Example (NAND flash write with multi phases in DMA mode) ........273 viii X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 11 Timer Stop Set Register (TSSR) ................333 13.3.16 Timer Stop Clear Register (TSCR) ................334 13.3.17 Timer Status Register (TSTR) ................. 335 13.3.18 Timer Status Set Register (TSTSR) ................ 336 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 12 Interrupt Source Register0 for PDMA (DSR0) ............353 15.2.12 Interrupt Mask Register0 for PDMA (DMR0) ............354 15.2.13 Interrupt Pending Register0 for PDMA (DPR0) ............354 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 13 17.6.10 DMA Channel IRQ Pending to MCU (DCIRQP) ............374 17.6.11 DMA Channel IRQ to MCU Mask (DCIRQM) ............375 17.7 MCU ............................ 375 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 14 Normal Mode ....................... 397 18.6.3 HIBERNATE Mode ....................... 397 18.6.4 Time Regulation ......................398 18.6.5 Clock select ........................398 19 EFUSE Slave Interface (EFUSE) ........... 400 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 15 Registers and Fields Description ................458 21.3 Operating Flow ........................482 21.3.1 I2C Behavior ........................ 483 21.3.2 Master Mode Operation ....................483 21.3.3 Slave Mode Operation ....................485 xiii X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 16 Software Guideline ......................517 23.8.1 Common flow ....................... 517 23.8.2 Interrupt Operation ....................... 518 23.9 Index ............................ 518 24 Universal Asynchronous Receiver/Transmitter(uart) ...... 520 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 17 Clock Control ....................... 556 25.4.10 Application Specified Command Handling .............. 556 25.5 Pins Description ........................556 25.6 Data Format Description ..................... 557 25.7 Register Description ......................557 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 18 26.6 Operation Flow ........................693 26.6.1 Core Initialization ......................693 26.6.2 Programming the Device Core ..................694 26.6.3 Programming the Host Core ..................697 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 USB Boot Specification ....................... 707 28.6 MSC0 Boot Specification ..................... 711 28.7 MSC1 boot Specification ..................... 713 28.8 SFC boot Specification ......................713 xvii X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 21 Table 13-2 SYS_OST Registers Configuration ................342 Table 14-1 Registers Memory Map-Address Base ..............349 Table 14-2 INTC Register ......................349 Table 15-1 Registers Memory Map-Address Base ..............357 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 22 Table 24-8 Description of Proprietary Vocabulary ............... 590 Table 24-9 The mapping between Commands and Steps ............590 Table 25-1 OTG Pins Description ....................593 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 23 Table 25-38 Host Channel-n Interrupt Register: HCINTn ............654 Table 25-39 Host Channel-n Interrupt Mask Register: HCINTMSKn ......... 656 Table 25-40 Host Channel-n Transfer Size Register: HCTSIZn ..........657 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 24 Table 27-8 Vendor Request 4 Setup Command Data Structure ..........711 Table 27-9 Vendor Request 5 Setup Command Data Structure ..........711 Table 27-10 SPI NOR flash boot flag informations(in spl signature) .......... 715 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 25 TABLES Table 27-11 SPI NAND flash boot flag informations(in spl signature) ........715 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 27 Figure 8-9 Digital microphone modulation noise reference spectrum (with FFT resolution = 20 Hz and 7 terms Blackman-Harris windowing) ................186 Figure 8-10 PSNT2 for VDDIO_CODEC when using PWM output ........... 187 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 28 Figure 20-8 Master Receiver — First Command Loaded After Tx FIFO Allowed to Empty/Restart Bit Set ..........................492 Figure 22-1 SSI Block Diagram ....................500 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 29 Figure 27-7 Typical Procedure of MSC0 Boot ................712 Figure 27-8 SPL Structure of MSC0/MSC1 Boot ............... 713 Figure 27-9 X1000/E SPI Boot Procedure ................. 714 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 31 OVERVIEW Section 1 OVERVIEW X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 32 ® – XBurst FPU instruction set supporting both single and double floating point format which are IEEE754 compatible ® – XBurst 9-stage pipeline micro-architecture X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 33 – Supports ITU656 (YCbCr 4:2:2) input – Configurable VSYNC and HSYNC signals: active high/low – Configurable PCLK: active edge rising/falling – PCLK max. 80MHz – Configurable output order X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 34 – Separate power-down modes for ADC and DAC path with several shutdown modes – Reduction of audible glitches systems: Soft Mute mode – Embedded low noise Linear Regulator X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 35 – 7 transfer formats: Standard SPI, Dual-Output/Dual-Input SPI, Quad-Output/Quad-Input SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI – two data transfer mode: slave mode and DMA mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 36 PCLK, EXTAL and RTCCLK can be used as the clock for counter  The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 37 Fast mode (400 Kb/s) – Device clock is identical with pclk – Programmable SCL generator – Master or slave I2C operation – 7-bit addressing/10-bit addressing X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 38 – Slow infrared asynchronous interface that conforms to IrDA specification – Two MMC/SD/SDIO controllers (MSC0, MSC1)  – Fully compatible with the MMC System Specification version 4.5 – Support SD Specification 3.0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 39 – Station Management Agent (SMA) – remote wake-up frame and magic packet frame processing  OTP(EFUSE) Slave Interface – Total 1Kb. 1.2.7 Bootrom 16KB Boot ROM memory X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 40 Core Functions Section 2 CORE FUNCTIONS X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 41 FPU, floating point unit implemented to improve floating point number processing ability  Unified level 2 cache that is transparent for programmer 2.1 Block Diagram X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 42 Debug D-Cache I-Cache DTLB JTLB ITLB Write Buffer JTAG L2C Bridge Unified L2 Cache Address Bus Data Bus Figure 2-1 Structure of CPU core X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 43 0 cycle penalty when BTB predicts taken Anyone and branch is taken, otherwise: 5/4/2/1 (delay slot) BTB miss, branch is taken, 3 cycles penalty. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 44 3 extra interlock cycles, LWL/LWR Anyone 4/3/2/1 LB/LBHU similarly, 2 extra for the third RAW one LH/HU and 1 extra for the forth RAW one, X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 45 No data dependency or hazards exist. Others Anyone NOTE: JMP denotes J and JR instructions; BC denotes branch conditionally instructions; BCL denotes branch conditionally and likely instructions. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 46 010: work in kernel mode 011: work in specific PC range PMON enable bit. 0: disable; 1: enable. Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 47 However, OS must make serious control for config7.bit6 and those dedicated resources to forbid this partial-kernel-mode permission for those malicious applications. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 48 IMAGE CORE Section 3 IMAGE CORE X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 49 Writing has no effect, read as zero. VDMA work mode 0: ACFG mode 1: TRAN mode VDMA trigger bit, set 1 to startup VDMA. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 50 Component 1 plane vertical size of a MCU 21:20 Component 1 plane horizontal size of a MCU 19:18 Component 0 plane vertical size of a MCU X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 51 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 52 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 53 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 54 Fixed as 0x132 19:3 Component 3 plane buffer address. Note: 1. its only used in UNIV mode reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 55 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 31:8 reserved Writing has no effect, read as zero. NBLK Number of block minus 1 in a MCU X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 56 First MB position of X direction of current slice Note: Since only rectangle slice partition of a frame is supported, so FSTX should always be set as 0. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 57 RAWC_SA then binding and delivering to the buffer indicated by RAW_DBA. It should be 512 byte aligned Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 58 0x1400 ~ 0x17FC. More detailed information is defined as the following illustration. Mapping offset Description 0x1400 ~ 0x14FC Quantization table 0 0x1500 ~ 0x15FC Quantization table 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 59 AC Huffman Table 0 0x1AC0 ~ 0x1D7C AC Huffman Table 1 0x1D80 ~ 0x1DBC DC Huffman Table 0 0x1DC0 ~ 0x1DFC DC Huffman Table 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 60 DISPLAY/CAMERA/AUDIO Section 4 DISPLAY/CAMERA/AUDIO X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 61 SLCD_TE Input Smart LCD tearing effect signal SLCD_DAT [15:0] Output The data of SLCD. Serial: SLCD_DAT [15] Parallel: 16bit SLCD_DAT [15:0] 8bit SLCD_DAT [7:0] X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 62 RSW - read and write, but set to 1 by read RWC - read and write, clear to 0 by write 1, write 0 has no effect X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 63 Display Area 0x0010 Horizontal Start/End Point LCDDAV Display Area Vertical 0x0014 Start/End Point Foreground 0 XY 0x0120 LCDXYP0 Position Register LCDXYP1 Foreground 1 XY 0x0124 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 64 DMA1 Page Width 0x0074 LCDPW1 Registers LCDCNUM1/LCDPOS1 DMA1 Commend 0x0078 Counter Registers Foreground1 x Size in 0x007C LCDDESSIZE1 Descriptor Priority level 0x02C0 LCDPCFG threshold configure X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 65 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 66 RST 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 67 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 68 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 69 = REVE + 1; 4.4.11 Interrupt ID Register (LCDIID) LCDIID is a read-only register that contains a copy of the Frame ID register (LCDFID) from the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 70 NOTE: If only one frame buffer is used in external memory, the LCDDAx field (word [0] of the frame descriptor) must point back to itself. That is to say, the value of LCDDAx is the physical address of itself. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 71 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 Buffer start address. (Only for driver debug) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 72 It is used to distinguish command and data in lcm mode. And it is only loaded via DMA channel 0. 1: The data is command 0: The data is data X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 73 30lines, the picture will be divided to 3 blocks of 30lines. Then OFFSIZE indcates the size between 2 pagewidth. But usually we will set PAGEWIDTH as large as 1line, and divide the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 74 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 75 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 76 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 77 Do not change this bit Reserved Writing has no effect, read as zero. CLKPLY Do not change this bit TTYPE Do not change this bit X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 78 8-bit color depth information(RGB332) , one pixel per cycle. 2‘b01 : 2-times transfer is used to transmit 1 pixel data, such as sending 16-bit color depth information(RGB565) , one and half X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 79 24bpp data in output fifo to relative bpps as follows 24bpp data in output fifo: 8bpp output data(R3G3B20: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 80 18 bits or the total 24bits of slcd data is useful, and the cmd will be data[17:0] or data[23:0]. Note5： DTIMES_NEW and CTIMES_NEW is only useful for descrptor mode, when in regster mode, X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 81 DMAMODE high or low depending on wether you want to use dma single mode or dma continue mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 82 Bits Name Description 31:30 The PTR bit of data register is used to decide the meanings of the low 24-bit. 2‘b00: data 2‘b01: command X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 83 SLOW_TIME: if use the function of slcd to wait for TE‘s relative edge, slcd will wait for SLOW_TIME‘s period of pixclk before it begin to flush out data X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 84 The SLCD Controller must not be re-enabled until the QD bit is set, indicating that the quick shutdown is complete. Do not set the DIS bit when a quick disabling command has been issued. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 85 It is suggested that the extra bits to be set zero. 4.6 System Memory Format 4.6.1 Data format 16bpp 18bpp X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 86 30bpp 16bpp with alpha 18bpp with alpha 24bpp with alpha 24bpp compressed BLUE 1 [7:0] RED 0 [7:0] GREEN 0 [7:0] BLUE 0 [7:0] X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 87 RED2 [7:0] 4.6.2 Command Format 18-bit command 16-bit command 9-bit command once 8-bit command once 8-bit command twice (Command = command part + data part) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 88 Because DMA transfer mode only can work in OSD mode, you need to configure the panel according OSD mode: Set Color. * LCDBGC0,1, LCDKEY0, LCDKEY1, LCDALHPA Set Display. * LCDVAT, LCDDAH, LCDDAV * LCDVSYNC, LCDHSYNC Set Descriptors. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 89 DC [31] = 0 XXX [30:9] Data [8:0] DC [31] = 0 XXX [30:8] Data [7:0] 4.8 Timing 4.8.1 Parallel Timing LCD_PCLK DATA Command Data X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 90 *please notice that use and only use DMA0 to transfer command no matter use DMA0 to transfer frame data or not. One recommend descriptor chain (CMD0 with CNUM>0 and CMD1 with CNUM=0): CMD0 CMD1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 91 5. setup SLCD for descrptor mode, here to make sure the 1 descriptor is cmd and CMDNUM>0, then the descriptor should switch between data and cmd X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 92 Table 5-2 CIM Registers Name Reset Value Offset Access Size CIMCFG 0x00000000 0x0000 CIMCR 0x00000000 0x0004 CIMST 0x00150002 0x0008 CIMIID 0x00000000 0x000C CIMDA 0x00000000 0x0020 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 93 OByte3 stands for the 4th byte stored in memory Then BS0 = 0: IByte0 is stored in OByte0 BS0 = 1: IByte1 is stored in OByte0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 94 3 input data bytes to form 32-bit data. 0: DUMMY zero function disabled 1: DUMMY zero function enabled E_VSYN External / internal VSYNC selection. When DSM is ITU656Progressive X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 95 1: External HSYNC mode, HSYNC is provided by image sensor via pin HSYNC Data sample mode. Please refer to the table below. Description 2‘b00 ITU656Progressive Mode 2‘b01 ITU656Interlace Mode 2‘b10 Gated Clock Mode 2‘b11 Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 96 0: Not request to stop 1: Request to stop SW_RST Software reset enable. 0: Don‘t care 1: Reset the CIM module. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 97 16 < n <= 32 32 < n 2‘b01 n <= 16 16 < n <= 32 32 < n <= 64 64 < n X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 98 When set to 1, indicates the DMA complete transferring data and stop the operation. Can generate an interrupt if CIMIMR.DSTPM is 0. Write 0 to clear. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 99 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 Bits Name Description 31:12 Reserved Read as zeros. DEEOFM The control bit to mask DMA EEOF interrupt. 0: enable X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 100 CIM state register. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 101 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 102 DMA to a frame buffer. LEN = 0 is not valid. DMA transfers data according to LEN. Each time one or more word(s) been transferred, LEN is decreased automatically. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 103 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 104 Gated Clock Mode ITU656 Interlace Mode ITU656 Progressive Mode 5.3.1 Timing Diagram CIMCFG.PCP == 0, Data is sampled by PCLK rising edge PCLK Data/ Hsync/ Vsync X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 105 PCLK when HSYNC is active; That means, HSYNC functions like ―data enable‖ signal. Please refer to the figure below. The VSYNC leading edge, HSYNC active level, PCLK valid edges are programmable. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 106 313-335 1: blanking end of active start of active video video 336-623 0: video data Field 2 624-625 1: blanking Coding for protection codes: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 107 [0] contains the physical address for next CIMDA word [1] contains the value for CIMFID word [2] contains the physical address for CIMFA X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 108 When using hardware to deal with frame size error, the flows configuration should be used: CIMCMD.OFAR should be set to 1 when preparing the DMA descriptor(s). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 109 Supports IEC60958 two-channel PCM audio and IEC61937 multi-channel compressed audio (Dolby Digital, DTS, etc.). This chapter describes the programming model for the AIC. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 110 8, 16, 18, 20 and 24 bit audio sample data sizes supported  DMA transfer mode supported  Stop serial clock supported  Programmable Interrupt function supported X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 111 Audio bit clock input SYNC Left/right words select input SYS_CLK Master/system clock input Figure 6-3 Interface to an External Slave Mode I2S/MSB-Justified CODEC Diagram (Share Clock Mode) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 112 MSB-justified format it inputs from the CODEC in slave mode and outputs to CODEC in master mode. In the master mode, the clock is generated internally that is 64 times the sampling frequency. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 113 Register AICSR AIC FIFO Status Register 0x00000008 0x10020014 AIC I2S/MSB-justified Clock Divider 0x00000003 I2SDIV 0x10020030 Register AICDR AIC FIFO Data Port Register 0x???????? 0x10020034 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 114 Writing has no effect, read as zero. 20:16 TFTH Transmit FIFO threshold for interrupt or DMA request. The TFTH valid value 0 ~ 31. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 115 CODEC. SYNCD SYNC Direction. This bit specifies input/output direction of SYNC in I2S/MSB-justified format. Change this bit in case of BIT_CLK is stopped X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 116 LSB align. The packed mode is only support 16bit sample size. PACK16 Sample Size Unpacked data mode. One word only contains one 16bit sample X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 117 Enabled. TDMS Transmit DMA enable. This bit is used to enable or disable the DMA during transmit audio data. TDMS Transmit DMA Disabled. Enabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 118 Enable TUR Interrupt. This bit is used to control the TUR interrupt enable or disable. ETUR TUR Interrupt Disabled. Enabled. ERFS Enable RFS Interrupt. This bit is used to control the RFS interrupt enable X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 119 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:18 Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 120 AIC Controller FIFO Status Register (AICSR) AICSR contains bits to reflect FIFOs status. Most of the bits are read-only except two, which can be written a 0. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 121 FIFO threshold, which is controlled by AICFR.RFTH. When RFS is 1, it may trigger interrupt or DMA request depends on the interrupt enable and DMA setting. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 122 Description AIC Receiver part is idle or disabled. AIC Receiver part currently is transmitting or receiving a frame. AIC busy in I2S/MSB-justified format. Description X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 123 RST 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 124 0: DMA transmitter disable 1: DMA transmitter enable D_TYPE If the bit number of data is less than16, the data in memory is as follows: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 125 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 126 Specify the trigger value of FIFO. TRIG Description Trigger Value is 4. Trigger Value is 8. Trigger Value is 16. Trigger Value is 32. 11:8 SRC_NUM Source number. 0000:Unspecified X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 127 Original sampling frequency. 1111:44.1kHz 1101:48kHz 1100:32kHz 0101:96kHz 0001:192kHz Others: Reference IEC60958-3 21:19 SAMPL_WL Sample word length. When MAX_WL=1: 001:20 bit 110:21 bit 010:22 bit 100:23 bit X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 128 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 129 In the A: LR mode, first send the left channel in a stereo frame. One Left slot and one Right slot make a sample frame. It is the normal mode of I2S. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 130 … 28 29 30 31 32 33 34 35 … 60 61 62 63 Cycle No. BIT_CLK SDATA_OUT B31 B30 Or SDATA_IN SYNC Right Left Figure 6-8 MSB-justified data format (D: RL mode) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 131 … Table 6-3 escribed the how sample data bits are transferred. Table 6-3 Sample data bit relate to SDATA_IN/SDATA_OUT bit I2S/MSB-Justified Format SDATA IN/OUT X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 132 Figure 6-9 Block format Sub-frame format in PCM mode is shown below: 27 28 Sync preamble Auxiliary Audio sample word Figure 6-10 Sub-frame format in PCM mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 133 AIC and optional, the external CODEC. Here is the initial flow. Select external CODEC (AICFR.ICDC). If I2S/MSB-Justified is selected, select between I2S and MSB-Justified (I2SCR.AMSL). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 134 Configure sample rate by clock dividers (for I2S/MSB-Justified format with BIT_CLK is provided internally) or by CODEC registers (for BIT_CLK provided by external CODEC). Some other configurations: mono to stereo, endian switch, signed/unsigned data transfer, X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 135 Take sample data from the receive FIFO until AICSR.RFL change to 0. So that all samples in the receive FIFO has been taken away, then we can have a clean start up next time. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 136 In case of DMA bus initiator, one 24, 20, 18 bits audio sample must occupies one 32-bits word in memory, so 32-bits width DMA must be used. One 16 bits sample occupies one 16-bits half word in X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 137 Through read these register fields, processor can detect when there are samples in receiving FIFO in audio record and then load them from the RX-FIFO, and when there are rooms in transmitting X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 138 0xXXXXX004 0xXXXXX000 0xXXXXX000 Figure 6-13 One channel (Left) and Two channels (right) mode (16 bits packed mode) Four channels mode and six channels mode: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 139 …… bit0 0xXXXXX004 0xXXXXX000 0xXXXXX000 Figure 6-16 One channel (Left) and Two channels (right) mode Four channels mode and six channels mode: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 140 The BIT_CLK is the rate at which audio data bits enter or leave the AIC. BIT_CLK can be supplied either by the CODEC or an internally PLL. If it is supplied internally, BIT_CLK is configured as output X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 141 CPM divider controlled by I2SCDR. If BIT_CLK is chosen as an output, another divider in AIC is used to divide SYS_CLK for it. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 142 PLL frequency as close to the frequencies listed as possible, then use clock dividers to generate different SYS_CLK/BIT_CLK for different sample rate. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 143 For an EXCLK clock frequency, try to generate PLL frequencies as close to the frequencies listed in Table 6-6 as possible. Table 6-8 lists the PLL parameters and audio sample errors at different PLL frequencies for EXCLK at 12MHz. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 144 The following status bits, if enabled, interrupt the processor:  Receive FIFO Service (AICSR.RFS). It‘s also DMA Request.  Transmit FIFO Service (AICSR.TFS). It‘s also DMA Request.  Transmit Under-Run (AICSR.TUR). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 145 Set SPCTRL.DMA_EN to choose DMA mode or CPU mode. Set SPCTRL.SIGN_N to choose whether to transfer the most significant bit by toggle or not. Set SPCTRL. SFT_RST to 1 reset FIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 146 Disable operation Set SPENA.SPEN to 0 to disable SPDIF to transmitter. Wait SPSTATE.BUSY to be set to 0 by hardware. You can do other operation. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 147 PCM Serial clock Line signal input/output PCMSYN Input / Output PCM sync signal input/output PCMDOUT Output PCM Serial data output PCMDIN Input PCM Serial data input X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 148 RS - read only, and set to 1 by read SPEC - special access method, relate to its description 3. Reset Value 1 - reset to 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 149 ERDMA Receive DMA Disabled. Enabled. ETDMA Transmit DMA Enable. This bit is used to enable or disable the DMA during transmit audio data. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 150 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 151 FIFO, indicated by PCMINTS.TFL, is less than the threshold value, PCMINTS.TFS is set. Smaller TFTH value provides lower DMA/interrupt request frequency but have more risk X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 152 TFS Interrupt Disabled. Enabled. ETUR Enable TUR Interrupt. This bit is used to control the TUR interrupt enable or disable. ETUR TUR Interrupt Disabled. Enabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 153 Transmit FIFO Under Run. This bit indicates that transmit FIFO has or has not experienced an under-run. Description When read, indicates under-run has not been found. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 154 PCMCLK clock divider value minus 1. Controls the divider used to create the PCMCLK based upon the CPM_PCM_SYSCLK. PCMCLK = CPM_PCM_SYSCLK / ( CLKDIV + 1 ). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 155 Figure 7-2 Short Frame SYN Timing (Shown with 16bit Sample) NOTE: Figure 7-2 shows a PCM transfer with the MSB configured one shift clock after the PCMSYN. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 156 Short PCMSYN Or Long PCMSYN Don't Care PCMDOUT Don't Care PCMDIN Figure 7-5 Multi-Slot Frame SYN Timing (Shown with two Slots and 8bit Sample) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 157 Initialize PCM and configure the register. Write 1 to PCMCTL.PCMEN and PCMCTL.CLKEN. Fill sample data to the transmit FIFO. Repeat this till finish all sample data. In this X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 158 FIFO and read from receive FIFO. One time access to PCMDP.DATA process one sample. The sample data should be put in LSB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 159 Polling approach is in very low efficiency and is not recommended. 7.6.5.2 Interrupt and Processor Access Set proper values to PCMCFG.TFTH and PCMCFG.RFTH, the FIFO interrupts trig thresholds. Set X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 160 Transmit FIFO Service (PCMINTS.TFS). It‘s also DMA Request.  Transmit Under-Run (PCMINTS.TUR).  Receive Over-Run (PCMINTS.ROR). For further details, see the corresponding register description sections. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 161 TBD = parameter or document section to be defined later on TBC = parameter or document section subject to change TO BE COMPLETED = section to be filled or subject to change X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 162 DMIC_IN is ‗GPIO : G3‘ , MIC_CLK is ‗GPIO : R5‘. Please refer to GPIO specification for these pins operating. nLR: Internal low noise linear regulator. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 163 Off if SB or SB_SLEEP or SB_ADC; Enable ADC Path to AIC Off if SB or SB_SLEEP or SB_DAC; Enable DAC Path to AIC Figure 8-2 Internal CODEC works with AIC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 164 The internal CODEC software interface includes 2 registers. They are mapped to IO memory address space of AIC module so that program can access them to control the operations of the CODEC. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 165 When it issues a writing command to CODEC‘s internal register, 14:8 RGADDR i.e.RGWR=1, this field specifies the corresponding CODEC register‘s address. In addition, this field also decides the address of the CODEC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 166 The internal embedded CODEC is controlled through its internal registers. These registers data can be accessed through memory-mapped registers, RGADW and RGDATA. AIC‘s BITCLK and X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 167 CODEC input SYNC to AIC. I2SCR.AMSL = 1; Use I2S operation mode. I2SCR.ESCLK = 1; Open MCLK to internal CODEC. (if using PLL Clock) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 168 CODEC input BIT_CLK to AIC. AICFR.SYNCD = 0; CODEC input SYNC to AIC. I2SCR.AMSL = 1; Use I2S operation mode. I2SCR.ESCLK = 1; Open MCLK to internal CODEC. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 169 Tsbyu is the reference wake-up time after complete power down. Tshd_adc is the ADC wake-up time after sleep mode. Tshd_dac is DAC wake-up time after sleep mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 170 The current in case of short circuit is the max value. This current is only sink or drawn until the short circuit detection system acts. Please refer to Chip Datasheet for more details. 8.7 CODEC internal Registers X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 171 0x0E CR_ADC ADC control register 0x0F CR_MIX Digital mixer control register 0x10 DR_MIX Digital mixer data register 0x1A MIX_0 Digital mixer control register 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 172 DAC2 soft clipping DRC control register 1 DAC2_AGC_2 DAC2 soft clipping DRC control register 2 DAC2_AGC_3 DAC2 soft clipping DRC control register 3 CR_ADC_AGC ADC automatic gain control register 0x2F X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 173 0: SRC is not locked. Data from the audio interface are automatically muted. 1: The SRC is locked and operating normally. Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 174 Writing has no effect, read as zero. 8.7.2.5 SIGR3: Signature Register 3 Register Name: SIGR3 Register Address: 0x04 bit7-R-? bit6-R-? bit5-R-? bit4-R-? bit3-R-? bit2-R-? bit1-R-? bit0-R-? Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 175 DAC_MUTE Read 00 : DAC not muted 01 : DAC being muted 10 : DAC leaving mute mode 11 : DAC in mute mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 176 Audio Data Word Length for ADC path. Read / Write 00: 16-bit word length data 01: 18-bit word length data 10: 20-bit word length data X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 177 SB_MIC1 MICBIAS1_V Reserved Bits Field Description Reserved Writing has no effect, read as zero. MICIDFF1 Microphone 1 input mode selection Read/Write 0= single-ended input X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 178 1: puts the DAC in soft mute mode Reserved Writing has no effect, read as zero. Reserved Writing has no effect, read as one.. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 179 8.7.2.16 CR_ADC: Control Register for ADC Register Name: CR_ADC Register Address: 0x0F bit7-RW-1 bit6-RW-0 bit5-RW-0 bit4-RW-1 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 ADC_SOFT_ ADC_DMIC_ Reserved SB_ADC Reserved MUTE X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 180 Refer to DR_MIX for MIX_LOAD description MIX_ADD Digital mixer control registers address Read/Write MIX_ADD Corresponding control register 000000 MIX_0 000001 MIX_1 000010 MIX_2 000011 MIX_3 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 181 MIX_1: Digital mixer control register 1 Register Name: CR_MIX Indirect register Address: 0x01 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 MIXDACL_SEL MIXDACR_SEL Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 182 Reserved Writing has no effect, read as zero. Note: MIXADCX_SEL should be configured to 01 in normal mode. MIX_4: Digital mixer control register 4 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 183 Reserved MCLK_DIV Reserved SHUTDOWN_ CRYSTAL CLOCK Bits Field Description Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 184 8.7.2.22 SFCCR_DAC: DAC Sample frequency fine control register Register Name: SFCCR_DAC Register Address: 0x15 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 DACFREQ_ DAC_FREQ_ADJ[14:8] VALID X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 185 Selection of the ADC sampling rate (Fs). Read/Write The sampling frequency value is given in the FREQ table. NOTE: Please refer to section Sample frequency: FREQ. 8.7.2.25 CR_TIMER_MSB: counter MSB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 186 8-bit parallel control interface or 8 MCLK cycles duration when using I2C control interface Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 187 8.7.2.29 IFR: Interrupt Flag Register Register Name: IFR Register Address: 0x1C bit7-RWC-? bit6-RWC-? bit5-RWC-? bit4-R-? bit3-R-? bit2-RWC-? bit1-RWC-? bit0-RWC-? ADAS_LOCK_ Reserved ADC_MUTE_ Reserved DAC_MUTE_ EVENT EVENT EVENT X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 188 Mask for the TIMER_END flag MASK Read/Write 0: interrupt enabled 1: interrupt masked (no IRQ generation) Reserved Writing has no effect, read as one.. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 189 8.7.2.33 GCR_DACR: right channel DAC Gain Control Register Register Name: GCR_DACR Register Address: 0x20 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 Reserved GODR X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 190 Reserved GIM1 Bits Field Description Reserved Writing has no effect, read as zero. GIM1 Microphone 1 boost stage gain programming value. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 191 Reserved Bits Field Description Reserved Writing has no effect, read as zero. ―Programmable input attenuation amplifier: GID‖. NOTE: Please refer to the section X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 192 8.7.2.42 GCR_MIXADCL: ADC Left Digital Mixer Control Register Register Name: GCR_MIXADCL Register Address: 0x29 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 LRGIMIX Reserved GIMIXL X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 193 DAC_AGC_ADD LOAD Bits Field Description DAC_AGC_EN Enable of the AGC system. Read/Write 0 : inactive 1 : enable the automatic level control DAC_AGC_LOAD Read/Write X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 194 00000: Full scale 00001: Full scale -1dB 00010: Full scale -2dB by step of - dB 11110: Full scale -30dB 11111: Full scale -31dB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 195 8.7.2.45.4 DAC_AGC_3: DAC Soft clipping DRC control register 3 Register Name: DAC_AGC_3 Indirect register address: 0x03 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 Reserved RCOMP X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 196 1: Left and right channels DRC parameters are the same: LTHRES and LCOMP are used for both left and right channels Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 197 00010: Full scale -2dB by step of - dB 11110: Full scale -30dB 11111: Full scale -31dB 8.7.2.47.4 DAC2_AGC_3: DAC Soft clipping DRC control register 3 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 198 Instructions for writing into a register The data must firstly be written into the DR_ADC_AGC register. The register address must then be written in CR_ADC_AGC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 199 000: -72 dB 001: -66 dB …by step of 6dB 111: -30 dB HOLD Hold time before starting AGC adjustment to the TARGET value. Read/Write X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 200 Reserved AGC_MAX Bits Field Description Reserved Writing has no effect, read as zero. AGC_MAX Maximum Gain Value to apply to the ADC path. NOTES: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 201 11101 39.5 00110 01110 10110 11110 00111 10.5 01111 22.5 10111 30.5 11111 42.5 Please refer to section ―AGC system guide‖ for more details. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 202 Register Address:0x34 bit7-RW-? bit6-RW-? bit5-RW-? bit4-RW-? bit3-RW-? bit2-RW-? bit1-RW-? bit0-RW-? Reserved Bits Field Description Reserved Writing has no effect. 8.7.2.54 CR_TR: Test Mode Control Register X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 203 Reserved Bits Field Description Reserved Writing has no effect. 8.7.2.58 SR_TR_SRCDAC: DAC test Mode Status Register X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 204 If the HPF is activated, data are valid after about 64 sample periods but the offset cancellation is not still completed at this time due to its internal time constant. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 205 The value of the gain GODL/R is programmable from +0 to –31dB with 1 dB pitch. The gain and output levels are obtained according to the following table: Decimal decoded value Gain Value (dB) … X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 206 Programmable digital mixer gain: GIMIX and GOMIX The following table shows the relation between the gain and GIMIX/GOMIX. GIMIX or GOMIX Gain value (dB) 00000 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 207 LOAD Rhpdo value capacitor values value Driving Headphone 16 Ohm / 220uF 470 Ohm typ. Driving Lineout 10k Ohm / 1uF 4.7k Ohm max. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 208 0000 8 kHz 0001 11.025 kHz 0010 12 kHz 0011 16 kHz 0100 22.05 kHz 0101 24 kHz 0110 32 kHz 0111 44.1 kHz X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 209 After power supplies ramp up, the CODEC starts its internal initialization sequence and SR. PON_ACK register is changed when the initialization sequence is complete. An interrupt request is sent when the ramp completes. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 210 GIM) in order to best reach this target. AGC_MAX and AGC_MIN fix the limits of the gain variation. ―CODEC Operating modes‖ for the AGC System diagram in the ―CODEC Power Please refer to Diagram‖. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 211 The noise gate threshold is set by the NG_THR register value. The following graph shows a more detailed application. The following graph summarizes the operations and shows more details. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 212 The part above the threshold id divided by the compression rate (programmed in soft clipping registers DAC_AGC_*); thus, the signal above threshold at the output of the soft clipping DRC is: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 213 AIDAC*SEL, AIADC*SEL, MIXDAC*SEL and MIXADC*SEL functionality are applied between the Digital Mixer and the Data interface. The behavior is the following: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 214 CODEC accepts bitstream from digital microphone and converts it into audio data at the sample rate (Fs) selected in FCR_ADC register. CODEC provides a clock (DMIC_CLK) and receives data on X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 215 CODEC can receive simultaneously data from two digital microphones. 8.17.1 Timing Diagram Figure 8-8 Digital microphone timing diagram at MCLK = 12 MHz (DMIC_CLK = 3 MHz) 8.17.2 Timings X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 216 The following graphic represents the maximum noise allowed on CODEC_AVDD to reach SNR performances of 80 or 95 or 105 dB on the DAC outputs. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 217 Normal mode: When CODEC is not in above mode, it is in this mode. This mode has three modes: RECORD mode, REPLAY mode, RECORD_REPLAY mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 218 Power-on sequence When the power supply ramps up, CODEC enters the power-on sequence. During this mode, the CODEC needs to be put in power-down in order to reduce audible pops. Power-down sequence X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 219 The CODEC then generates an IRQ and set DAC_MUTE_EVENT (respectively ADC_MUTE_EVENT) register bit to ‘1‘. Figure 8-13 ADC Gain up and gain down sequence X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 220 When SB_SLEEP is set to ‘1‘, CODEC enters the sleep mode. Analog functions - except the voltage biasing references - enter the power-down mode. Thus, the power consumption is reduced without penalizing the start-up time. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 221 Different working modes are sum-up in the following table (non exhaustive table): Mode Register signal values after a reset mode power-down mode Sleep mode X X X X X X X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 222 To use the embedded CODEC with AIC, the following AIC registers should be set up before start the CODEC: AICFR.ICDC = 1 AICFR.AUSEL = 1 AICFR.BCKD = 0 AICFR.SYNCD = 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 223 (PSNT2) described in the sections Power Supply Noise Tolerance Template. X1000 Audio codec power supply VDDIO_CODEC VSSIO_CODEC AGND Figure 8-15 Peripheral power supply connection X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 224 Application schematic with differential MIC input (Vmicbias generated on board): XBurst Processor MICBIAS MICBIAS 1 uF MICP MICN 1 uF CODEC_AVSS Application schematic with single-ended MIC input (using MICBIAS pin): X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 225 MICBIAS output current is 4mA max. MICBIAS output noise is 40uVrms max. This configuration is better suited for microphone with single wire + shielding. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 226 The track length between any signal input of the amplifier and the components must be shorter than 1 cm. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 227 Cmic Micbias decoupling capacitor Refer to +/-20% Microphon Rmic Microphone external resistor connection Cbyline Input bypass capacitor +/-20% > maximum analog power X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 228 1 kHz sine wave @ Full Scale -1 dB and gains = 0 dB Fs≤ 16 kHz 1 kHz sine wave @ Full Scale -1 dB and gains = 0 dB Fs > 16 kHz X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 229 A-weighted, 1 kHz sine wave @ Full Scale -60 over gain range dB and gain GIL*= 0 dB, boost gain GIM* = (DRgr) [0-20]dB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 230 AIP-AIN to DIL (1) Scales with VREF = VREFP_CODEC- CODEC_AVSS (2) The specified value is extrapolated by adding 60 dB to the measured SNR X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 231 Parameter Min. Max. Unit Fall Time Rise Time Difference between Fall Time and Rise Time Skew between PWM outputs (*LP, *LN, *RP, *RN) (1) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 232 24MHz Wind Noise Filter corner Mode 1 -3 dB 59 Hz frequency Mode 2 -3 dB 117 Hz Mode 3 -3 dB 235 Hz X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 233 MEMORY INTERFACE Section 5 MEMORY INTERFACE X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 234 Row address width less than 16-bit & Column width less than 12-bit are supported. 9.1.2 Block Diagram Following figure shows the functional block diagram of DDR system. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 235 Please Note that: the DDRC_AHB_CFG_GROUP must not be access under retention mode. Table 9-1 DDRC Register Address Name Group Width Access Description offset DSTATUS DDRC_AHB 0x00 DDR Status Register X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 236 DDRC_AHB 0x34 Multi-media stride register WCMDCT Write command reorder & grouping DDRC_AHB 0x100 (Performance control) RCMDCT Read Channel mode control DDRC_AHB 0x104 (Performance control) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 237 0x310 Bus efficiency data ALUE CLKSTP_ DDRC_APB 0x068 Auto Clock Gating configuration DDRC_S DDRC_APB 0x06C DDR status TATUS PHYRET_ DDRC_APB 0x034 Retention Mode Configuration X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 238 (reset value) DFI initialization completed ENDIAN: Read-only, indicate the data endian status. Bit [7] Description Remark Little data Endian. (reset value) Big data Endian. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 239 (reset value) CKE1 Pin is high. CKE0: Indicate the CKE0 Pin status of DDR memory. Bit [0] Description Remark CKE0 Pin is low. (reset value) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 240 Normal SDR (Single-Data-Rate) SDRAM(Not support). (reset value) Mobile SDR(Not support). Normal DDR1 (Not support) Mobile DDR(LPDDR). Normal DDR2. LPDDR2(Not support) Normal DDR3 LPDDR3 (Not support). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 241 DDR Pin CS0 is in use. BA0/1: Bank address width of external memory device. Bit [1] Description Remark 4 bank device (reset value) 8 bank device X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 242 When there‘s no access to DDR memory for a period of time, hardware drives DDR into power-down mode to save power consumption. Hardware can exit Power-Down mode automatically when new access arrives. If PDT=0, power-down function is disabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 243 SLOWEXPD: Slow exit power-down enable. If set, the controller use DTIMING6.tXSRD value as tXPDLL. Bit [3] Description Remark Slow exit power-down disenable. (reset value) Slow exit power-down enable. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 244 When performing a DDR command, BA[2:0] corresponding to external DDR address Pin BA[2:0]. Bit [10:8] Description Remark corresponding to external DDR address Pin (reset value) BA[2:0]. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 245 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 246 WRITE Recovery Time defined by register MR of DDR2 DDR3 memory. tWL: Write latency, please notice that this version only support AL=0. tCCD: CAS# to CAS# command delay X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 247 CKE pulse width, include high level and low level. Bit [18:16] Description Remark 1 tCK. (reset value) 2 tCK. 3 tCK. 4 tCK. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 248 EXIT-POWER-DOWN to next valid command period. tXP defines the EXIT-POWER-DOWN to next valid command period to all banks. Bit [6:4] Description Remark 1 tCK. (reset value) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 249 When the DDR memory is in self-refresh mode or in deep-power-down mode, disable the clock of auto-refresh counter can save power consumption. Future more, the module clock to DDRC can also be stopped. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 250 Bits 31~16: Reserved. Writing has no effect, read as zero. BASE: base address. MASK: address mask. Examples: 1 DDR address space in system memory : 0x2000_0000 ~ 0x2FFF_FFFF (256MB) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 251 RST 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 252 Terminology: Priority: priority of command, the command with higher priority will be processed prior to that with lower priority. The priority is generated from: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 253 Range: 0x001 ~0xFFF NOTE: configure step: 1. set disable_reorder to 0. 2. execute step1 for 14 times 3. set wcmd_pend_qos to expect value X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 254 RST 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 Bits Name Description Reset [31] ch3_rcmd_igr_cflit 1: enable. Consistence between wcmd and rcmd will not be guaranteed. 0: disable. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 255 If Ch1 rfifo level threshold higher than this value, rcmd request is masked ch4_rcmd_igr_cflit 0: disable rfifo_thd (recommended) 1: enable rfifo_thd ch4_fifo_thd_en 1: enable. consistence between wcmd and rcmd will not be guaranteed. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 256 1: Wready bolck Debug usage, don't change this bit [15:14] CH7_boundary 0: 512byte boundary (default) 1: 1024byte boundary 2: 2048byte boundary 3: 4096byte boundary X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 257 RST 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 258 Port_pri: priority provided by masters. Iport_pri: register configurable which applies to each ports. The finial priority is the larger value of port_pri and iport_pri. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 259 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 260 Timer Cnt: when the bus interface is idle(all transfer are 0x100 finished), the internal timer is going to run, after the Timer Cnt is meet, DDR issues Self-Refresh command. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 261 Clock is gating, the timer used for lp/auto-sr will stop running. As a result, if the Auto-self-refresh enabled, the bit [28] should be set. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 262 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 Bits Name Description Rrset cfg_iso_en PHY output prdata isolation enable phy_iso_en PHY output dfi signal isolation enable (high-active) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 263 [31:2] Reserved Inner usage, keep 0x10 DLLRESET 1: reset the DLL in DDR PHY 0: disable the reset. CFGCLKEN Inner usage, keep to 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 264 // Enable Refresh Counter //----------------------------------------------------------------------------------------------------------- 14 Enable Refresh Counter : Configure DREFCNT = 0x. 15 AUTO-REFRESH : Configure DCTRL = 0x. //----------------------------------------------------------------------------------------------------------- // END INITIALIZING SEQUENCE X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 265 (0xB00000D0) CPM_DRCG[1] <= 1; Step2, Configure DLL into bypass mode. (0xB3011014) DDR_ACDLLCR[0] <= 1; Then, (0xB00000D0) CPM_DRCG[1] <= 0; 9.5 Data Endian Fix to little Endian. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 266 DDRC_STATUS.ddr_sr_mode to make sure the DRAM is in self-refresh mode S3: Read ZQ value and reserve it future use. (refer: X1000_ddrphy_spec: ZQnSR0.ZCTRL) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 267 Please note that, the retention mode is only used in system sleep mode, which still powering on GPIO. Because GPIO is must for exiting retention operation. 9.6.2 Exit Retention mode Soft ware control flow X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 268 Turn off CPM: ddr gating if it is gated in 'Enter Retention Mode: S7'.  Disable PHY clock isolation PHYRET_CFG.clk_iso_en <= 0  Disable Auto-clk-stp mode CLKSTP.clkstp_en <= 0 S4: Soft reset DDR PHY X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 269 Configure register to exit DCTL.SR <= 0 S17: Polling register to ensure ddrc exit self-refresh mode DDRC_STATUS.ddr_sr_mode = 0 S18: Perform Data training X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 270 CLKSTP_CFG.clkstp_en <= 1  ..others ..S21: Finish DDR is thoroughly get out of Retention mode. Change PC to DDR for normal operation. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 271 Both virtual spaces and physical spaces are 32-bit wide in this architecture. Virtual addresses are translated by MMU into physical address which is further divided into several partitions for static memory, SDRAM, and internal I/O. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 272 0x16000000 Reserved Space (16MB) 0x15000000 Reserved Space (16MB) 0x14000000 Internal I/O Space (64MB) 0x10000000 DRAM Space (256MB) 0x00000000 Figure 10-1 Physical Address Space Map X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 273 1 The 16KB address space from H‗1FC00000 to H‗1FC03FFF in bank 0 is mapped to on-chip boot ROM. The other memory spaces in bank 0 are not used. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 274 0x00001AFE 0x13410034 configuration register SACR2 Static memory bank 2 address 0x000018FE 0x13410038 configuration register SACR3 Static memory bank 3 address 0x000017FE 0x1341003c configuration register X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 275 For burst ROM, these bits specify the number of wait cycles to be inserted in first data read strobe X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 276 Address Hold Time. These bits specify the number of wait cycles to be inserted from negation of read/write strobe to address. TAH2~0 Wait cycle X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 277 These bits specify the bus width. This filed is writeable and are initialized to 0 by a reset. BW1~0 Bus Width 8 bits (Initial Value) Reserved Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 278 Programming overlapping bank regions will result in unpredictable error. These registers are initialized by a reset. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 279 Address Mask: Defines the mask of Static Bank n (n = 1 to 6). The initial values are: SACR1.MASK 0xFF SACR2.MASK 0xFF SACR3.MASK 0xFF SACR4.MASK 0xFF SACR5.MASK 0xFF SACR6.MASK 0xFF X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 280 There are some requirements for writes to flash memory. Flash memory space must be un-cacheable and un-buffered. Writes must be exactly the width of the populated Flash X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 281 Therefore, there is no negation period in case of access at minimum pitch. Figure 10-4 Basic Timing of Normal Memory Read X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 282 DDR Controller Figure 10-5 Basic Timing of Normal Memory Write Figure 10-6 Normal Memory Read Timing With Wait (Software Wait Only) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 283 4, 8, 16, or 32 with bits BL1~0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 284 WAIT# pin sampling is always performed when one or more wait states are set. Following figures show the timing of burst ROM. Figure 10-9 Burst ROM Read Timing (Software Wait Only) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 285 Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI  two data transfer mode: slave mode and DMA mode  Configurable 6 phases for software flow X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 286 SINGLE transfer is supported. 11.4.1.2 AHB Master Interface  transfer data in DMA mode  SINGLE, INCR, INCR4, INCR8, INCR16, INCR32 are supported. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 287 Figure 11-3 Sample point(has delay) 11.4.2.2 AC timing tSETUP(tSLCH), tHOLD(tCHSH), tSH(tSHSL) are configurable. sfc.ce … tSETUP tHOLD sfc.clk … … dev.do … Figure 11-4 AC timing X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 288 … … … … … command address dummy data sfc.dr … … … … … Full Dual I/O SPI Figure 11-6 Data Format(Dual SPI) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 289 Following chapter will descript the functions of all software accessible registers. Conventions: Register Address = Base + Address offset The registers can be read and written by AHB2 bus Register read/write attribute X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 290 DEV_ADR3 0x0000_0000 Base+0x003c Device address of phase3 0xFFFF_FFFF DEV_ADR4 0x0000_0000 Base+0x0040 Device address of phase4 0xFFFF_FFFF DEV_ADR5 0x0000_0000 Base+0x0044 Device address of phase5 0xFFFF_FFFF X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 291 1: DMA mode The number of phase in one flow. 001: 1 phase (default) PHASE_NUM 010: 2 phases 011: 3 phases 100: 4 phases X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 292 Hold time of SFC_CE, the time between the last edge of SFC_CLK and SFC_CE de-assertion. 12:11 THOLD 00: half SFC_CLK cycle (default) 01: one SFC_CLK cycle 10: one and a half SFC_CLK cycle X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 293 The default invalid level of SFC_HOLD pin HOLD_DL 0: low 1: high (default) The default invalid level of SFC_WP pin WP_DL 0: low 1: high (default) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 294 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Flash status mask for comparing. 31:0 DEV_STA_MSK 1: this bit will be checked. 0: this bit will not be checked. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 295 0: format0(default) 1: format1 The needed dummy cycle num (unit: SFC_CLK cycle) 000000: no dummy transfer (default) 22:17 DMY_BITS ..000100: 4 dummy cycles X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 296 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 297 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:3 Reserved Write has no effect. Read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 298 1: FIFO is over-run. This bit will generate the INT_OVER interrupt. 0: no error. UNDER 1: FIFO is under-run This bit will generate INT_UNDR signal. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 299 0: the INT_END is not masked MASK_END 1: the INT_END will be masked (default) 0: the INT_TREQ is not masked MASK_TREQ 1: the INT_TREQ will be masked (default) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 300 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 301 In all phases, only one phase can have DATA section.(we call this phase as data phase, other are command phase)  Sections in a phase will be operated by two sequence format: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 302 Repeat step 2 for other flow 11.8.3 One phase flow The flow can also be executed by only one phase. The NAND write perspective flow shown in the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 303 (PL) sfc.ce sfc.clk … … … … sfc.io … … … … command Dummy[3:0], address tran Configure the parameter of PL into phase0 registers: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 304 END bit zone 11.8.7 Example (NAND flash write with single phase in REG mode) configure SFC_DEV_CONF and SFC_GLB register program load (PL) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 305 Waiting END and clear. get features command to read the status sfc.ce sfc.clk … … … sfc.io … … … command address rece X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 306 Time from select pull high to select pull low. See a NOR Flash device spec tSLCH Time from select pull low to clock pull high. See a NOR Flash device spec X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 307 SYSTEM FUNCTIONS Section 6 SYSTEM FUNCTIONS X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 308 CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK frequency can be changed separately for  software by setting registers  MSC clock supports 50M clock Functional-unit clock gating  Random Number Generator  X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 309 CGU Block Diagram Following figure illustrates a block diagram of CGU. 32.768K SCLK_A L2CAHE 24M/ APLL AHB0 SCLK_M MPLL AHB2 SCLK_A SCLK_M SCLK_A other module SCLK_M X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 310 0x00000000 0x0070 LPCDR LCD pix clock divider Register 0x00000000 0x0064 MSC0CDR MSC0 clock divider Register 0x40000000 0x0068 MSC1CDR MSC1 clock divider Register 0x00000000 0x00A4 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 311 When switching clock source, it should be ensured that the clock switched from and the clock switched to both are running. 29:28 SEL_CPLL 00: stop MUX clock output X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 312 0, writes on H2DIV, PDIV have no affect. 19:16 PDIV Divider for Peripheral Frequency. Specified the PCLK division ratio. Bit 19~16: PDIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 X1/8 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 313 Divider for AHB0 Frequency. Specified the AHB0 CLK division ratio. Bit 11~8: H0DIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 X1/8 X1/9 X1/10 X1/11 X1/12 X1/13 X1/14 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 314 Import Note1 : for PDIV and AHB2DIV, AHB2’s clock frequency must be 1 or 2 times of PDIV’s clock frequency. For L2CDIV and CDIV, CPU’s clock frequency must be 1,2,3, or 4 times of X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 315 Software should be wait until H2DIV_BUSY == 0, then may begin another frequency change. H0DIV_B The bit is a read-only bit. It indicates whether the frequency change has X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 316 When DDR_STOP is 1 and CE_DDR is 1, the DDR clock will stop. When DDR_STOP is 0 and CE_DDR is 1, the DDR clock will continue. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 317 When MAC_STOP is 1 and CE_MAC is 1, the MAC clock will stop. When MAC_STOP is 0 and CE_MAC is 1, the MAC clock will continue. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 318 Recommend the De_p is less than 5% and De_n is great than -5%. If the parameter D of AIC M/N divider is in automatic calculation mode, namely I2S_DEN X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 319 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 320 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description MPCS 0: select SCLK_A clock output 1: select MPLL clock output X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 321 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 322 0: USB clock source is EXCLK 1: USB clock source is PLL output divided by USBCDR If UCS == 0, the clock divider is gated, don‘t set CE_USB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 323 SFC device clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on SSICDR.the clk relation ship of SFC and SSI is as follows: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 324 When the bit is 0, it indicates frequency change has finished., otherwise it indicates the frequency change is on going Software should be wait until SSI_BUSY == 0, may begin another X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 325 When the bit is 0, it indicates frequency change has finished., otherwise it indicates the frequency change is on going Software should be wait until CIM_BUSY == 0, may begin another frequency change. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 326 50%. Error of duty cycle is: De_p = (ceill( N / M) - (N / M)) / (N / M). ceil: Round toward positive infinity. and: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 327 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 328 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:3 Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 329 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 330 This bit is the power control for otg block in OTG PHY. 19:17 COMPDISTUNE These bits control disconnect threshold adjustment. 3‘b111 +4.5% 3‘b110 3‘b101 +1.5% 3‘b100 Default 3‘b011 -1.5% X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 331 +15mv 2‘b01 -15mv 2‘b00 reserved TXVREFTUNE These bits control HS DC voltage level adjustment. 4‘b1111 +12.5% 4‘b1110 +11.25% 4‘b1101 +10% 4‘b1100 +8.75% 4‘b1011 +7.5% X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 332 RST 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 333 11 PHYCLOCK cycles. Reserved Writing has no effect, read as zero. WORD_I This bit selects utmi data bus width of otg 1: 16bit/30M X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 334 PLL Stabilize Time. Specifies the PLL stabilize time by unit of RTCCLK (approximate 32kHz) cycles. It is used when change PLL multiplier or change PLL from off to on. It is initialized to H‘20. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 335 The PLL developed as a macro cell for clock generator. It can generate a stable high-speed clock from a slower clock signal. The output frequency is adjustable and can be up to 1000MHz. The PLL X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 336 PLL output frequency FOUT is calculated from the following equations: NF = 1+ M0 + M1*2 + M2*4 + M3*8 + M4*16 + M5*32 + M6*64 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 337 But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 338 0x00CC CLKGR Clock Gate Register0 0x1FFFFF80 0x 0020 OPCR Oscillator and Power Control Register 0x10801500 0x 0024 MESTSEL asnyc handshake control register 0x00000000 0x00EC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 339 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 340 The reset value of this register reflects the clock gate information of the relative modules. RST 0: After reset period, the clock is not stopped. RST 1: After reset period, the clock is stopped. Module Description X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 341 CPM will not wait for XX module‘s stop_ack if you stop it‘s clk by set CLKGR.XX. Note2: Scc‘s clk is 1/8 of exclk. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 342 28:26 Reserved Write has no effect, Read as 0 LCD_SR 0: LCD does not enter soft reset mode 1: LCD enters soft reset mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 343 Write has no effect, Read as 0 ERNG 0: not enable 1: enable 12.2.2.10 RNG Register (RNG) The RNG Register is a 32-bit read only registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 344 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 31:0 SLPC When SLBC is 1, sleep boot is jumped to SLPC, not true boot as any X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 345 DDRCDR.DCS is stopped in sleep mode 1: those clk is not stopped in sleep mode 21：20 Reserved Write has no effect, read as 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 346 When current operation of CPU core has finished and CPU core is idle, CCLK supply to CPU core is stopped. IDLE mode is exited by an interrupt (IRQ or on-chip devices) or a reset. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 347 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 348 Then WDT reset source is cleared because of internal reset. The internal reset is asserted for about 10 milliseconds. CPU and peripherals are clocked by EXCLK oscillator output directly. PLL is reset to off state. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 349 TCU2: It can work in sleep mode, but operated more complicated than TCU1 13.2 Pin Description Table 13-1 PWM Pins Description Name Description PWM [4:0] Output PWM channel output signals. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 350 Timer Counter Enable Clear 0x???? 0x018 Register Timer Flag Register 0x003F003F 0x020 TFSR Timer Flag Set Register 0x???????? 0x024 TFCR Timer Flag Clear Register 0x???????? 0x028 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 351 13.3.1 Timer Control Register (TCSR) The TCSR is a 16-bit read/write register. It contains the control bits for each channel. It is initialized to 0x00 by any reset. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 352 INITL Selects an initial output level for PWM output. 0: Low 1: High PWM_EN PWM output pin control bit. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 353 PCK_EN == 0, RTC_EN == 0 and EXT_EN == 1 < ½ f DIV_CLK PCLK (IN_CLK = EXTAL) PCK_EN == 1, RTC_EN == 0 and EXT_EN == 0 (IN_CLK = PCLK) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 354 But it can be cleared to 0 by setting TCSR.CLRZ to 1, and if the counter is really cleared, TCSR.CLRZ will be set to 0 by hardware. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 355 TCEN 3 Enable the counter in timer 3. 0: Stop counting up 1: Begin counting up TCEN 2 Enable the counter in timer 2. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 356 TCST 3 Set TCEN 3 bit of TER. 0: Ignore 1: Set TCEN 3 bit to 1 TCST 2 Set TCEN 2 bit of TER. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 357 TCCL 3 Set TCEN 3 bit of TER. 0: Ignore 1: Set TCEN 3 bit to 0 TCCL 2 Set TCEN 2 bit of TER. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 358 13.3.9 Timer Flag Set Register (TFSR) The TFSR is a 32-bit write-only register. It contains the comparison match flag set bits for all the channels. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 359 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 360 Writing has no effect, read as zero. FMASK 7~0 FULL comparison match interrupt mask. 0: Comparison match interrupt not mask 1: Comparison match interrupt mask X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 361 Writing has no effect, read as zero. 23:16 HMCL 7~0 Set HMASK n bit of TMR. 0: Ignore 1: Set HMASK n bit to 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 362 1: The clock supplies to timer 3 is stopped STOP 2 0: The clock supplies to timer 2 is supplied 1: The clock supplies to timer 2 is stopped X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 363 1: Set STOP 4 bit to 1 0: Ignore STPS 3 Set STOP 3 bit of TSR. 0: Ignore 1: Set STOP 3 bit to 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 364 Set STOP 5 bit of TSR. 0: Ignore 1: Set STOP 5 bit to 0 STPC 4 Set STOP 4 bit of TSR. 0: Ignore X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 365 1: The counter 2 is busy now BUSY1 0: The counter 1 is ready now 1: The counter 1 is busy now Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 366 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:19 Reserved Writing has no effect, read as zero. REALC 2 Clear REAL 2 bit of TSTR. 0: Ignore X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 367 Enable the counter. Setting the TESR.TCST bit to 1 to enable the TCNT. NOTE: The input clock and PCLK should follow the rules advanced before. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 368 13.4.5 Read Counter in TCU2 Mode If you want to read the data from register TCNT when the TCU is working, you can check X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 369 Writing TCSR.SD to setting the shutdown mode (Abrupt shutdown or Graceful shutdown). Writing TCSR.PRESCALE to set to 0. Setting TCNT, TDHR and TDFR. Enable the clock. Writing TCSR.PWM_EN to disable PWM. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 370 Enable the counter. Setting the TESR.TCST bit to 1 to enable the TCNT. NOTE: The input clock and PCLK should follow the rules adviced before. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 371 0 - reset to 0 ? - value unknown after reset Table 14-1 Registers Memory Map-Address Base Name Base Description SYS_OST 0x12000000 Address base of SYS_OST X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 372 Internal clock: CLK/16 Reserved These bits select the TCNT count clock frequency for ost1. Don‘t PRESCALE1 change this field when the channel is running. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 373 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:2 Reserved Writing has no effect, read as zero. OST2ENS Enable the counter in channel2‘s timer. 0: no effect X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 374 Write 1 at this bit to clear channel2's timer OST1CLR Clear the counter in channel1‘s timer. Write 1 at this bit to clear channel1's timer X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 375 Reserved Writing has no effect, read as zero. FFLAG channel1‘s FULL comparison match flag. (OST1CNT = OSTDFR) 0: Comparison not match 1: Comparison match X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 376 14.2.9 Operating System Timer Counter high 32 bits buffer (OSTCNT2HBUF) The operating system timer counter high 32 bits buffer OSTCNT2HBUF is used to store the high 32 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 377 OSTCCR third: Setting the OSTESR.TCST bit to 1 to enable the TCNT again. Setting the TESR.OSTST bit to 1 to enable the OSTCNT again. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 378 SPEC - special access method, relate to its description 3. Reset Value 1 - reset to 1 0 - reset to 0 ? - value unknown after reset X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 379 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 380 RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits Of ICMR0 Description The corresponding interrupt is not masked. The corresponding interrupt is masked. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 381 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 382 Will clear the corresponding interrupt mask bit. 15.2.9 Interrupt Controller Pending Register (ICPR0) This register contains the status of the interrupt sources after masking. This register is read only. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 383 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 384 The corresponding interrupt is active and is not masked to the processor. 15.2.14 Interrupt Source Register1 to PDMA (DSR1) This register contains status of all interrupts. A ―1‖ indicates the corresponding interrupt is pending. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 385 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 386 Execute the interrupt handler and unmask it by writing the register ICMCRx when exit the handler. CPU restores the saved environment and exits the interrupt state. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 387 0 - reset to 0 ? - value unknown after reset Table 16-1 Registers Memory Map-Address Base Name Base Description 0x10002000 Address base of WDT X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 388 Select PCLK as the timer clock input. 1: Enable 0: Disable NOTE: The input clock of timer and the PCLK should keep to the rules as follows: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 389 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 390 The clock of WDT can be stopped by setting register TSR, and register TSR can only be set by register TSSR or TSCR. The content of register TSR, TSSR and TSCR can be found in TCU spec. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 391 Features  Support up to 8 independent DMA channels  Descriptor or No-Descriptor Transfer mode compatible with previous Ingenic SOC  A simple Xburst-1 CPU supports smart transfer mode controlled by programmable firmware  Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte ...
  • Page 392 Channel n Command 0x14 + n*0x20 DDAn Channel n Descriptor Address 0x18 + n*0x20 DSDn Channel n Stride Difference 0x1C + n*0x20 17.4.2 Global Control Registers X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 393 MCU Interrupt 0x103C NOTES: Grey ones are obsolete registers defined in previous Ingenic SOC. They are relative to clock gating and have no real function, and they are not supported any longer. 17.5 DMA Channel Register Definition 17.5.1 DMA Source Address (DSAn, n = 0 ~ 7)
  • Page 394 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ？ ？ ？ ？ ？ ？ Bits Name Description 31:6 Reserved Write has no effect, read as zero. Transfer request type. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 395 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 396 RST 0 0 0 0 0 0 0 0 ？ ？ 0 0 ？ ？ ？ ？ ？ ？ ？ ？ 0 ？ ？ ？ 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 397 Programmer must care the detail of the FIFO of the device binding with relative DMA channel to set the correct and best recommended data unit value according to FIFO‘s data width and depth, refer to following table. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 398 4-byte; when setting non-autonomy (TSZ!=7), for transferred bytes in a bus transaction denoted by TSZ, it must not exceed the critical value of triggering DMA request meanwhile must be the times of 4-byte. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 399 RST ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 400 MSC(MSC1, MSC2), SSI(SSI1), UART0~4, AIC will be in fast mode. DMAE is a global switch, so software must be careful to toggle it from 0 to 1 or 1 to 0. It is X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 401 For example, write 0x00000001 to DDS, DDB0 bit is set to 1 and enable DMA channel 0 to fetch its first descriptor. Write 0 to DDS, no meaning. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 402 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 403 Description 31:0 DCPn Channel programmable enable. 0, compatible with previous Ingenic SOC; 1, firmware controlled channel 17.6.8 DMA Soft IRQ Pending (DSIRQP) DSIRQP BASE+0x 1020 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 404 1 immediately to raise an IRQ to MCU. Moreover, when an channel m with above attribute is bound with the INTC_IRQ, if DCIRQMm==0, an active INTC_IRQ request will trigger an active CIRQn immediately X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 405 Write has no effect, read as zero. 23:8 SC_OFF Set the offset of the caller‘s data structure for SC_CALL reserved Write has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 406 IRQ to main CPU when relative MASK field in DMINT is not set. Note that writing the register is inhibited by HW when DMCS.SCMD == 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 407 Available CP0 registers of MCU are not entirely compatible with MIPS PRA spec, they are listed below. CP0 Name Description (number) STATUS (12) Bit 31~27:: reserved, read as zero Bit26: readable; only 1 can bet written into*1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 408 CPU so that MCU can acknowledge a RESET exception, now MCU begins to run from the PC 0xF4000000. Following is a simple example. Prepare a simple RESET exception handler, total 3 instructions: WAIT //sleep //endless loop X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 409 0 to DCSn.CTE, and then safely clear DCSn.TT or DCSn.HLT to 0. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 410 Transfer Counter 5th (DES4) 31-16 Target Stride Address 15-0 Source Stride Address 6th(DES5) 31-6 Reserved DMA Request Type 7th(DES6) 31-0 Reserved 8th(DES7) 31-0 Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 411 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 412 DMA to let DMA rerun properly later. 17.8.3 Descriptor Transfer Interrupt/Stop control DMA descriptor provides a more fast and easy way to transfer data. Usually in a long descriptor X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 413 Note: DIP will raise if the two conditions satisfy, one is this is not the last descriptor, the other is the current TIE in DCMn or TIE in current descriptor is set. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 414 DSIRQM.SIRQMn must be set 0, then at expected moment, the MCU sets 1 to DSIRQP.SIRQn to trigger a soft IRQ. It is the responsibility of this soft IRQ‘s handler to remove the IRQ by setting 0 to DSIRQP.SIRQn. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 415 Alarm wakeup External pin wakeup with up to 2s glitch filter  18.3 Block Diagram PWRDET EXCLK/512 RTCLK RTCLK XRTCLK PPRST_ HIBER WKUP_ PWRON X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 416 RSW - read and write, but set to 1 by read RWC - read and write, clear to 0 by write 1, write 0 has no effect X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 417 Hibernate mode Wakeup Status Register in HWRSR 0x00000??? 0x030 Hibernate mode HSPR Scratch pattern register 0x???????? 0x034 WENR Write enable pattern register 0x00000000 0x03C X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 418 Write 1 to this bit is ignored. 1HZIE 1Hz interrupt enable. Writing to this bit takes effect immediately without delay. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 419 1Hz pulse if the real time clock is enabled (RTCCR.RTCE = 1). When read, it should be read continued more than once and take the value if the adjacent results are the same. RTCSR is not initialized by any reset. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 420 (any type of) resets. LOCK Description Write to RTCGR is allowed. Write to RTCGR is forbidden. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 421 The HIBERNATE mode Wakeup Filter Counter Register (HWFCR) is a 32-bit read/write register .It filter the glitch generated by a dedicated wakeup pin. The HWFCR is not initialized by any reset. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 422 The HIBERNATE Wakeup Control Register is a 32-bit read/write register that controls real time clock alarm wake up enable. The reset value only for PPRST_ . X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 423 APD is set and remains set until software clears it. This bit can only be X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 424 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 425 This is a register used to control the enable and set the judge time to reset the chip when extend press the WKUP pin. The are only initialized by PPRST_ and HRST_. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 426 Check RTCCR.WRDY, make sure it equals to 1 Write the target register Waiting RTCCR.WRDY equals to 1 to make sure the current write processing was finished. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 427 Check RSR to determine what caused the reset. Check PIN/ALM bits of HWRSR in order to know whether or not the power-up is caused by which wake-up from HIBERNATE mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 428 There could be two clock input to RTC internal clock called rtclk. One is OSC32k clock; the other is EXCLK/512. The software MUST make sure the RTC run in valid clock configuration. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 429 NOTE: If using HIBERNATE mode, MUST have both 32KHz crystal (or input 32Khz clock) and 24Mhz EXCLK crystal connected, or RTC time will be insignificant. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 430 RWS - read and write, set to 1 by write 1, write 0 has no effect RC - read only, and clear to 0 by read RS - read only, and set to 1 by read X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 431 RST 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 432 RD_STROBE Adjust number of h2clk cycles when EFUSE reading STROBE Signed value, h2clk period multiply(RD_ADJ + 3 + RD_STROBE) should greater than 15 ns. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 433 1: protect, security boot enable can write 0: no protect, security boot enable can't write DIS_JTAG Disable JTAG 1: disable JTAG 0: enable JTAG X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 434 2. The EFUSE 1K programmable bits are separated into thirteen segments as below table. The first Segment used to store Ingenic chip id, second segment store 128bit random number, third segment used to store customer id, forth segment store segment protect bit, fifth segment used to store root key, sixth segment used to store chip key, seventh used to sore user key, the last segment used to store NKU.
  • Page 435 6. Write control register WR_EN bit to 1 7. Wait status register WR_DONE set to 1. 8. Disconnect AVDEFUSE pin from 2.5V. 9. Write control register PG_EN bit to 0. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 436 Use on-chip counter and GPIO to coordinate external supply source. : Only the 1.3.2 flow can be used to program the User Key and NKU Segment, The Root key and Chip key Segment will be programmed at CP by Ingenic, other segments only can program use 1.3.1 flow.
  • Page 437 PERIPHERALS Section 7 PERIPHERALS X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 438 PA00, will decide is high level value value value default value the FUNC0 "sd0_(io-0)", "sd0" X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 439 PA28 PRUW08DGZ_G (i-0) sfc_dr(io-0) ssi0_dr(i-0) (i-0) PA29 PRUW08DGZ_G (i-0) sfc_dt(io-0) ssi0_dt(o) (i-0) PA30 PRUW08DGZ_G (i-0) sfc_wp(io-0) ssi0_ce1(o) (i-0) PA31 PRUW08DGZ_G (i-0) sfc_hold(io-0) ssi0_gpc(o) (i-0) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 440 PB31 is RTC WKUP pin, can only be used as input and interrupt, no pull-up and pull-down. The SLCD rd and ce function only can be used by set PB16/PB18 as normal GPIO function. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 441 The group is a dummy group which is not mapping to any on-chip ports. It is used to avoid 3rd (intermittent) state error during configuration. Please refer 1.4.5 and 1.4.6 for detailed information. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 442 Address base of GPIO Port B 0x10010200 Address base of GPIO Port C 0x10010300 Address base of GPIO Port D 0x10010700 Address base of GPIO Group Z (Shadow group) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 443 RW PORT B PULL Disable Register 0x70000000 0x70 PBPENS PORT B PULL Disable Set Register 0x00000000 0x74 PBPENC PORT B PULL Disable Clear Register 0x00000000 0x78 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 444 RW PORT D Pattern 1 Register 0x0000003F 0x30 PDPAT1S PORT D Pattern 1 Set Register 0x00000000 0x34 PDPAT1C PORT D Pattern 1 Clear Register 0x00000000 0x38 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 445 Where n = 0 ~ 31 and PAPINL n = PAPINL0 ~ PAPINL31. The PORT A PIN level can be read by reading PINL n bit in register PAPINL. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 446 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 447 MSKS n Writing 1 to MSKS n will set MSK n to 1 in register PAMSK. Writing 0 to MSKS n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 448 When INT n = 0 and MSK = 1 (GPIO function): 0: Corresponding pin is used as gpio output 1: Corresponding pin is used as gpio input X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 449 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 450 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 451 FLAGC n When GPIO is used as interrupt function and when write 1 to the bit, the bit FLAG n in PAFLG will be cleared. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 452 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 453 Where n = 0 ~ 31 and INT n = INT31 ~ INT00. Interrupt enable. 0: Corresponding pin is used as device functions or normal gpio 1: Corresponding pin is used as interrupt X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 454 RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 455 MSKC n Writing 1 to MSKC n will set MSK n to 0 in register PBMSK. Writing 0 to MSKC n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 456 PAT1S n Writing 1 to PAT1S n will set PAT1 n to 1 in register PBPAT1. Writing 0 to PAT1S n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 457 When INTn = 0 and MSK = 1 and PAT1 = 0: 0: Port is GPIO output 0 1: Port is GPIO output 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 458 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 459 Where n = 0 ~ 31 and PEN n = PEN0 ~ PEN31. PEN n is used for setting the port to be PULL function enable. 0: port PULL enable 1: port PULL disable X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 460 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 461 Writing 1 to INTS n will set INT n to 1 in register PCINT. Writing 0 to INTS n will no use. 20.4.3.4 PORT C Interrupt Clear Registers (PCINTC,0x18) PORT C GROUP interrupt clear registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 462 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 463 When INT n = 0 and MSK = 1 (GPIO function): 0: Corresponding pin is used as gpio output 1: Corresponding pin is used as gpio input X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 464 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 PAT0 n Where n = 0 ~ 31 and PAT0 n = PAT00 ~ PAT031. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 465 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 466 FLAGC n When GPIO is used as interrupt function and when write 1 to the bit, the bit FLAG n in PCFLG will be cleared. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 467 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 468 Writing 1 to GFCFG0S n will set glitch filter control signal GFCFG0 n to 0 in register PCGFCFG0. Writing 0 to GFCFG0S n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 469 Not every PAD support glitch filter control, please check out Function Overview chapter for details. 20.4.3.23 PORT C GLITCH FILTER Configure Register 1 (PCGFCFG1S,0x414) PORT C GROUP glitch filter control bit 1 set registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 470 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 471 Writing 1 to GFCFG2C n will clear glitch filter control signal GFCFG2 n to 0 in register PAGFCFG2. Writing 0 to GFCFG2C n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 472 Writing 0 to GFCFG3S n will no use. 20.4.3.30 PORT C GLITCH FILTER Configure Clear Register 3 (PCGFCFG3C,0x438) PORT C GROUP glitch filter control bit 3 clear registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 473 Not every bit for each port is implement this function. please refer 1.3. 20.4.4 PORT D Register Group 20.4.4.1 PORT D PIN Level Registers (PDPINL,0x00) PORT D GROUP level registers. They are read-only registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 474 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 475 1: Disable the pin as an interrupt source When INT n = 0: 0: Corresponding pin will be used as device function 1: Corresponding pin will be used as gpio X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 476 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 477 PAT1C n Writing 1 to PAT1C n will set PAT1 n to 0 in register PAPAT1. Writing 0 to PAT1C n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 478 PAT0S n Writing 1 to PAT0S n will set PAT0 n to 1 in register PAPAT0. Writing 0 to PAT0S n will no use. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 479 Not every PAD support Input Enable Control, please check out Function Overview chapter for details. 20.4.4.15 PORT D FLAG Clear Registers (PDFLGC,0x58) PORT D GROUP flag clear registers. They are read-only registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 480 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 481 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 482 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 483 Shadow register load to work groups Load to GPIO Port A Load to GPIO Port B Load to GPIO Port C Load to GPIO Port D Reserved Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 484 GPIOZ. When assert GPIOZ.LD, all the four registers will load their content into target group at the same time. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 485 PzINT, PzMSK, PzPAT0, PzPAT1 are also can be configured straightly. Step2: configure PzGID2LD to specify which port group to load PzGID2LD = 0x1; (0x1 stands for GPIO Port B) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 486 PA01/ PC27 I2C1 serial data SCL1 1-bit PA00/ PC26 I2C1 serial clock SDA2 1-bit PD01 I2C2 serial data SCL2 1-bit PD00 I2C2 serial clock X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 487 Fast speed I2C SCL high count 16bits 0x003C I2C_FLCNT 0x20 Fast speed I2C SCL low count 16bits 0x0082 I2C_INTST 0x2C I2C Interrupt Status 12bits 0x000 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 488 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 489 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CTAR 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 Bits Name Description X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 490 21.2.2.3 I2C_SAR (I2C Slave Address Register) I2C_SAR BASE + 0x08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 491 1: STOP is issued after the byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 492 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 Bits Name Description 15:0 I2CSHCNT This register must be set before any I2C bus transaction can take X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 493 This register can be written only when the I2C interface is disabled which corresponds to I2C_ENABLE[0] being set to 0. Writes at other X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 494 It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the I2C_CGC register. I2C stores the received data in the Rx buffer. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 495 Set during transmit if the transmit buffer is filled to I2C_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the I2C_DC register. When the module is X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 496 Writing has no effect, read as zero. MIGC These bits mask their corresponding interrupt status bits in the I2CINTST register. MISTT MISTP MIACT MRXDN MTXABT MRDREQ X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 497 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Bits Name Description 15:6 Reserved Writing has no effect, read as zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 498 Read this register to clear the RXUF interrupt (bit 0) of the I2C_INTST register. 21.2.2.16 I2C_CRXOF (I2C Clear RXOF Interrupt Register) I2C_CRXOF BASE + 0x48 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 499 Name Description 15:1 Reserved Writing has no effect, read as zero. CLRDREQ Read this register to clear the RDREQ interrupt (bit 5) of the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 500 I2C_CACT (I2C Clear ACTIVITY Interrupt Register) I2C_CACT BASE + 0x5C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 501 Name Description 15:1 Reserved Writing has no effect, read as zero. CSTT Read this register to clear the START interrupt (bit 10) of the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 502 TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. I2CENB Controls whether the I2C is enabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 503 Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 504 Contains the number of valid data entries in the transmit FIFO 21.2.2.28 I2C_RXFLR(I2C Receive FIFO Level Register) This register contains the number of valid data entries in the receive FIFO buffer. It is cleared X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 505 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:16 Reserved Reserved. 15:0 SDAHD I2C Hold Time. Sets the required SDA hold time in units of APB clock period. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 506 1: Slave has received a read command and some data exists in the XFIFO TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 507 Reset value: 0x0. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 508 I2C_DMATDLR (I2C DMA Transmit Data Level Register) I2C_DMACR BASE + 0x8c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 509 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t >= 250 ns must then be met. This will automatically be the case if the device does SU;DAT X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 510 The register is used to report the I2C hardware status when the I2C_ENABLE[0] is set from 1 to 0; that is, when I2C is disabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 511 I2CENB is set to 0 but has not taken effect. NOTES: If the remote I2C master terminates the transfer with a STOP X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 512 NOTE: It is important to note that the I2C should only be set to operate as an I2C Master, or I2C Slave, but not both simultaneously. This is achieved by ensuring that bit 6 (I2CSLAVE_DISABLE) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 513 21.3.2 Master Mode Operation This section includes the following topics:  ―Initial Configuration‖  ―Dynamic I2CTAR or I2C10BITADDR_MASTER Update‖  ―Master Transmit and Master Receive‖ X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 514 I2CTAR register. You can dynamically write to the I2CTAR register provided the following conditions are met: I2C is not enabled (I2CENB=0); I2C is enabled (I2CENB=1); X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 515 For instance, if the device is only going to be a master, there would be no need to set the slave address because you can configure X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 516 The timing interval used should be similar to that described in the previous step for the I2CINTST[5] register. Software writes to the I2C_DC register with the data to be written (by writing a ‗0‘ in bit 8). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 517 In the standard I2C protocol, all transactions are single byte transactions and the programmer responds to a remote master read request by writing one byte into the slave‘s TX FIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 518 NOTE: This step can be ignored if I2C is programmed to operate as an I2C slave only. The variable POLL_COUNT is initialized to zero. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 519 Figure 21-2 illustrates the behavior of the I2C when the Tx FIFO becomes empty while operating as a master receiver, as well as showing the generation of a STOP condition. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 520 Figure 21-5 illustrates operation as a master transmitter where the Stop bit of the I2C_DC register is set and the Tx FIFO is not empty X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 521 Figure 21-8 illustrates operation as a master receiver where the first command loaded after the Tx FIFO is allowed to empty and the Restart bit is set X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 522 I2C Controller Figure 21-8 Master Receiver — First Command Loaded After Tx FIFO Allowed to Empty/Restart Bit Set X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 523 Auto-character repeat in T=0 transmit mode.  Transforms inverted format to regular format and vice versa.  Support stop clock function in some power consuming sensitive applications.  X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 524 SCCDR 0x?? 0x10040000 SCCFDR 0x00 0x10040004 SCCCR 0x00000000 0x10040008 SCCSR 0x8000 0x1004000C SCCTFR 0x0173 0x10040010 SCCEGTR 0x00 0x10040014 SCCECR 0x00000000 0x10040018 SCCRTOR 0x00 0x1004001C X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 525 Transmit or Receive Select. 0 – Reception mode. 1 – Transmission mode. Auto-T2R support. T2R means Transmit turn to Reception. 0 – controlled by SW. 1 – controlled by HW. 28:26 Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 526 SCC clock stop. 0 – SCC has left or is leaving clock stop mode. 1 – SCC CLKSTP has entered or is entering clock stop mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 527 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 Bits Name Description 15:11 Reserved 10:0 Value of F/D. The initial value is 0x173(371). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 528 7 6 5 4 3 2 1 0 RTOR 0 0 0 0 0 0 0 0 Bits Name Description Retry times when parity error detected. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 529 Two slave select signal (SSI_CE0 / SSI_CE1) supporting up to 2 slave devices  Back-to-back character transmission/reception mode  Loop back mode for testing X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 530 FIFO. Read operations automatically target the receive FIFO, while write operations write data to the transmit FIFO. Both the transmit and receive FIFO buffers are 128 entries deep by 17 bits wide. As the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 531 While SSP and SPI are full-duplex protocols, Microwire uses a half-duplex master-slave messaging protocol. At the start of a frame, a 1 or 2-byte control message is transmitted from the controller to the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 532 SSI_CLK … (POL = 1) SSI_CE0/ SSI_CE1 (SSICR1.FRMHLn= 0) … SSI_DT … SSI_DR SSI_GPC Figure 23-3 SPI Single Character Transfer Format (PHA = 1) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 533 Back-to-back transfer is performed as transmit-only/full-duplex operation when transmit-FIFO is not empty before the completion of the last character‘s transfer or performed as receive-only operation. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 534 … SSI_CE0/ SSI_CE1 (SSICR1.FRMHLn = … SSI_DT … SSI_DR SSI_GPC Figure 23-5 SPI Frame Interval Mode Transfer Format (ITFRM = 0, LFST = 0) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 535 MSB first or LSB first. At the end of the transfer, SSI_DT retains the value of the last bit sent through the next idle period. 1 SSI_CLK period … SSI_CLK … SSI_CE0 SSI_DT SSI_DR Figure 23-7 TI’s SSP Single Transfer Format X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 536 … … … … … … … … … … … X1000/E IoT Application Processor Programming Manual … Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved. … … … … … … … … … … … …...
  • Page 537 … … SSI_CLK SSI_CE0 1 -- 16-bit command … SSI_DT 2 -- 17-bit data … SSI_DR Figure 23-11 National Microwire Format 2 Read Timing X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 538 The SSI has the following registers: one data, two control, one status, one bit-rate control, and two interval control registers. The table lists these registers. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 539 16, the maximum length of one written or read data (is defined in FLEN) can be 17. Transmit-FIFO only contain one read operation command once, or one X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 540 And do not output any valid signals on the pins. 0: normal SSI mode; 1: LOOP mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 541 SSI will stop the SSI_CLK and negate the SSI_CE0 / SSI_CE1 if necessary. To make sure present transfer is completed, user must read and get SSISR.END = 1 (or SSISR.BUSY = 0). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 542 3 more SSI_CLK cycle delay is added Reserved Writing has no effect, read as zero. ITFRM Frame during interval, selects if the Frame (SSI_CE0 /SSI_CE1) signal is X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 543 These bits set the bit length of every character to be transmitted/received. The maximum data length can be configured is 32 bits. For data length X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 544 1: Transmission and/or reception is in process This bit denotes transmit-FIFO is full or not. 0: Transmit-FIFO is not full 1: Transmit-FIFO is full X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 545 Counting clock source select. 0: Use SSI bit clock (SSI_CLK) as the interval counter clock source 1: Use 32K clock as the interval counter clock source X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 546 SSIICR is ignored for SSICR1.FMAT  B‘00. The desired transfer number of characters-per-frame is (SSIICR set value + 1). 23.7.8 SSI Clock Generator Register (SSIGR) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 547 RCNT, the receiving operation will be stopped automatically. 23.8 Software Guideline 23.8.1 Common flow The initial steps are: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 548 The convention used to interpret the bytes making up a data word when those bytes are stored in computer memory. See Endianness at Wikipedia FIFO First In, First Out, a method for organizing and manipulating a data buffer X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 549 Synchronous Serial Interface(SSI) See Endian See Endian Quad SPI See SPI Serial Peripheral Interface Standard SPI See SPI X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 550 UART; From PIN to receive the data processing and put it on the APB bus. For the transmission direction,UART gets the data from the APB bus and sent to the PIN. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 551 Clear to Send --- Modem Transmission enabled RTS_ Output Request to Send --- UART Transmission request NOTE: UART2, UART1, UART0 support RxD, TxD, RTS_, CTS_. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 552 Table 24-2 Registers Memory Map Base Address Name Base Description UART0 0x10030000 Address base of UART0 UART1 0x10031000 Address base of UART1 UART2 0x10032000 Address base of UART2 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 553 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ？ ？ ？ ？ ？ ？ ？ ？ Bits Name Description X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 554 Divisor is shown by the formula when UMR and UACR are not set: Baud Rate = (UART device clock) / (16 * Divisor) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 555 The UART Interrupt Enable Register (UIER) contains the interrupt enable bits for the five types of interrupts (receive data ready, timeout, line status, and transmit data request, and modem status) that set a value in UIIR. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 556 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 557 FIFO mode: Trigger FIFO mode: Reading URBR Highest Ready threshold was reached till below trigger threshold. Non-FIFO mode: URBR Non-FIFO mode: Empty full URBR X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 558 1: Enable UART DMA Mode Enable. 0: Disable DMA mode 1: Enable DMA mode TFRT Transmit Holding Register Reset. 0: Not reset 1: Reset transmit FIFO X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 559 0: Odd parity 1: Even parity PARE Parity Enable. Enables a parity bit to be generated on transmission or checked on reception. 0: No parity X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 560 RTS bit of the UMCR is connected to CTS bit of UMSR respectively. Loopback mode must be selected before the UART is enabled. 0: Normal operation mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 561 1: All the data in the transmit shifter and UTHR has been shifted out TDRQ Transmit Data Request. Set when UTHR has half or more empty location (FIFO mode) or empty X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 562 Set when both receive buffer and shifter are full and new data is received which will be lost. Cleared when the processor reads the ULSR. 0: No data has been lost 1: Receive data has been lost X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 563 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 564 IrDA decoder before it is fed to the UART (RCVEIR = 1) or bypass IrDA decoder and is fed directly to the UART (RCVEIR = 0). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 565 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:12 Reserved Writing has no effect, read as zero. 11:0 If the nth bit of the register is： X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 566 Description 31:7 Reserved Writing has no effect, read as zero. TCNT TXFIFO Counter. Indicates there are n data in TXFIFO when this field is X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 567 If ULSR.DRY = 1 or receive data request interrupt generates, then read ULSR.FIFOE or see if there is error interrupt, if FIFOE = 1, it means received data has receive error, then go to error X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 568 Each UART supports slow infra-red (SIR) transmission and reception by setting ISR.XMITIR and ISR.RCVEIR to 1 (make sure the two bits are not set to 1 at the same time because SIR can‘t operate X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 569 A 12-bit register is used to indicate where to insert the extra cycles. The first line is the time expected The second line is the time actual The third line is the time error X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 570 M+1 cycles to transmit or receive the bit To set UACR value you must ensure that the max error of each bit should be less than 0.5P X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 571 Write 0x408 to UACR ： cycle/bit M，M，M，M+1，M，M，M，M，M，M，M+1，M ： UACR 24.9 Index Table 24-5 Description of Proprietary Vocabulary Name Description UART universal asynchronous receiver/transmitter Serial infrared X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 572 Supports CE-ATA digital protocol commands  Support Command Completion Signal and interrupt to CPU  Command Completion Signal disable feature  The maximum block length is 4096bytes X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 573 CMD/DAT will return to push-pull mode, to have maximum driving for maximum operation frequency. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 574 Inactive State. The host then issue the command All_Send_CID (CMD2) to each card and get its unique card identification (CID) number. Card that is unidentified, that is, which is in Ready State, send X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 575 WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The status X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 576 To facilitate selection, a first command with the starting address is followed by a second command with the final address, and all sectors (or groups) within this range will be selected for erase. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 577 The password and its size is kept in an 128-bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase them. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 578 16-bit CRC. The data block shall indicate the mode (SET_PWD), the length (PWD_LEN) and the password itself. In case that a password replacement is done, then X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 579 (PWD_LEN is not 0), then the card will be locked automatically after power on reset. An attempt to lock a locked card or to lock a card that X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 580 (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previous issued command. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 581 An invalid selection of sectors or groups for erase occurred. 0: No Error 1: Error WP_VIOLATION E R X Attempt to program a write X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 582 The card could not sustain data programming in stream write mode. 0: No Error 1: Error CID/CSD_OVERWRITE E R X Can be either one of the following errors. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 583 0: No Ready 1: Ready Reserved APP_CMD The card will expect ACMD, or indication that the command has been interpreted as ACMD. 0: Disable X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 584 I/O device. I/O functions may be identical or completely different from each other. All I/O functions are organized as a collection of registers, and there is a maximum of 131,072 registers X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 585 SDIO device. To determine if a card supports the Read Wait protocol, the host must test capability bits in CCCR. The timing for Read Wait is base on the Interrupt Period. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 586 CMD16. The response to CMD56 will be R1b (card status + busy indication). 25.5 Pins Description  MSC_CLK, output, host to card clock signal.  MSC_CMD, inout, bidirectional command/response signal.  MSC_DAT[7:0], inout, bidirectional data bus. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 587 . . . Block length Figure 25-2 msc data format 25.7 Register Description Following chapter will describe the functions of all software accessible registers. Conventions: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 588 MSC_RDTO 0x00FFFFFF 0x14 MSC_BLKLEN 0x0000 0x18 MSC_NOB 0x0000 0x1C MSC_SNOB 0x???? 0x20 MSC_IMASK 0xFFFFFFFF 0x24 MSC_IFLG 0x2000 0x28 MSC_CMD 0x00 0x2C 0x00000000 0x30 MSC_ARG X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 589 CE_ATA device. After sending CMD12, MSC_STAT. AUTO_CMD12_DONE is set and generates interrupt to CPU. After sending the CCSD, controller automatically clears the SEND_AS_CCSD bit. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 590 RST 0 0 0 ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 591 Indicates whether data transmission to card has completed. 0: not completed 1: completed END_CMD_RES Indicates whether command and response/no-response sequence have been completed 0: not completed 1: completed X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 592 25.7.2.3 MSC Clock Rate Register (MSC_CLKRT,0x08) The MSC_CLKRT register specifies the frequency division of the MMC/SD bus clock. The software is responsible for setting this register. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 593 CCS from device 1: interrupts are enabled in CE_ATA device, or RW_BLK command expects command completion signal from device If the command expects Command Completion Signal X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 594 , RXFIFO_RD_REQ will be set to 1. 00: more than or equal to 16 01: more than or equal to 32 10: more than or equal to 64 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 595 It is also used to reset RX_FIFO and TX_FIFO. 0: Current command without data transfer 1: Current command with data transfer RESPONSE_FORMAT Response Type Selection. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 596 MMC/SD host controller turns on the time-out error for the received data. The unit is MSC_CLK. 25.7.2.7 MSC Block Size Register (MSC_BLKLEN,0x18) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 597 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 15:0 MSC_SNOB Specify the number of successfully transferred blocks for a multiple block transfer. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 598 Mask the interrupt of DMA end. 0: Not masked. 1: Masked. AUTO_CMD12_DONE Mask the interrupt AUTO_CMD12_DONE. 0: Not masked 1: Masked DATA_FIFO_FULL 0: Not masked X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 599 TXFIFO_WR_REQ, and RXFIFO_RD_REQ are masked off with the DMA function is used. The software is responsible for monitoring these bit in program I/O mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 600 Indicates the BAR interrupt. 0: the interrupt is not detected 1: the interrupt is detected Write 1 to clear. DMAEND Indicates the DMA end interrupt. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 601 Receive FIFO read request. Set if data FIFO becomes half full (the number of words is >= 8) or the entries in data FIFO are the last read data. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 602 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 603 The MSC_TXFIFO is used to write the data to a card. It is write-only to the software, and is written on 32-bit boundary. The size of this FIFO is 128 x 32-bit. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 604 Clock will stop when card in idle (should be normally set to only MMC and SD cards. For SDIO cards, if interrupts must be detected, clock should not be stopped) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 605 0: Special DMA in MSC controller is used 1: Common DMA in DMAC controller is used DMAEN DMA Function Enable 0: Disable DMA function 1:Enable DMA function X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 606 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 607 If the interrupt mask bit MSC_IMASK.DMAEND is 0b, the interrupt flag MSC_IFLG. DMAEND will be set to 1b also. 1: DMA will continue to fetch another descriptor. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 608 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 RTCNT This field indicates how many data in word units are stored in RTFIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 609 25.8.2 DMA and Program I/O Software may communicate to the MSC controller via the DMA or program I/O. The SDMA and CDMA X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 610 Step 1: Prepare the descriptor in system memory Step 2: If the address is not word boundary, it is suggested to configure MSC_DMAC.ALIGNEN and X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 611 Write MSC_CTRL with 0x01 to stop the MMC/SD bus clock. Wait until MSC_STAT[CLK_EN] becomes zero. To start the clock the software writes MSC_CTRL with 0x02. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 612 Step 1. Check whether SDIO card is inserted. Step 2. Check whether SDMEM card is inserted. Step 3. Check whether MMC cards are inserted. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 613 Because there may be several MMC card, so some steps (5 ~ 8) should be repeated several times. The commands are sent as follows: Step 1. Send CMD1 (SEND_OP_CMD) to validate voltage (the general OCR value is 0x00FF88000). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 614 MSC_IFLG [PROG_DONE] interrupt. This ensures that the card is not in the busy state. In addition, CMD26 (PROGRAM_CID), CMD27 (PROGRAM_CSD), CMD42 (LOCK/UNLOCK), CMD56 (GEN_CMD: write) and CMD53 (single block write) operations are similar to single block write. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 615 For SDIO card, CMD53 (multiple block write) is also similar, but when IO abort (CMD52) is sent, MSC_CMDAT [IO_ABORT] should be 1. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 616 Open-ended or SDIO Stop reading in advance (not Set MSC_CTRL [EXIT_MULTIPLE]. infinite write MSC_NOB blocks) Wait for DATA_TRAN_DONE interrupt. Send CMD12 or CMD52. (IO abort) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 617 If WRITE_BL_PARTIAL is not set, 16 more stuff bytes need to be written after the useful X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 618 Clear the MSC_CMDAT [INIT] bit. Start the operation. Write MSC_IMASK with some value to unmask the expected interrupts. Then the software must perform the following steps: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 619 Wait for the MSC_IFLG [DATA_TRAN_DONE] interrupt. Send STOP_TRANS (CMD12) or I/O abort (CMD52). Wait for the MSC_IFLG [END_CMD_ERS] interrupt. Wait for the MSC_IFLG [DATA_TRAN_DONE] interrupt. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 620 CMD16 SET_BLOCKLEN CMD17 READ_SINGLE_BLOCK CMD18 READ_MULTIPLE_BLOCK Open-ended CMD18 READ_MULTIPLE_BLOCK Predefine blocks CMD20 WRITE_DAT_UNTIL_STOP CMD23 SET_BLOCK_COUNT CMD24 WRITE_SINGLE_BLOCK CMD25 WRITE_MULTIPLE_BLOCK Open-ended CMD25 WRITE_MULTIPLE_BLOCK Predefine blocks X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 621 NOTE: For stream read/write, STOP_CMD is sent after finishing data transfer. For write, STOP_CMD is with the last six bytes. For read, STOP_CMD is sent after receiving data and card sends some data which MSC ignores. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 622 Supports INCR4, INCR8, INCR16, INCR, and SINGLE transfers on the AHB Slave interface   Software-selectable AHB burst type on AHB Master interface in DMA mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 623 Figure 26-2 OTG Internal DMA mode 26.3 Pin Description Table 26-1 OTG Pins Description Name Type Description Inout Data Positive Inout Data Minus Inout Identification DRVVBUS Charge pump enable X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 624 3FFFFh Figure 26-3 OTG CSR Memory Map 26.4.2 Register Maps The tables in this section provide high-level summaries of each register and register group. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 625 054h "Core LPM Configuration Register (GLPMCFG)" 0x58h Reserved GDFIFOCFG 05Ch "DFIFO Software Config Register (GDFIFOCFG)" GADPCTL 0x60h "ADP Timer, Control and Status Register (GADPCTL)" X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 626 Table 26-5 Device Mode CSR Map (800h-BFFh) Acronym Offset Address Register Name 800h-ACh Device Logical IN Endpoint-Specific Registers DCFG 800h Device Configuration Register (DCFG) DCTL 804h Device Control Register (DCTL) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 627 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn) 90Ch Reserved DIEPTSIZ0 910h Device Endpoint 0 Transfer Size Register (DIEPTSIZ0/DOEPTSIZ0) DIEPTSIZn 910h Device Endpoint-n Transfer Size Register (DIEPTSIZn/DOEPTSIZn) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 628 F000h-FFFCh WO/RO Access Device OUT Endpoint 14/Host IN Channel 14: DFIFO Read Access Device IN Endpoint 15/Host OUT Channel 15: DFIFO Write 10000h-10FFCh WO/RO X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 629 Register field can be read by the application (Read), can be set to 1'b1 by Self Clear or Write the core on certain internal or USB or AHB events (Self Set), and can be X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 630 Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 631 UTMI+ PHY with an 8- or 16-bit interface. 1'b0: 8 bits 1'b1: 16 bits "Host Configuration This register configures the core after power-on. Do not make X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 632 The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.  2'b00: DATA0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 633 USB host to which the core is connected. See "Device Initialization" in the Programming Guide for details. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 634 Table 26-8 Control and Status Register: GOTGCTL Field Description Mode Reset Access 31:26 Reserved Host and Device Chirp On Enable (ChirpEn) Device 1'b0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 635 Note: If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 636 B-Peripheral Session Valid OverrideValue (BvalidOvVal) Device 1'b0 This bit is used to set the Override value for Bvalid signal only when GOTGCTL.BvalidOvEn is set. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 637 1'b0 The application sets this bit to initiate a session request only on the USB. The application can clear this bit by writing a X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 638 Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). A-Device Timeout Change (ADevTOUTChg) Host and 1'b0 R_SS_W The core sets this bit to indicate that the A-device has Device X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 639 Mode Reset Access 31:25 Reserved Host and Device 1‘b0 Inverse Descriptor Endianness(InvDescEndianness) Host and 1'b0: Descriptor endianness is similar to the AHB Master Device X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 640 Host and 1'b0 This bit is programmed to enable the functionality to wait Device for the system DMA Done Signal for the DMA Write X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 641  1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty  1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 642  1'b0: Mask the interrupt assertion to the application.  1'b1: Unmask the interrupt assertion to the application. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 643 IC_USB TrafficPullRemove Control (IC_USBTrafCtl) Device 1'h0 When this bit is set, pullup/pulldown resistors are detached from the USB during traffic signaling, per section 6.3.4 of the IC_USB X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 644 SRP.  1'b0: Data line pulsing using utmi_txvalid (default).  1'b1: Data line pulsing using utmi_termsel. ULPI External VBUS Indicator (ULPIExtVbusIndicator) Host 1'b0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 645 In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.  1'b0: 480-MHz Internal PLL clock  1'b1: 48-MHz External Clock X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 646 PHY domain must be tied to the appropriate values. ULPI DDR Select (DDRSel) Host and 1'h0 The application uses this bit to select a Single Data Rate Device X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 647 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 648 Non-periodic TxFIFO flush in Host mode Non-periodic TxFIFO flush in device mode when in shared FIFO operation Tx FIFO 0 flush in device mode when in dedicated FIFO mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 649 The application must only write to this bit after checking X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 650 Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed.  Any transactions on the AHB Master are terminated X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 651 Field Description Mode Reset Access Resume/Remote Wakeup Detected Interrupt (WkUpInt) Host 1'b0 R_SS_W Wakeup Interrupt during Suspend(L2) or LPM(L1) state.  During Suspend(L2): Device X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 652 LPM- Capable (LPMCap) field is set to 1 and the User HW Config3 register's OTG_ENABLE_LPM bit is set Periodic TxFIFO Empty (PTxFEmp) Host 1'b1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 653 For example, after detecting an endpoint mismatch, the application:  Sets a global non-periodic IN NAK handshake X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 654 OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 655 USB Reset (USBRst) Device 1'b0 R_SS_W The core sets this bit to indicate that a reset is detected on only X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 656 Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 657 Current Mode of Operation (CurMod) Host 1'b0 Indicates the current mode.  1'b0: Device mode Device  1'b1: Host mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 658 This bit is enabled only when device periodic endpoints are enabled in Dedicated TxFIFO mode. OUT Endpoints Interrupt Mask (OEPIntMsk) Device 1'b0 only IN Endpoints Interrupt Mask (IEPIntMsk) Device 1'b0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 659 Reserved Host and Device 26.5.3.8 Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP)  Offset for Read: 01Ch  Offset for Pop: 020h X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 660 This is the least significant 4 bits of the (micro)frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 661 The application can program the RAM size and the memory start address for the Non-periodic TxFIFO. Note: The fields of this register change, depending on host or device mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 662 Description Reset Access 31:24 Top of the Non-periodic Transmit Request Queue (NPTxQTop) 7'b0 Entry in the Non-periodic Tx Request Queue that is currently being X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 663 This 32-bit field uses two bits per endpoint to determine the endpoint direction. Endpoint  Bits [31:30]: Endpoint 15 direction  Bits [29:28]: Endpoint 14 direction X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 664  2'b10: 8  Others: Reserved This field is configured using parameter "Name: OTG_NPERIO_TX_QUEUE_DEPTH". Reserved Multi Processor Interrupt Enabled (MultiProcIntrpt) Configurable  1'b0: No X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 665 1'b0: Multi-point application (hub and split support) 1'b1: Single-point application (no hub and no split support) This field is configured using parameter "Name: OTG_SINGLE_POINT". X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 666  0 - No Battery Charger Support  1 - Battery Charger support present. OTG_ENABLE_HSIC HSIC mode specified for Mode of Operation in coreConsultant X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 667 The application uses this bit to indicate the DWC_otg core's OTG capabilities.  1'b0: Not OTG capable  1'b1: OTG Capable This field is configured using parameter "Name: OTG_MODE". X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 668 OTG_EN_DESC_DMA". 29:26 Number of Device Mode IN Endpoints Including Control Endpoints Configurable (INEps) Range 0 -15  0:1 IN Endpoint  1:2 IN Endpoints X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 669 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width Configurable (PhyDataWidth) When a ULPI PHY is used, an internal wrapper converts ULPI to UTMI+.  2'b00: 8 bits X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 670 "FIFO RAM Allocation" in the Programming Guide. The DWC_otg core does not have any corrective logic if the FIFO sizes are programmed incorrectly. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 671 The power- on reset value of this register is the sum of the Largest Rx Data FIFO Depth, Largest Non-periodic Tx Data FIFO Depth, and all lower numbered Largest Device Mode Periodic Tx Data FIFOn Depth specified . X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 672 OTG_TX_DINEP_DFIFO_DEPTH_ 1. 26.5.4 Host Mode Registers These registers affect the operation of the core in the Host mode. Host mode registers must not be X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 673 NOTE: This bit must be modified only once after a reset. The following combinations are available for programming:  GAHBCFG.DMAEn=0, HCFG.DescDMA=0 => Slave mode X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 674 48MHZ. When you select a 6 MHz clock during LS Mode, you must do a soft reset (for 1.1 FS transceiver Interface)  Others: Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 675 26.5.4.3 Host Frame Number/Frame Time Remaining Register (HFNUM)  Offset: 408h This register indicates the current frame number. It also indicates the time remaining (in terms of the number of X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 676 Periodic Transmit Request Queue. This queue holds both IN and OUT requests.  8'h0: Periodic Transmit Request Queue is full  8'h1: 1 location available  8'h2: 2 locations available X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 677 Reset Access 31:16 Reserved 15:0 Channel Interrupt Mask (HAINTMsk) 16'h0 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 678 2'b0 Indicates the current logic level USB data lines  Bit [10]: Logic level of D+  Bit [11]: Logic level of D- Reserved X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 679 1'b1: Resume driven When LPM is enabled and the core is in the L1 (Sleep) state, setting this bit results in the following behavior: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 680 26.5.4.7.1 Moving the Host Core to Test Mode To move the DWC_otg core to test mode, you must set HPRT.Port Test Control. Complete the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 681 This field is not applicable for Scatter/Gather DMA mode and need not be programmed by the application and is ignored by the core. 28:22 Device Address (DevAddr) 7'h0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 682 1'b0: OUT  1'b1: IN 14:11 Endpoint Number (EPNum) 4'h0 Indicates the endpoint number on the device serving as the data source or sink. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 683 Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 684 Bit stuff error  False EOP In Scatter/Gather DMA mode, the interrupt due to this bit is not set. NYET Response Received Interrupt (NYET) 1'b0 R_SS_WC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 685  Offset: 50Ch + (Channel_number * 20h) This register reflects the mask for each channel status described in the previous section.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 686 Host Channel-n Transfer Size Register (HCTSIZn)  Channel_number: 0n15  Offset: 510h + (Channel_number * 20h) In Scatter/Gather DMA mode, the HCTSIZn register is defined as described inTable 26-40. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 687 SCHED_INFO (Schedule information) 8'h0 Every bit in this 8 bit register indicates scheduling for that microframe. Bit 0 indicates scheduling for 1 st microframe and bit X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 688  Offset: 514h + (Channel_number * 20h) This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 689 0 to 63. (Non 0 - 1 descriptor. lsoc) 63- 64 descriptors. This field indicates the current descriptor processed in the list. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 690 Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device Mode registers fall into two categories: Device Logical IN Endpoint-Specific Registers X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 691 When the Scatter/Gather DMA option selected during configuration of the RTL, the application can set this bit during initialization to enable the Scatter/Gather DMA operation. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 692 32 KHz during a suspend. This bit can only be set if USB 1.1 Full-Speed Serial Transceiver Interface has been selected. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 693 1'b0: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 694 1: Packets are not flushed when an ISOC IN token is received for an elapsed frame. The core ignores the frame number, sending packets as soon as the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 695 The application must set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 696 USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 697 When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 698 IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 699 31:15 Reserved NYET Interrupt Mask (NYETMsk) 1'h0 NAK Interrupt Mask (NAKMsk) 1'h0 Babble Interrupt Mask (BbleErrMsk) 1'h0 11:10 Reserved BNA interrupt Mask (BnaOutIntrMsk) 1'h0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 700 However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 701 This bit is set when the write pointer wraps. It is cleared when the learning queue is cleared. Reserved IN Token Queue Write Pointer (INTknWPtr) 5'h0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 702 A read from this register returns the last 8 endpoint entries of the learning queue. Table 26-55 Device IN Token Sequence Learning Queue Register 4: DTKNQR4 Field Description Reset Access 31:0 Endpoint Token (EPTkn) 32'h0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 703 This register is valid only for device mode in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO=1). Thresholding is not supported in Slave mode and so this register must not be programmed in Slave mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 704 When the value of AHBThrRatio is 2'h00, the threshold length must be at least 8 DWORDS. If the AHBThrRatio is nonzero, the application must ensure that X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 705  Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).  The interrupt is automatically cleared once the DOEPINTn / DIEPINTn interrupt is cleared by the application. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 706 Device Each In Endpoint-n Interrupt Register (DIEPEACHMSKn)  Offset 840h  Endpoint_number: 0=< n =< 15  Offset for IN endpoints: 840h + (Endpoint_number * 4h) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 707 DOEPINTn register can be masked by writing 0 to the corresponding bit in this register. Status bits are masked by default.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 708 The core clears this bit before setting the following interrupts on this endpoint:  Endpoint Disabled  Transfer Completed Endpoint Disable (EPDis) 1'b0 R_WS_SC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 709 USB Active Endpoint (USBActEP) 1'b1 This bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 710 1'b0 A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 711 2'b00: 64 bytes  2'b01: 32 bytes  2'b10: 16 bytes  2'b11: 8 bytes 26.5.5.22 Device Endpoint-n Control Register (DIEPCTLn/DOEPCTLn)  15  Endpoint_number: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 712 Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 713 Otherwise, a separate periodic FIFO must be allocated for an interrupt IN endpoint, and the number of this FIFO must be programmed into the TxFNum field. Configuring an interrupt IN endpoint as a non-periodic X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 714 IN endpoint, even if there data is available in the TxFIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 715 Endpoint Enable (EPEna) bit is low. This field is not valid in Slave mode operation. Note: This field is valid only for Shared FIFO operations. 10:0 Maximum Packet Size (MPS) 11'h0 X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 716 Core to process, such as Host busy or DMA done. Dependency: This bit is valid only when Scatter/Gather DMA mode is enabled. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 717 IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. Status Phase Received For Control Write (StsPhseRcvd) This interrupt is X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 718 Applies to IN and OUT endpoints. This bit indicates that the endpoint is disabled per the application's request. Transfer Completed Interrupt (XferCompl) 1'b0 R_SS_WC X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 719 The core decrements this field every time a packet from the external memory is written to the TxFIFO. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 720 USB. The core uses this field to calculate the data PID for isochronous IN endpoints.  2'b01: 1 packet  2'b10: 2 packets X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 721 RxFIFO and written to the external memory. Note: Note for Descriptor DMA The maximum transfer size supported is 219 bytes X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 722 Holds the current buffer address.This register is updated as and when programmed the data transfer for the corresponding end point is in progress. as the X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 723 DMA Mode bit (applicable only when the OTG_ARCHITECTURE ❑ parameter is set to Internal/External DMA) AHB Burst Length field (applicable only when the OTG_ARCHITECTURE ❑ parameter is set to Internal/External DMA) X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 724 The application must meet the following conditions to set up the device core to handle traffic: In Slave mode, GINTMSK.NPTxFEmpMsk, and GINTMSK.RxFLvlMsk must be unset. ■ In DMA mode, the GINTMSK.NPTxFEmpMsk, and GINTMSK.RxFLvlMsk ■ interrupts must be masked. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 725 DAINTMSK.INEP0 = 1 (control 0 IN endpoint) ❑ DAINTMSK.OUTEP0 = 1 (control 0 OUT endpoint) ❑ DOEPMSK.SETUP = 1 ❑ DOEPMSK.XferCompl = 1 ❑ X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 726 SETUP packet. In Scatter/Gather DMA mode, the descriptors must be set up in memory before enabling the endpoint. DOEPCTL0.EPEna = 1 ❑ X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 727 OUT transaction or to be expected from the first IN transaction). Program the Transfer Size field so that the channel‘s transfer size is a multiple of X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 728 (GINTSTS.PrtInt) to the application. When GINTSTS.PrtInt is triggered, the application reads the HPRT register to check if the HPRT.Port Connect Detected (PrtConnDet) bit is set or not. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 729 Full-duplex and half-duplex operation  MDIO Master interface for PHY device configuration and management  remote wake-up frame and magic packet frame processing  X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 730 BOOT Section 8 BOOT X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 731 12KB code from MMC/SD card to tcsm and jump to it. NOTE: The X1000/E's tcsm is 16KB, its address is from 0xf4000000 to 0xf4004000. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 732 XBurst Boot ROM Specification Figure 28-1 Boot sequence diagram of X1000/E X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 733 256 bytes space of the MBR. When NAND boot, the parameters will be placed at the end of the SPL signature. SPL Parameters‘s location and structure show below: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 734 The length of SPL in bytes, and must be 512 byte aligned. the size of SPL must be not more than 26K. CPU freq： Cpu frequency conversion value in HZ. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 735 Polling Value Addr(This is lower 16 bits address , th higher 16bit address is 0xb000). The configuration value of the ―saddr‖ register value: poll_h: Polling high bit mask(32bit). poll_l: Polling low bit mask(32bit). X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 736 SUCCESS poll_h != 0 while(!(*paddr & poll_h)) poll_l != 0 while(*paddr & poll_l) cnt of desc == 14? Figure 28-4 SPL configuration change Procedure X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 737 Branch to internal Stage 4. SRAM. The target Program Start address is specified by Control transfer the request. Bulk transfer Figure 28-5 USB Communication Flow X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 738 VR_FLUSH_CACHES (0x03) and VR_PROGRAM_START2 (0x05) to let the CPU to execute the new program. Next figure is the typical procedure of USB boot. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 739 Send VR_FLUSH_CACHES to flush D caches Send VR_PROGRAM_START2 Figure 28-6 Typical Procedure of USB Boot Following tables list all the vendor requests that USB boot program supports: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 740 Table 28-7 Vendor Request 3 Setup Command Data Structure Offset Field Size Value Description bmRequestType D7 0: Host to Device. D6-D5 2: Vendor. D4-D0 0: Device. bRequest VR_FLUSH_CACHES: flush I-Cache and D-Cache. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 741 MSC0_CLK, MSC0_CMD as function pins. Only one data pin MSC0_D0 is used. Then the boot program sends CMD55 to test if it‘s SD or MMC card and initializes the card. At last it loads 12KB code X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 742 SPL Structure show below , SPL signature fist 4 bytes is sd card magic code is used for Identification of SD,the remaining of the signature is unused and filled with 0xff. The first 512 byte of MBR store cpu X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 743 ―SFC Boot Procedure‖ Note: Any irregularity in boot steps, SPI_boot will disable SFC controller and jump to MSC1 boot. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 744 16 bytes that agreed SPI boot flag. The SPI boot flag information table and procedure of the T10 SPI NOR boot is shown as follow: X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 745 :The bytes per page of SPI Nand, the value is X/1024, for example, the bytes per page is 2048, then bpp is 2048/1024=2. 0x0C~0x0F :The length of copy data. X1000/E IoT Application Processor Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

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