Ingenic JZ4780 Manuals

Manuals and User Guides for Ingenic JZ4780. We have 2 Ingenic JZ4780 manuals available for free PDF download: Programming Manual, Design Manual

Ingenic JZ4780 Programming Manual

Ingenic JZ4780 Programming Manual (893 pages)

Mobile Application Processor

Brand: Ingenic | Category: Computer Hardware | Size: 16 MB

Table of Contents

Table of Contents

3
Tables

27
- Figures
  
  33
  - Section 1 Overview
    37
- Overview
  
  38
  - Block Diagram
    39
  - Features
    39
    
    Cpu
    39
    
    Figure 1-1 JZ4780 Diagram
    39
    
    Gpu
    40
    
    Vpu
    40
    
    Display
    41
    
    Audio
    43
    
    Camera
    43
    
    Memory Interface
    45
    
    System
    45
    
    Peripheral
    47
    
    Bootrom
    50
  - Characteristic
    50
    
    Section 2 Core Functions
    51
- Cpu
  
  52
- Vpu
  
  59
  - Block Diagram
    59
  - Figure 3-1 VPU Block Diagram
    59
  - Features of VPU
    60
  - Table 3-1 VPU Features
    60
  - Internal Physical Address Base Definition
    61
  - Table 3-2 VPU Internal Physical Address Base Definition
    61
  - Aux
    62
    
    Register Definition
    62
  - Tcsm/Sram
    65
    
    TCSM/SRAM Space Usage
    65
  - Video Acceleration Block
    65
  - Table 3-3 TCSM/SRAM Space Usage
    65
- Gpu
  
  66
  - Graphics
    66
    
    Introduction
    66
    
    Powervr SGX Architecture - Key Features
    66
    
    SGX540 - 3D Features
    66
    
    SGX540 - Performance
    68
  - Extreme 2D
    68
    
    Overview
    68
    
    Registers Descriptions
    69
    
    Table 4-1 Register List
    69
  - Software Stack
    81
    
    Section 3 Display/Camera/Audio
    82
- LCD Controller
  
  83
  - Overview
    83
  - Pin Description
    84
  - Table 5-1 LCD Controller Pins Description
    84
  - Block Diagram
    85
  - Figure 5-1 Block Diagram When Use OSD Mode
    85
  - Figure 5-2 Block Diagram of TFT Mode (Not Use OSD)
    86
  - Figure 5-3 Block Diagram of HDMI Interface
    86
  - LCD Display Timing
    87
  - Figure 5-4 Display Parameters
    87
  - OSD Graphic
    88
    
    Color Key
    88
    
    Figure 5-5 OSD Graphic
    88
  - Register Description
    90
  - Table 5-2 LCD Controller Registers Description
    90
    
    Configure Register (LCDCFG)
    92
    
    Control Register (LCDCTRL)
    94
    
    OSD Configure Register (LCDOSDC)
    95
    
    Status Register (LCDSTATE)
    95
    
    OSD Control Register (LCDOSDCTRL)
    97
    
    OSD State Register (LCDOSDS)
    97
    
    Background0 Color Register (LCDBGC0)
    98
    
    Background1 Color Register (LCDBGC1)
    98
    
    Foreground Color Key Register 0 (LCDKEY0)
    98
    
    ALPHA Register (LCDALPHA)
    99
    
    Foreground Color Key Register 1 (LCDKEY1)
    99
    
    IPU Restart (LCDIPUR)
    100
    
    RGB Control (LCDRGBC)
    100
    
    Display Area Horizontal Start/End Point (LCDDAH)
    102
    
    Virtual Area Setting (LCDVAT)
    102
    
    Display Area Vertical Start/End Point (LCDDAV)
    103
    
    Foreground 0 XY Position Register (LCDXYP0)
    103
    
    Foreground 1 XY Position Register (LCDXYP1)
    103
    
    Foreground 0 Size Register (LCDSIZE0)
    104
    
    Foreground 1 Size Register (LCDSIZE1)
    104
    
    Vertical Synchronize Register (LCDVSYNC)
    104
    
    Horizontal Synchronize Register (LCDHSYNC)
    105
    
    PS Signal Setting (LCDPS)
    105
    
    CLS Signal Setting (LCDCLS)
    106
    
    REV Signal Setting (LCDREV)
    106
    
    SPL Signal Setting (LCDSPL)
    106
    
    Descriptor Address Registers (Lcddax)
    107
    
    Interrupt ID Register (LCDIID)
    107
    
    Frame ID Registers (Lcdfidx)
    108
    
    Source Address Registers (LCDSA)
    108
    
    DMA Command Registers (Lcdcmdx)
    109
    
    DMA OFFSIZE Registers (Lcdoffsx)
    110
    
    DMA Page Width Registers (Lcdpwx)
    110
    
    DMA Commend Counter Registers (Lcdcnumx)
    111
    
    DMA Commend Counter Registers (Lcdcposx)
    111
    
    Foreground X Size in Descriptor (Lcddessizex)
    112
    
    Priority Level Threshold Configure Register (LCDPCFG)
    113
    
    Dual LCDC Channel Control(LCDCDUALCTRL)
    114
    
    Image Enhancement CFG (LCDENH_CFG)
    114
    
    Color Space Conversion CFG (LCDENH_CSCCFG)
    115
    
    Luma Cfg (Lcdenh_Lumacfg)
    116
    
    Chroma0 Cfg (Lcdenh_Chrocfg0)
    117
    
    Chroma1 Cfg (Lcdenh_Chrocfg1)
    117
    
    Dither Cfg (Lcdenh_Dithercfg)
    117
    
    Enhance Status (LCDENH_STATUS)
    118
    
    Gamma Cfg (Lcdenh_Gamma)
    118
    
    Vee Cfg (Lcdenh_Vee)
    119
  - LCD Controller Pin Mapping
    119
    
    TFT and CCIR Pin Mapping
    119
    
    Data Mapping to GPIO Function
    121
  - Display Timing
    122
    
    Figure 5-6 General 16-Bit and 18-Bit TFT LCD Timing
    122
    
    General 16-Bit and 18-Bit TFT Timing
    122
    
    8-Bit Serial TFT Timing
    123
    
    Figure 5-7 8-Bit Serial TFT LCD Timing (24Bpp)
    123
    
    Special TFT Timing
    123
    
    Figure 5-8 Special TFT LCD Timing 1
    124
    
    Figure 5-9 Special TFT LCD Timing 2
    124
    
    Delta RGB Panel Timing
    125
    
    Figure 5-10 Delta RGB Timing
    125
    
    RGB Dummy Mode Timing
    125
  - Format of Frame Buffer
    126
    
    16Bpp
    126
    
    Figure 5-11 RGB Dummy Timing
    126
    
    16Bpp with Alpha
    127
    
    24Bpp
    127
    
    24Bpp Compressed
    127
  - Format of Data Pin Utilization
    128
    
    18-Bit Parallel TFT
    128
    
    8-Bit Serial TFT (24Bpp)
    128
  - LCD Controller Operation
    129
    
    Disabling the Controller
    129
    
    Enabling the Controller
    129
    
    Set LCD Controller AHB Clock and Pixel Clock
    129
    
    Ccir601/Ccir656
    130
    
    Frame Buffer
    130
    
    OSD Operation
    130
    
    Resetting the Controller
    130
    
    Descriptor Operation
    131
    
    IPU Direct Connect Mode
    132
    
    VGA Output
    132
- Smart LCD Controller
  
  133
  - Overview
    133
  - Structure
    133
  - Pin Description
    134
  - Register Description
    134
  - Table 6-1 SLCD Pins Description
    134
    
    SLCD Configure Register (MCFG)
    135
    
    SLCD Control Register (MCTRL)
    136
    
    SLCD Data Register (MDATA)
    137
    
    SLCD Status Register (MSTATE)
    137
  - System Memory Format
    138
    
    Command Format
    138
    
    Data Format
    138
  - Transfer Mode
    139
    
    DMA Transfer Mode
    139
    
    Register Transfer Mode
    140
  - Timing
    140
    
    Parallel Timing
    140
    
    Serial Timing
    141
  - Operation Guide
    141
    
    DMA Operation
    141
    
    Register Operation
    142
- Decompresser
  
  143
  - Overview
    143
  - Compress Method
    143
  - Operation Guide
    145
- Image Enhancement
  
  146
  - Overview
    146
  - Operation Guide
    146
- Image Process Unit
  
  147
  - Overview
    147
    
    Feature
    147
  - Block
    148
  - Data Flow
    148
    
    Figure 9-1 the Block about the Ipudata Flow
    148
    
    Input Data
    148
    
    Output Data
    148
    
    Resize Coefficients LUT
    148
  - Registers Descriptions
    149
  - Table 9-1 Register List
    149
    
    IPU Global Control Register
    150
    
    IPU OSD Control Register
    150
    
    IPU Frame Control Register
    151
    
    IPU Status Register
    152
    
    IPU Register Configure Enable Control Register
    153
    
    IPU Trigger Register
    153
    
    Data Format Register
    154
    
    Input y Data Address Register
    155
    
    Input U Data Address Register
    156
    
    Input V Data Address Register
    156
    
    Destination TLB Base Address
    157
    
    Input Source TLB Base Address
    157
    
    Input U Data Address of Next Frame Register
    158
    
    Input V Data Address of Next Frame Register
    158
    
    Input y Data Address of Next Frame Register
    158
    
    Destination TLB Base Address of Next Frame
    159
    
    Source TLB Base Address of Next Frame
    159
    
    ADDRESS Mapping
    160
    
    Input Geometric Size Register
    160
    
    Input UV Data Line Stride Register
    161
    
    Input y Data Line Stride Register
    161
    
    Output Frame Start Address Register
    161
    
    Output Data Address of Next Frame Register
    162
    
    Output Frame Offset on Screan Register
    162
    
    Output Data Line Stride Register
    163
    
    Output Geometric Size Register
    163
    
    CSC C0 Coefficient Register
    164
    
    CSC C1 Coefficient Register
    164
    
    CSC C2 Coefficient Register
    165
    
    CSC C3 Coefficient Register
    165
    
    CSC C4 Coefficient Register
    165
    
    Horizontal Resize Coefficients Look up Table Register Group
    166
    
    Resize Coefficients Table Index Register
    166
    
    Vertical Resize Coefficients Look up Table Register Group
    171
    
    Calculation for Resized Width and Height
    172
    
    CSC Offset Parameter Register
    173
  - IPU Operation Flow
    174
    
    Data out to Frame Buffer
    174
    
    Data out to Lcdc
    175
    
    Operation Example
    176
    
    Table 9-2 no Mapping Mode
    176
    
    Table 9-3 Mapping Mode
    177
  - Special Instruction
    178
    
    Color Convention Feature
    178
    
    Resizing Size Feature
    178
    
    Output Data Package Format (RGB Order)
    179
    
    Yuv/Ycbcr to RGB CSC Equations
    179
    
    Input Data Package Format (RGB Order)
    180
    
    Source Data Storing Format in External Memory (Separated YUV Frame)
    180
- LVDS Controller
  
  182
  - Overview
    182
  - Register Description
    182
    
    Table 10-1 LVDS Register Description
    182
    
    TXCTRL (LVDS Transmitter Control Register)
    182
    
    TXPLL0 (LVDS Transmitter's PLL Control Register 0)
    184
    
    TXECTRL (LVDS Transmitter's Enhance Control)
    185
    
    TXPLL1 (LVDS Transmitter's PLL Control Register 0)
    185
  - Operate Description
    186
    
    LVDS Output Amplitude Control
    186
    
    Operate Mode
    186
    
    Table 10-2 Operation Mode Description
    186
    
    Table 10-3 LVDS Output Amplitude Control
    186
    
    LVDS Input Clock Edge-Delay Control
    187
    
    Table 10-4 LVDS Output Swing Level Control
    187
    
    Table 10-5 LVDS Output Level Function
    187
    
    Table 10-6 LVDS_TX Clock Edge Delay Control
    187
    
    Output Data Start-Edge Control
    188
    
    PLL Feedback Divider Value Setting
    188
    
    PLL Input Divider Value Setting
    188
    
    Table 10-7 Output Data Start-Edge Calibration (1X Clock Mode)
    188
    
    Table 10-8 PLL Input Divider Configuration
    188
    
    LVDS-LCDC RGB Data Mapping
    189
    
    PLL Output Clock Frequency Setting
    189
    
    Table 10-10 PLL VCO Gain Calibration
    189
    
    Table 10-11 PLL Post Divider Configuration
    189
    
    Table 10-9 PLL Feedback Divider Configuration
    189
    
    VCO Gain Calibration
    189
    
    LVDS VESA/JEIDA Mode
    190
  - Operate Flow
    191
    
    Figure 10-1 VESA Mode LVDS Output Timing
    191
    
    Figure 10-2 JEIDA Mode LVDS Output Timing
    191
    
    Power down Mode
    191
    
    LVDS Output Mode
    192
    
    RGB CMOS Output Mode
    192
- Camera Interface Module
  
  193
  - Overview
    193
    
    Features
    193
    
    Pin Description
    193
    
    Table 11-1 Camera Interface Pins Description
    193
  - CIM Special Register
    194
    
    CIM Configuration Register (CIMCFG)
    194
    
    CIM Register Map
    194
    
    Table 11-2 CIM Registers
    194
    
    CIM Control Register (CIMCR)
    197
    
    CIM Control Register 2 (CIMCR2)
    198
    
    CIM Status Register (CIMST)
    200
    
    CIM Interrupt ID Register (CIMIID)
    202
    
    CIM Interrupt Mask Register (CIMIMR)
    202
    
    CIM Descriptor Address (CIMDA)
    203
    
    CIM Frame Buffer Address Register (CIMFA)
    203
    
    CIM DMA Command Register (CIMCMD)
    204
    
    CIM Frame ID Register (CIMFID)
    204
    
    CIM Window Size (CIMWSIZE)
    205
    
    CIM Frame Size Register (CIMFS)
    206
    
    CIM Window Offset (CIMWOFFSET)
    206
    
    CIM y DMA Command Register (CIMYCMD)
    207
    
    CIM y Frame Buffer Address Register (CIMYFA)
    207
    
    CIM Cb DMA Command Register (CIMCBCMD)
    208
    
    CIM Cb Frame Buffer Address Register (CIMCBFA)
    208
    
    CIM Cr DMA Command Register (CIMCRCMD)
    209
    
    CIM Cr Frame Buffer Address Register (CIMCRFA)
    209
    
    CIM TLB Control Register (CIMTC)
    210
    
    CIM TLB Index Register (CIMTINX)
    210
    
    CIM TLB Content Register (CIMTCNT)
    211
  - CIM Data Sampling Modes
    211
    
    Gated Clock Mode
    211
    
    Table 11-3 the Modes and the Corresponding Signals Used
    211
    
    ITU656 Interlace Mode
    212
    
    Figure 11-1 Typical BT.656 Vertical Blanking Intervals for 625/50 Video Systems
    213
    
    ITU656 Progressive Mode
    213
  - DMA Descriptors
    214
    
    4-Word Descriptor
    214
    
    Figure 11-2 ITU656 Progressive Mode
    214
  - Interrupt Generation
    215
  - Software Operation
    216
    
    Disable CIM
    216
    
    Enable CIM with DMA
    216
    
    Enable CIM Without DMA
    216
- AC97/I2S/SPDIF Controller
  
  217
- PCM Interface
  
  269
  - Overview
    269
  - Pin Description
    269
  - Table 13-1 PCM Interface Pins Description
    269
  - Block Diagram
    270
  - Register Description
    270
    
    PCM Control Register (PCMCTL)
    270
    
    Table 13-2 PCM Registers Description
    270
    
    PCM Configuration Register (PCMCFG)
    272
    
    Pcm Fifo Data Port Register (Pcmdp)
    273
    
    Pcm Interrupt Control Register (Pcmintc)
    273
    
    Pcm Interrupt Status Register (Pcmints)
    274
    
    Pcm Clock Divide Register (Pcmdiv)
    275
  - PCM Interface Timing
    276
    
    Figure 13-1 Short Frame SYN Timing (Shown with 16Bit Sample)
    276
    
    Short Frame SYN
    276
    
    Figure 13-2 Short Frame SYN Timing (Shown with 16Bit Sample)
    277
    
    Figure 13-3 Long Frame SYN Timing (Shown with 16Bit Sample)
    277
    
    Figure 13-4 Long Frame SYN Timing (Shown with 16Bit Sample)
    277
    
    Long Frame SYN
    277
    
    Multi-Slot Operation
    278
  - PCM Operation
    278
    
    Figure 13-5 Multi-Slot Frame SYN Timing (Shown with Two Slots and 8Bit Sample)
    278
    
    PCM Initialization
    278
    
    Audio Record
    279
    
    Audio Replay
    279
    
    Fifos Operation
    280
    
    Figure 13-6 Transmitting/Receiving FIFO Access Via APB Bus
    280
    
    Data Flow Control
    281
    
    PCM Serial Clocks and Sampling Frequencies
    281
    
    Figure 13-7 PCMCLK and PCMSYN Generation Scheme
    282
    
    Interrupts
    282
- Internal CODEC Interface
  
  283
  - Overview
    283
  - Features
    283
    
    Signal Descriptions
    284
    
    Table 14-1 CODEC Signal IO Pin Description
    284
    
    Block Diagram
    285
    
    Figure 14-1 CODEC Block Diagram
    285
    
    Figure 14-2 Internal CODEC Works with AIC
    285
    
    Application Schematic
    286
  - Mapped Register Descriptions
    287
    
    CODEC Internal Register Access Control (RGADW)
    287
    
    Table 14-2 Internal CODEC Mapped Registers Description (AIC Registers)
    287
    
    CODEC Internal Register Data Output (RGDATA)
    288
  - Operation
    289
    
    Access to Internal Registers of the Embedded CODEC
    289
    
    CODEC Controlling and Typical Operations
    289
    
    Pop Noise and the Reduction of It
    290
    
    Power Saving
    290
  - Timing Parameters
    291
  - C Parameters
    292
  - CODEC Internal Registers
    293
    
    CODEC Internal Registers
    294
  - Programmable Gains
    321
    
    Programmable Boost Gain: GIM
    321
    
    Programmable Digital Attenuation: GOD
    322
    
    Programmable Input Gain Amplifier: GID
    322
    
    Programmable Attenuation: GO
    323
    
    Programmable Bypass Path Attenuation: GI
    324
    
    Programmable Digital Mixer Gain: GIMIX and GOMIX
    324
    
    Gain Refresh Strategy
    325
  - Configuration of the Headphone Output Stage
    325
  - Out-Of-Band Noise Filtering
    325
  - Output Short-Circuit Protection (Headphone Output)
    326
    
    Capacitor-Coupled Headphone Connection
    326
    
    Indication of the Short Circuit Detection
    326
    
    Reset of Short Circuit Detection
    326
  - Sampling Frequency: FREQ
    326
  - Programmable Data Word Length
    327
  - Ramping System Note
    327
  - AGC System Guide
    328
    
    AGC Operating Mode
    328
    
    Figure 14-3 AGC Adjusting Waves
    329
    
    Figure 14-4 AGC Adjust Areas
    330
  - Digital Mixer Description
    331
  - Digital Microphone Interface
    332
  - Figure 14-5 Digital Microphone Interface Connection
    332
    
    Figure 14-6 Digital Microphone Timing Diagram at MCLK = 12 Mhz
    333
    
    Timing Diagram
    333
    
    Timings
    333
    
    Noise Template (TBC)
    334
  - CODEC Operating Modes
    334
  - Figure 14-7 Digital Microphone Modulation Noise Reference Spectrum
    334
    
    Figure 14-8 CODEC Power Diagram
    335
    
    Power-On Mode and Power-Off Mode
    335
    
    RESET Mode
    335
    
    SLEEP Mode
    336
    
    STANDBY Mode
    336
    
    Figure 14-9 DAC Gain up and Gain down Sequence
    337
    
    Initial All the Gain
    337
    
    Soft Mute Mode
    337
    
    Figure 14-10 ADC Gain up and Gain down Sequence
    338
    
    Power-Down Mode and ACTIVE Mode
    338
    
    Working Modes Summary
    338
    
    SYS_CLK Turn-Off and Turn-On
    339
    
    Anti-Pop Operation Sequences
    340
    
    Initialization and Configuration
    340
    
    Requirements on Outputs and Inputs Selection and Power-Down Modes
    340
    
    Start up Sequence (DAC)
    340
    
    Figure 14-11 Start up Sequence
    341
    
    Figure 14-12 Shutdown Sequence
    342
    
    Shutdown Sequence (DAC)
    342
    
    Start up Sequence (Line Input)
    343
    
    Shutdown Sequence (Line Input)
    344
    
    Avoid Quiet Ground Common Currents
    345
    
    Circuits Design Suggestions
    345
    
    Figure 14-13 Capacitor-Coupled Connection
    346
    
    Headphone Connection (Capacitor-Coupled)
    346
    
    Microphone Connection
    346
    
    Description of the Connections to the Jack
    349
    
    Figure 14-14 Ground Distributing
    349
    
    Figure 14-15 the Bottom Corner of Chip PCB Layer
    350
    
    PCB Considerations
    350
    
    Analog Characteristics
    351
    
    Line Input to Audio ADC Path
    351
    
    Audio DAC to Headphone Output Path
    352
    
    Audio DAC to Mono Line Output Path
    354
    
    Line Input to Headphone Output Path (Analog Bypass)
    354
    
    Micbias and Reference
    356
    
    Section 4 Memory Interface
    357
- DDR Controller
  
  358
  - Overview
    358
    
    Block Diagram
    358
    
    Supported DDR SDRAM Types
    358
  - Register Description
    359
  - Table 15-1 DDRC Register
    359
  - Figure 15-1 DDRC Block Diagram
    359
    
    Dstatus
    361
    
    Dcfg
    362
    
    Dctrl
    364
    
    Dlmr
    367
    
    DTIMING1,2,3,4,5,6 (DDR Timing Configure Register)
    369
    
    DREFCNT (DDR Auto-Refresh Counter)
    372
    
    DMMAP0,1 (DDR Memory Map Configure Register)
    373
    
    DDLP (DDR DFI Low Power Handshake Control Register)
    374
    
    DREMAP1,2,3,4,5 (DDR Address Remapping Register 1,2,3,4,5)
    375
    
    WCMDCTRL1 (Performance Wcmd Reorder & Grouping)
    376
    
    RCMDCTRL0 (Performance Rcmd Request Control)
    377
    
    RCMDCTRL1 (Performance Rcmd Request Control)
    379
    
    WDATTHD0 (Performance Wcmd Request Control)
    379
    
    IPORTPRI (Performance Priority Control)
    380
    
    WDATTHD1 (Performance Wcmd Request Control)
    380
    
    CHQOS0,1,2,3,4,5 (Performance Qos Control)
    382
    
    Cpm_Drcg
    383
  - Functional Description
    383
    
    DDRC and DDR2 Memory Initialization Sequence
    383
  - Change Clock Frequency
    384
    
    CPM Driven SELF-REFRESH Mode
    384
    
    Manually SELF-REFRESH Mode
    384
    
    DLL Bypass Mode
    385
  - Data Endian
    385
  - DDR Connection Diagrams
    385
    
    Connection to One 512Mb X16 DDR2 Device
    385
    
    Connection to Two 512Mb X16 DDR2 Devices
    386
- External NAND Memory Controller
  
  387
- BCH Controller
  
  421
  - Overview
    421
  - Table 17-1 BCH Registers
    421
  - Register Description
    423
    
    BCH Control Register (BHCR)
    423
    
    BCH Control Set Register (BHCSR)
    424
    
    BCH Control Clear Register (BHCCR)
    425
    
    BCH ENC/DEC Count Register (BHCNT)
    425
    
    BCH Data Register (BHDR)
    426
    
    BCH Parity Register (Bhparn, N=0, 1, 2, 3, 4, 5
    426
    
    BCH Error Report Register (Bherrn, N=0,1,2,3,4,5,6,7
    427
    
    BCH Interrupt Status Register (BHINT)
    428
    
    BCH Interrupt Enable Clear Register (BHINTEC)
    430
    
    BCH Interrupt Enable Set Register (BHINTES)
    430
    
    BCH Interrupt Enable Register (BHINTE)
    431
    
    BCH User TAG OUTPUT Register (BHTO)
    432
  - BCH Operation
    432
    
    Encoding Sequence
    432
    
    Figure 17-1 Block Diagram for BCH Encoding
    433
    
    Decoding Sequence
    434
    
    Figure 17-2 Block Diagram for BCH Decoding
    434
    
    Figure 17-3 BCH Decoding Data Flow
    435
    
    Section 5 System Functions
    436
- Clock Reset and Power Controller
  
  437
  - Overview
    437
    
    CGU Block Diagram
    438
    
    CGU Registers
    440
    
    Table 18-1 CGU Registers Configuration
    440
    
    Figure 18-1 Block Diagram of PLL
    476
    
    PLL Operation
    476
    
    Main Clock Division Change Sequence
    477
  - Power Manager
    477
    
    Low-Power Modes and Function
    477
    
    Register Description
    478
    
    Table 18-2 Power/Reset Management Controller Registers Configuration
    478
    
    Doze Mode
    491
    
    IDLE Mode
    492
    
    Power down Mode
    492
    
    SLEEP Mode
    492
  - Reset Control Module
    493
    
    Register Description
    493
    
    Power on Reset
    494
    
    WDT Reset
    494
- Timer/Counter Unit
  
  495
  - Overview
    495
  - Pin Description
    495
  - Register Description
    495
  - Table 19-1 PWM Pins Description
    495
    
    Timer Control Register (TCSR)
    497
    
    Timer Data FULL Register (TDFR)
    499
    
    Timer Counter (TCNT)
    500
    
    Timer Counter Enable Register (TER)
    500
    
    Timer Data HALF Register (TDHR)
    500
    
    Timer Counter Enable Set Register (TESR)
    501
    
    Timer Counter Enable Clear Register (TECR)
    502
    
    Timer Flag Register (TFR)
    503
    
    Timer Flag Set Register (TFSR)
    504
    
    Timer Flag Clear Register (TFCR)
    505
    
    Timer Mast Register (TMR)
    506
    
    Timer Mask Clear Register (TMCR)
    507
    
    Timer Mask Set Register (TMSR)
    507
    
    Timer Stop Register (TSR)
    508
    
    Timer Stop Set Register (TSSR)
    509
    
    Timer Stop Clear Register (TSCR)
    510
    
    Timer Status Register (TSTR)
    511
    
    Timer Status Clear Register (TSTCR)
    512
    
    Timer Status Set Register (TSTSR)
    512
    
    Timer Control Mode Register (TCUMOD)
    513
    
    Timer Fifo State Register (TFIFOSR)
    514
    
    Timer Fifo Write Data (TFWD)
    514
  - Operation
    515
    
    Basic Operation in TCU1 Mode
    515
    
    Basic Operation in TCU2 Mode
    515
    
    Disable and Shutdown Operation in TCU1 Mode
    515
    
    Disable and Shutdown Operation in TCU2 Mode
    516
    
    Read Counter in TCU2 Mode
    516
    
    Pulse Width Modulator (PWM)
    517
    
    Trackball Input Waveform Detect
    517
    
    Basic Operation in FIFO Mode 1
    518
    
    Basic Operation in FIFO Mode 2
    518
- Operating System Timer
  
  520
  - Overview
    520
  - Register Description
    521
    
    Operating System Control Register (OSTCSR)
    521
    
    Operating System Timer Data Register (OSTDR)
    522
    
    Operating System Timer Counter (OSTCNTH, OSTCNTL)
    523
    
    Operating System Timer Counter High 32 Bits Buffer (OSTCNTHBUF)
    523
  - Operation
    523
    
    Basic Operation
    523
    
    Disable and Shutdown Operation
    524
- Interrupt Controller
  
  525
- Watchdog Timer
  
  534
  - Overview
    534
  - Register Description
    534
    
    Watchdog Control Register (TCSR)
    534
    
    Watchdog Enable Register (TCER)
    535
    
    Watchdog Timer Counter (TCNT)
    536
    
    Watchdog Timer Data Register (TDR)
    536
  - Watchdog Timer Function
    536
- PDMA Controller
  
  538
  - Features
    538
  - Block Diagram
    538
  - Figure 23-1 Block Diagram of PDMA
    538
  - Memory Mapped Register Descriptions
    539
    
    DMA Channel Registers
    539
    
    Global Control Registers
    539
    
    Table 23-1 DMA Channel Registers (N=0~31)
    539
    
    Table 23-2 Global Control Registers
    539
  - DMA Channel Register Definition
    540
    
    DMA Source Address (Dsan, N = 0 ~ 31)
    540
    
    DMA Target Address (Dtan, N = 0 ~ 31)
    540
    
    DMA Transfer Count (Dtcn, N = 0 ~ 31)
    540
    
    DMA Request Types (Drtn, N = 0 ~ 31)
    541
    
    Table 23-3 Transfer Request Types
    541
    
    DMA Channel Control/Status (Dcsn, N = 0 ~ 31)
    542
    
    DMA Channel Command (Dcmn, N = 0 ~ 31)
    543
    
    Table 23-4 Available RDIL
    544
    
    DMA Descriptor Address (Ddan, N = 0 ~ 31)
    548
    
    DMA Stride Difference (Dsdn, N = 0 ~ 31)
    548
  - DMA Global Register Definition
    548
    
    DMA Control
    548
    
    DMA Doorbell (DDB)
    550
    
    DMA Doorbell Set (DDS)
    550
    
    DMA Interrupt Pending (DIRQP)
    550
    
    DMA Channel Programmable (DMACP)
    551
    
    DMA Soft IRQ Pending
    551
    
    DMA Channel IRQ Pending to MCU
    552
    
    DMA Channel IRQ to MCU Mask
    552
    
    DMA Soft IRQ Mask
    552
    
    Programmable Channel Bound with INTC_IRQ
    553
    
    Special Channel 0 and Channel 1
    553
  - Mcu
    554
    
    MCU Control & Status
    554
    
    MCU Normal Mailbox
    554
    
    MCU Interrupt
    555
    
    MCU Security Mailbox
    555
    
    CP0 Registers of MCU
    556
    
    Multiple Bank Tightly Coupled Sharing Memory
    556
    
    Security ROM & Security RAM
    556
    
    Table 23-5 TCSM Space
    556
    
    How to Boot MCU up
    557
    
    Normal Exceptions Accepted by MCU
    557
    
    Securitycall Accepted by MCU
    557
    
    Interruptable SMD Mode
    558
  - DMA Manipulation
    559
    
    Descriptor Transfer Mode
    559
    
    Table 23-6 Descriptor Structure
    560
    
    Figure 23-2 Descriptor Transfer Flow
    561
    
    No-Descriptor Transfer Mode
    562
  - DMA Requests
    562
  - Figure 23-3 Example for Stride Transfer Mode
    562
    
    Auto Request
    563
    
    On-Chip Peripheral Request
    563
  - How to Use Programmable DMA Channel
    563
- SAR A/D Controller
  
  564
  - Overview
    564
  - Table 24-1 SADC Pin Description
    564
  - Register Description
    565
    
    ADC Enable Register (ADENA)
    565
    
    Table 24-2 SADC Register Description
    565
    
    ADC Configure Register (ADCFG)
    566
    
    ADC Control Register (ADCTRL)
    568
    
    ADC Status Register (ADSTATE)
    569
    
    ADC same Point Time Register (ADSAME)
    570
    
    ADC Touch Screen Data Register (ADTCH)
    570
    
    ADC Wait Pen down Time Register (ADWAIT)
    570
    
    ADC aux Data Register (ADADAT)
    573
    
    ADC VBAT Data Register (ADVDAT)
    573
    
    ADC Clock Divide Register (ADCLK)
    574
    
    ADC Command Register (ADCMD)
    575
  - SAR A/D Controller Guide
    576
    
    A Sample Touch Screen Operation
    576
    
    Power down Mode
    576
    
    SLEEP Mode Sample Operation
    577
    
    AUX Sample Operation
    578
    
    Disable Touch Screen
    578
    
    Multi-Touch Operation
    578
    
    VBAT Sample Operation
    578
    
    Use 5-Wire Touch Panel Operation
    579
    
    Use External Touch Screen Controller Operation
    579
    
    Use Software Command Operation
    579
    
    Use TSC to Support Keypad
    579
    
    Figure 24-1 6X5 Keypad Circuit
    581
    
    Figure 24-2 Wait for Pen-Down (C=1100) Circuit
    582
    
    Figure 24-3 Measure X-Position (C=0010) Circuit
    583
    
    Figure 24-4 Measure Y-Position (C=0011) Circuit
    583
- Real Time Clock
  
  585
  - Overview
    585
    
    Features
    585
    
    Signal Descriptions
    585
  - Register Description
    586
  - Table 25-1 Registers for Real Time Clock
    586
    
    RTC Control Register (RTCCR)
    587
    
    Table 25-2 Registers for Hibernating Mode
    587
    
    RTC Regulator Register (RTCGR)
    589
    
    RTC Second Alarm Register (RTCSAR)
    589
    
    RTC Second Register (RTCSR)
    589
    
    Hibernate Control Register (HCR)
    590
    
    HIBERNATE Mode Wakeup Filter Counter Register (HWFCR)
    591
    
    Hibernate Reset Counter Register (HRCR)
    591
    
    HIBERNATE Wakeup Control Register (HWCR)
    592
    
    HIBERNATE Wakeup Status Register (HWRSR)
    592
    
    Hibernate Scratch Pattern Register (HSPR)
    594
    
    Write Enable Pattern Register (WENR)
    594
    
    CLK32K Pin Control Register (CKPCR)
    595
    
    OWI Pin Control Register (OWIPCR)
    596
    
    Power on Control Register (PWRONCR)
    597
  - Time Regulation
    597
  - Operate Mode
    598
    
    Figure 25-1 Core Power on Directly
    598
    
    Normal Mode
    598
    
    HIBERNATE Mode
    599
  - Clock Select
    599
  - Figure 25-2 Core Power On-Off-On
    599
  - Table 25-3 Clock Select Registers
    600
  - Figure 25-3 RTC Clock Selection Path
    600
- EFUSE Slave Interface (EFUSE)
  
  601
  - Overview
    601
  - Register Description
    601
    
    EFUSE Control Register (EFUCTRL)
    602
    
    EFUSE Configure Register (EFUCFG)
    603
    
    EFUSE Status Register (EFUSTATE)
    603
    
    EFUSE Data Register (Efudatan)
    604
  - Flow
    606
    
    Read EFUSE Flow
    606
    
    Write EFUSE Flow
    606
    
    Write Security Key Flow
    606
    
    Read Security Key/Random Number Flow
    607
    
    Section 6 Peripherals
    608
- TS Slave Interface (TSSI)
  
  609
  - Overview
    609
  - Pin Description
    609
  - Register Description
    609
  - Table 27-1 TSSI Pin Description
    609
    
    Table 27-2 TSSI Register Description
    610
    
    TSSI Enable Register (TSENA)
    610
    
    TSSI Configure Register (TSCFG)
    611
    
    TSSI Control Register (TSCTRL)
    613
    
    TSSI FIFO Register (TSFIFO)
    614
    
    TSSI PID Enable Register (TSPEN)
    614
    
    TSSI State Register (TSSTAT)
    614
    
    TSSI Data Number Register (TSNUM)
    615
    
    TSSI Data Trigger Register (TSDTR)
    615
    
    TSSI DMA Descriptor Address (TSDDA)
    616
    
    TSSI PID Filter Registers (TSPID0~15)
    616
    
    TSSI DMA Command (TSDCMD)
    617
    
    TSSI DMA Identifier (TSDID)
    617
    
    TSSI DMA Target Address (TSDTA)
    617
    
    TSST DMA Status (TSDST)
    618
    
    TSSI Transfer Control Register (TSTC)
    619
  - TSSI Timing
    620
  - TSSI Guide
    620
    
    Figure 27-1 Timing Waveform in Parallel Mode
    620
    
    Figure 27-2 Timing Waveform in Serial Mode
    620
    
    TSSI Operation Without PID Filtering Function
    620
    
    TSSI Operation with PID Filtering Function
    621
- General-Purpose I/O Ports
  
  622
  - Overview
    622
    
    GPIO Port a Summary
    622
    
    Table 28-1 GPIO Port a Summary
    622
    
    GPIO Port B Summary
    623
    
    Table 28-2 GPIO Port B Summary
    623
    
    GPIO Port C Summary
    624
    
    Table 28-3 GPIO Port C Summary
    624
    
    GPIO Port D Summary
    625
    
    Table 28-4 GPIO Port D Summary
    625
    
    GPIO Port E Summary
    626
    
    Table 28-5 GPIO Port E Summary
    626
    
    GPIO Port F Summary
    627
    
    Table 28-6 GPIO Port F Summary
    627
  - Registers Description
    629
  - Table 28-7 GPIO Registers
    629
    
    PORT PIN Level Registers (Pxpin)
    633
    
    PORT Interrupt Clear Registers (Pxintc)
    634
    
    PORT Interrupt Registers (Pxint)
    634
    
    PORT Interrupt Set Registers (Pxints)
    634
    
    PORT Mask Registers (Pxmsk)
    635
    
    PORT Mask Set Registers (Pxmsks)
    635
    
    PORT Mask Clear Registers (Pxmskc)
    636
    
    PORT Pat1/Direction Registers (Pxpat1)
    636
    
    PORT Pat0/Data Registers (Pxpat0)
    637
    
    PORT Pat1/Direction Clear Registers (Pxpat1C)
    637
    
    PORT Pat1/Direction Set Registers (Pxpat1S)
    637
    
    PORT Pat0/Data Set Registers (Pxpat0S)
    638
    
    PORT FLAG Registers (Pxflg)
    639
    
    PORT Pat0/Data Clear Registers (Pxpat0C)
    639
    
    PORT FLAG Clear Registers (Pxflgc)
    640
    
    PORT PULL Disable Registers (Pxpe)
    640
    
    PORT PULL Set Registers (Pxpes)
    640
    
    PORT PULL Clear Registers (Pxpec)
    641
  - Program Guide
    641
    
    Port Function Guide
    641
- SMB Controller
  
  643
  - Overview
    643
    
    Features
    643
    
    Pin Description
    643
    
    Table 29-1 SMB Pin Description
    643
  - Registers
    644
    
    Registers Memory Map
    644
    
    Table 29-2 Registers Memory Map-Address Base
    644
    
    Table 29-3 Registers Memory Map-Address Offset
    644
    
    Registers and Fields Description
    645
  - Operating Flow
    666
    
    Master Mode Operation
    667
    
    SMB Behavior
    667
    
    Slave Mode Operation
    669
    
    Disabling SMB
    672
- Synchronous Serial Interface
  
  674
- UART Interface
  
  693
  - Overview
    693
    
    Features
    693
    
    Pin Description
    693
  - Register Descriptions
    693
  - Table 31-1 UART Pins Description
    693
    
    Register Mapping
    694
    
    Table 31-2 UART Registers Description
    694
    
    UART Receive Buffer Register (URBR)
    694
    
    UART Divisor Latch Low/High Register (UDLLR / UDLHR)
    695
    
    UART Transmit Hold Register (UTHR)
    695
    
    UART Interrupt Enable Register (UIER)
    696
    
    UART Interrupt Identification Register (UIIR)
    696
    
    Table 31-3 UART Interrupt Identification Register Description
    697
    
    UART FIFO Control Register (UFCR)
    698
    
    UART Line Control Register (ULCR)
    699
    
    UART Line Status Register (ULSR)
    700
    
    UART Modem Control Register (UMCR)
    702
    
    UART Modem Status Register (UMSR)
    703
    
    UART Scratchpad Register
    703
    
    Infrared Selection Register (ISR)
    704
    
    UART Add Cycle Register (UACR)
    705
    
    UART M Register (UMR)
    705
    
    UART RXFIFO Counter Register (URCR)
    705
    
    UART TXFIFO Counter Register (UTCR)
    706
  - Operation
    706
    
    UART Configuration
    706
    
    Data Reception
    707
    
    Data Transmission
    707
    
    Receive Error Handling
    707
    
    DMA Transfer
    708
    
    Modem Transfer
    708
    
    Slow Irda Asynchronous Interface
    708
    
    For any Frequency Clock to Use the UART
    709
- MMC/SD CE-ATA Controller
  
  711
  - Overview
    711
  - Features
    711
  - Pins Description
    711
  - Block Diagram
    712
  - MMC/SD Controller Signal I/O Description
    712
  - Figure 32-1 MMC/SD Controller Block Diagram
    712
  - Register Description
    713
  - Table 32-1 Command Token Format
    713
  - Table 32-2 MMC/SD Data Token Format
    713
  - Table 32-3 MMC/SD Controller Registers Map
    713
    
    MSC Control Register (MSC_CTRL)
    714
    
    MSC Control 2 Register (MSC_CTRL2)
    716
    
    MSC Status Register (MSC_STAT)
    717
    
    MSC Clock Rate Register (MSC_CLKRT)
    719
    
    MSC Command and Data Control Register (MSC_CMDAT)
    719
    
    MSC Response Time out Register (MSC_RESTO)
    722
    
    MSC Block Count Register (MSC_NOB)
    723
    
    MSC Block Size Register (MSC_BLKLEN)
    723
    
    MSC Read Time out Register (MSC_RDTO)
    723
    
    MSC Interrupt Mask Register (MSC_IMASK)
    724
    
    MSC Successfully-Transferred Blocks Count Register (MSC_SNOB)
    724
    
    MSC Interrupt Flag Register (MSC_IFLG)
    726
    
    MSC Command Index Register (MSC_CMD)
    728
    
    MSC Command Argument Register (MSC_ARG)
    729
    
    MSC Receive FIFO Port Register (MSC_RXFIFO)
    729
    
    MSC Response FIFO Register (MSC_RES)
    729
    
    MSC Low Power Mode Register (MSC_LPM)
    730
    
    MSC Transmit FIFO Port Register (MSC_TXFIFO)
    730
    
    MSC DMA Control Register (MSC_DMAC)
    731
    
    MSC DMA Data Address Register (MSC_DMADA)
    732
    
    MSC DMA Descriptor Address Register (MSC_DMANDA)
    732
    
    MSC DMA Command Register (MSC_DMACMD)
    733
    
    MSC DMA Data Length Register (MSC_DMALEN)
    733
    
    MSC RTFIFO Data Counter Register(MSC_RTCNT)
    734
  - MMC/SD Functional Description
    734
    
    Card Registry
    735
    
    MSC Card Reset
    735
    
    MSC Reset
    735
    
    Voltage Validation
    735
    
    Card Access
    736
    
    Protection Management
    738
    
    Table 32-4 Command Data Block Structure
    739
    
    Card Status
    742
    
    Table 32-5 Card Status Description
    742
    
    SD Status
    745
    
    Table 32-6 SD Status Structure
    745
    
    Sdio
    746
    
    Application Specified Command Handling
    747
    
    Clock Control
    747
  - MMC/SD Controller Operation
    748
    
    Data Fifos
    748
    
    DMA and Program I/O
    749
    
    Software Reset
    751
    
    Start and Stop Clock
    751
    
    Voltage Validation and Card Registry
    752
    
    Single Data Block Write
    754
    
    Multiple Block Write
    755
    
    Single Block Read
    755
    
    Multiple Block Read
    756
    
    Table 32-7 How to Stop Multiple Block Write
    756
    
    Stream Write (MMC)
    757
    
    Table 32-8 How to Stop Multiple Block Read
    757
    
    Erase, Select/Deselect and Stop
    758
    
    Stream Read (MMC)
    758
    
    Operation and Interrupt
    759
    
    SDIO Readwait
    759
    
    SDIO Suspend/Resume
    759
    
    Table 32-9 the Mapping between Commands and Steps
    760
- OTG Controller
  
  762
- Smart Card Controller
  
  865
  - Overview
    865
  - Pin Description
    866
  - Register Description
    866
    
    FIFO Data Count Register (SCCFDR)
    866
    
    Table 34-1 Smart Card Controller Pins Description
    866
    
    Table 34-2 Smart Card Controller Registers Description
    866
    
    Transmit/Receive FIFO Data Register (SCCDR)
    866
    
    Control Register (SCCCR)
    867
    
    Status Register (SCCSR)
    868
    
    ETU Counter Value Register (SCCECR)
    869
    
    Extra Guard Timer Register (SCCEGTR)
    869
    
    Transmission Factor Register (SCCTFR)
    869
    
    Reception Timeout Register (SCCRTOR)
    870
- KMC Controller
  
  871

Advertisement

Ingenic JZ4780 Design Manual

Ingenic JZ4780 Design Manual (50 pages)

Brand: Ingenic | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
5
1 Overview

9
- Introduction
  9
- Reference Platform
  10
2 Platform Stack-Up and Placement

11
3 Static Memory Interface Design Guidelines

15
- Overview
  15
- Boot Memory
  15
- NAND Flash Connection
  16
4 Ddr3 Sdram

17
5 Audio Codec Design Guidelines

22
- Overview
  22
- Audio Power
  22
- Headphone out
  22
- MIC in
  23
- Speaker
  24
- Receiver
  24
- Line in
  24
- Ditigal MIC
  25
- Layout Guideline
  25
6 USB and OTG Design Guidelines

27
- USB Overview
  27
  - 6.1.1 USB Power
    27
- OTG Overview
  27
  - 6.2.1 OTG Power
    27
- Guidelines for the USB and OTG Interface
  28
7 Lcd

30
8 Lvds

33
- Overview
  33
9 Hdmi

34
- HDMI Overview
  34
  - 9.1.1 HDMI Power
    34
10 Camera

35
- Overview
  35
11 Msc

36
- Overview
  36
  - 11.1.1 MSC Power
    36
12 PS/2 and Keyboard

37
- Overview
  37
13 SAR A/D Controller

38
- Overview
  38
- Touch Screen
  38
- Battery Voltage Measurement
  39

Advertisement

Related Products

Ingenic Categories

Computer Hardware Motherboard Control Unit

More Ingenic Manuals