Addi-Data ADDICOM PA 7400 Series Technical Description page 9

Communication adapter
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PA 7400
Tables
Table 5-1: Setting the base address for the serial port 1...................................................11
Table 5-2: Setting the base address for the serial port 2...................................................11
Table 5-3: Setting the base address for the parallel port ..................................................11
Table 5-4: Setting the interrupt lines for the parallel port ...................................................12
Table 5-5: Receiving data: jumper J1 and J2 ..................................................................13
Table 5-6: 20 mA Current Loop - Transmitting data..........................................................13
Table 5-7: Transmission control: J21(10) and J39(40)........................................................14
Table 5-8: Reception control: Jumper J16(7) ...................................................................15
Table 5-10: Terminator - Jumper J8(13) ............................................................................15
Table 5-11: Current source - Jumper J22(3) and J23(4) ...................................................16
Table 5-12: Protection circuitry - J24 and J5.....................................................................16
Table 5-13: Derivation of interference potential - J9.........................................................17
Table 7-1: Pin assignment for the serial port 1 ..................................................................29
Table 7-2: Pin assignment for the serial port 2 ..................................................................30
Table 8-1: I/O map - Serial port 1 .....................................................................................32
Table 8-2: I/O map - Serial port 2 .....................................................................................33
Table 8-3: I/O map - Parallel port .....................................................................................33
Table 8-4: I/O map ...........................................................................................................47
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