HMS Anybus CompactCom B40 Modbus Serial User Manual page 28

Hardware Design
Signal Group
B
A
The differential signals Rx and Tx should be routed as differential pairs with a characteristic
impedance of 100 Ω differentially.
Rx Channel Design Requirements
The Rx channel is designed for an optical transceiver output that has an AC coupled 100 Ω
differential signal with 100-1000 mV amplitude, e.g. LVPECL (low voltage positive emitter
coupled logic). Each line is terminated with 50 Ω to a common point with a potential of 1.2 V on
the brick.
If a transceiver with a DC coupled output is used, series capacitors are needed to obtain desired
signal levels for the brick. Below is a figure describing three different options to connect a
transceiver output to an Rx channel on the brick:
Brick
AC coupled transceiver
Fig. 12
The AC coupling capacitors typically have a value of 100 nF. Resistors draining bias current
typically have a value of 150 Ω.
Anybus ® CompactCom ™ B40 Modbus Serial User Manual
Signal Name Type
B_RXP I
B_SDA
I/O
B_RXN I
B_SDP I
B_SCL
I/O
B_SDN I
B_TXEN O
B_TXDIS O
B_TXP O
B_TXN O
A_RXP I
A_SDA
I/O
A_RXN I
A_SDP I
A_SCL
I/O
A_SDN I
A_TXEN O
A_TXDIS O
A_TXP O
A_TXN O
Trans-
Brick
ceiver
DC coupled transceiver
Pin Description
3
Rx, LVPECL positive signal
4 SDA, I2C data
5
Rx, LVPECL negative signal
7 Signal Detect, LVPECL positive signal
8
SCL, I2C clock
9 Signal Detect, LVPECL negative signal
11
Tx enable
TXEN is implemented as the inverse to TXDIS
13
Tx disable
15
Tx, LVPECL positive signal
17
Tx, LVPECL negative signal
29 Rx, LVPECL positive signal
30
SDA, I2C data
31 Rx, LVPECL negative signal
33
Signal Detect, LVPECL positive signal
34 SCL, I2C clock
35
Signal Detect, LVPECL negative signal
37 Tx enable
TXEN is implemented as the inverse to TXDIS
39 Tx disable
41
Tx, LVPECL positive signal
43
Tx, LVPECL negative signal
Trans-
Brick
ceiver
DC coupled transceiver with bias current
26 (48)
Trans-
ceiver
SCM-1202-130 1.1 en-US