Epson S5U1C63000H6 Manual page 18

5 OPERaTIOnS anD FUnCTIOnS OF THE S5U1C63000H6
(3) Interrupt at single step operation
Interrupts during single step operation can be enabled or disable using the MD command. Each operation is as
follows.
When interrupt is enabled
If an interrupt request is generated while the target program is single stepping by the S or N command, the
interrupt processing will be started when an instruction is executed, and the execution stops after fetching
the vector address of the interrupt. Therefore, the next single step operation executes the interrupt handler
routine. When the HALT or SLP instruction is executed by the S or N command, the execution is not termi-
nated until an interrupt occurs. In this status, a forced break input from the host computer can suspend the
execution.
When interrupt is disabled
An interrupt processing is not executed by the S command. Therefore, the execution of the HALT or SLP
instruction is immediately suspended, and the program counter indicates the address next to the HALT or
SLP instruction. The N command operates similar to the S command in the execution of the main routine.
However, it enables interrupts while a sub routine is being executed regardless of whether the MD com-
mand enables interrupts or not.
(4) Data read from undefined RaM area
When a data RAM (ROM) area or an I/O area that is not available in the actual IC chip is read, the read
data becomes indefinite. Read data from the actual IC is also indefinite, however it is different from the
S5U1C63000H6.
(5) Detection of SP1 incorrect stack access
It is possible to detect any incorrect stack access to out of the SP1 area by specifying the SP1 area with the BSP
command.
The S1C63000 CPU has a queue register and takes stack values in advance in order to make high speed process
of the stacking operation for the CALR instruction and interrupts. Therefore, when restoring a value from the
top address of the stack, the S1C63000 CPU takes a value beyond the top address and writes it into the queue
register. This operation works without any problem. However, the queue register has an indefinite value. In or-
der not to make this process incorrect access, add three to the top address of the SP1 area when specifying.
(6) Data read break
Executing the "INT addr6" instruction issues a dummy read cycle for the memory specified with the addr6 op-
erand. Therefore, a break caused by the dummy read will occur at this instruction when a data read break condi-
tion has been specified by the BD command.
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EPSOn
S5U1C63000H6 ManUal
(S1C63 Family In-Circuit Emulator)