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3.44 SIGNAL LEVEL CONTROL SWITCH
(Refer to circuit diagram Fig-42)
The value of R022 is chosen so that the maximum
channel gain is the same, no matter the video input
signal is 0.7V or 1.0V.
3.45 CLAMP SIGNAL
(Refer to circuit diagram Fig-45)
The CLAMP signal for the video amplifier and
background circuit is generated by multivibrators
0051.
The triggering signal is fed to pin 2 of 0051a via pin1
of 0053 for G + SYNC. signal.
Pin 1 0051a is the Sync. mode detection input.
When G+SYNC. signal inputs, this pin is "LOW".
When H+V or SEPARATE signal inputs, this pin is
CLAMP SIGNAL CIRCUIT
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Pins 12, 2 of 0049b and 0049C are at
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Pin 13 is the output of 0051a, clamp (CLAMP 1)
signal is fed to pin 12 of video amplifier 0002 (0062,
0122, respectively) via inverters 0049a and 0049b.
The clamp (CLAMP2) signal is fed to CUTOFF circuit
via 0049c and C028.
For the COMPOSITE SYNC. or SEPARATE SYNC.
signal input, the clamp (CLAMP 1) signal is generated
from 0051 b and the triggering signal is fed to pin 10
of 0051 b via pin 6 of P003, Pin 5 is the output of
0051 b, this clamp signal is fed to pin 12 of video
amplifier 0002 (0062, 0122, respectively) via inverters
0049a and 0049d.
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3.46 CRT DRIVE CIRCUIT
(Refer to circuit diagram Fig-46)
The output of the RED video signal is fed to the CRT
(KR) via pin 1 of P901.
ROO? and L901 are output
peakings.
2901 is Spark gap whose spark voltage is 200V is
used for preventing high voltage discharge from the
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CRT to the video amplifier. It may cause the damage
during the CRT discharge.
R901 is surge absorbing resistor, it prevent short-
circuiting of video amplifier's output in low impedance
condition with decrease of surge voltage after the
spark gap works.
= 3-37
=
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