Ramp: Ramp Wave Signal Output Instruction - INVT IVC2H Programming Manual

Programming manual of IVC series small PLC

6.11.2 RAMP: Ramp wave signal output instruction

LAD:
IL: RAMP (S1) (S2)
Operand Type
S1 INT Constant KnX
S2 INT Constant KnX
D1 INT
S3 INT Constant KnX
D2 BOOL
Operand description
S1: starting value
S2: end value
D1: output value
S3: step number (S3>0, or system will report operand error
and do not execute the calculation)
D2: output state 0
Function description
In each scan cycle, when the power flow is ON, this
instruction can determine the increment and current output
value D1 according to the ramp wave height and step
number. When the output value D1 reaches S2, it will keep
stable, and the output state D2 will be set ON. If the power
flow falls, the output state D2 will be set OFF, but the output
value D1 will not change, until the power flow rises again,
when D1 will be initialized as S1, and continue to conduct
the next ramp calculation.
See the following figure:
pf
S2
S1
D1
D2
pf: state of the power flow
Analysis of the execution process of the ramp instruction is
shown in the following figure (S3=5):
(D1) (S3) (D2)
KnY KnM KnS
KnY KnM KnS
KnY KnM KnS
Y M S
Chapter 6 Application instructions
Applicable to
Influenced flag bit
Program steps
Applicable elements
KnLM KnSM D SD
KnLM KnSM D SD
D
KnLM KnSM D SD
LM
D1
D2
SM15
Note
1. If the result is not divisible when calculating the program
steps, round off to the nearest whole number.
2. The instruction will generate one ramp data upon every
rising edge.
3. When S1=S2, D1=S2, D2=ON.
4. The total number of RAMP, HACKLE and TRIANGLE
instructions in a program should not exceed 100.
Example
//Initialize registers upon the first scan cycle after the
power-on
LD SM1
MOV 0 D0
MOV 2000 D1
//Execute RAMP instruction when X0 is ON
LD X0
RAMP
//Output the ramp function result to external DA module
when X1=ON to generate ramp wave form
LD X1
TO 0 6 D10 1
The LAD of the preceding instructions is shown below:
IVC2L IVC1S IVC1L IVC1 IVC2H
12
C T V Z
C T V Z
V
C T V Z
C T
S3
D0 D1 D10 1000 M0
164
Indexed
addressing
R √
R √
R √
R √