Pioneer HD-V9000 Service Manual page 73

5
QQ
3 7 63 1515 0
A 4/18
FPGA_SARADEC
4:13C
TO FPGA
TO SCALER
SARADEC_SCALER
8:3C
A 8/18
VOFSYNC
#CS_SARA
R29 T29 U29 V29 W29 Y29 AA29
EL PCIRESETN VSSC32 VSSO41 VSSO44 VDD33O11 VDD33O14 VSSC51
R28 T28 U28 V28 W28 Y28 AA28
1 WEN SHIRQN ADR11 ADR5 DT29 DT23 DT17
R27 T27 U27 V27 W27 Y27 AA27
0 WHIRQN EHIRQN ADR12 ADR6 DT30 DT24 DT18
R26 T26 U26 V26 W26 Y26 AA26
9 SACKN REN ADR13 ADR7 DT31 DT25 DT19
R25 T25 U25 V25 W25 Y25 AA25
8 EACKN CSN ADR14 ADR8 ADR2 DT26 DT20
R24 T24 U24 V24 W24 Y24 AA24
7 PCIMODE ADR17 ADR15 ADR9 ADR3 DT27 DT21
R23 T23 U23 V23 W23 Y23 AA23
6 WACKN ADR18 ADR16 ADR10 ADR4 DT28 DT22
VDD33I27
R22 T22 U22 V22 W22 Y22 AA22
VDD33I21 VDD33I24 VDD33I25
VDD33I17
VDD33I22
VDD33I19
R21 T21 U21 V21 W21 Y21 AA21
5 VSSO34 VSSO37 VSSO40 VSSO43 VSSO47 VSSO49 VDD_DDR2_26
R20 T20 U20 V20 W20 Y20 AA20
2 VDDC29 VDDC36 VDDC40 VDDC49 VDDC51 VDD_DDR2_19 VSS_DDR2_80
R19 T19 U19 V19 W19 Y19 AA19
3 VSSC27 VSSC31 VSSC39 VSSC41 VSSC50 VSS_DDR2_74 VDD_DDR2_25
R18 T18 U18 V18 W18 Y18 AA18
1 VDDC28 VDDC35 VDDC39 VDDC48 VSSC49 VDD_DDR2_18 VSS_DDR2_79
R17 T17 U17 V17 W17 Y17 AA17
2 VSSC26 VSSC30 VSSC38 VDDC47 VSSC48 VSS_DDR2_73 VDD_DDR2_24
TE
L 13942296513
R16 T16 U16 V16 W16 Y16 AA16
0 VDDC27 VDDC34 VSSC37 VDDC46 VSSC47 VDD_DDR2_17 VSS_DDR2_78
R15 T15 U15 V15 W15 Y15 AA15
9 VDDC26 VDDC33 VSSC36 VDDC45 VSSC46 VSS_DDR2_72 VDD_DDR2_23
R14 T14 U14 V14 W14 Y14 AA14
8 VDDC25 VDDC32 VSSC35 VDDC44 VSSC45 VDD_DDR2_16 VSS_DDR2_77
R13 T13 U13 V13 W13 Y13 AA13
1 VSSC25 VSSC29 VSSC34 VDDC43 VSSC44 VSS_DDR2_71 VDD_DDR2_22
R12 T12 U12 V12 W12 Y12 AA12
7 VDDC24 VDDC31 VDDC38 VDDC42 VSSC43 VDD_DDR2_15 VSS_DDR2_76
R11 T11 U11 V11 W11 Y11 AA11
0 VSSC24 VSSC28 VSSC33 VSSC40 VSSC42 VSS_DDR2_70 VDD_DDR2_21
R10 T10 U10 V10 W10 Y10 AA10
6 VDDC23 VDDC30 VDDC37 VDDC41 VDDC50 VDD_DDR2_14 VSS_DDR2_75
R9 T9 U9 V9 W9 Y9 AA9
4 V S S O 3 3 V S S O 3 6 V S S O 3 9 V S S O 4 2 V S S O 4 6 V S S O 4 8 V D D _ D D R 2 _ 2 0
R8 T8 U8 V8 W8 Y8 AA8
4 VDD33I16 VDD33I18 VDD33I20 VDD33O10 VDD33I23 VDD33O13 VDD33I26
R7 T7 U7 V7 W7 Y7 AA7
AVD4 AVD2 RDATA1 RDATA3 RDATA5 RDATA7 ATCK
R6 T6 U6 V6 W6 Y6 AA6
3 AVS4 AVS2 RDATA0 RDATA2 RDATA4 RDATA6 RSTOP
R5 T5 U5 V5 W5 Y5 AA5
R APREQ PLL_MS1 AFSB AFSA UDVA UDVB UDVC
R4 T4 U4 V4 W4 Y4 AA4
C APDATA PWM1 ADVB ADVA UFSA UFSB UFSC
R3 T3 U3 V3 W3 Y3 AA3
O7 VDD33O8 VDD33O9 ASDB ASDA USDA USDB USDC
R2 T2 U2 V2 W2 Y2 AA2
3 VSSO32 VSSO35 ASCKB ASCKA USCKA USCKB USCKC
R1 T1 U1 V1 W1 Y1 AA1
PWM0 APDVD VSSO38 TTCLK VSSO45 VDD33O12 VDD33O15
RD1
RD0
RD3
RD2
RD5
RD4
UDVA
USFA
USDA
USCKA
RD7
RD6
GNDD
www
R 2 0 7 2
0
TP2066
TP2067
TP2068
TP2069
TP2070
TP2071
GNDD
TP2072
TP2073
TP2074
TP2075
STATUS0
V+3.3_3LAIO
TP2076
TP2077
.
GNDD
TP2140
TAP_SEL
TAP_SEL
X2001 D S S 1 1 8 1 - A UNUSED
C N 2 0 0 1
u / 1 0
OUTPUT GND
3 2
2 0 9 6
C 2 0 9 7
VDD STANDBY
0 u / 6 . 3 4 1
GNDD
(QYB)
36.666MHz
D
f=36.666MHz TP2064
5
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AB29 AC29 AD29 AE29 AF29 AG29 AH29 AJ29
PCICLK VDD33O16 VDD33I28 VSSC55 VSSC56 VDD33I29 VSS_DDR2_138
VDD33I30
AB28 AC28 AD28 AE28 AF28 AG28 AH28 AJ28
VSSC53 DT7 DT4 VDDIO_DDR2_88
DT2 DT0
DT1
VSS_DDR2_134
VSSO54
AB27 AC27 AD27 AE27 AF27 AG27 AH27 AJ27VSS_DDR2_137
DT12 DT8 DT5 DT3 VDDIO_DDR2_85
VSS_DDR2_127
VSSO53
AB26 AC26 AD26 AE26 AF26 AG26 AH26 AJ26
DT13 DT9 DT6 VSS_DDR2_122 AMDQ13
VDDIO_DDR2_77
VSSO52
AB25 AC25 AD25 AE25 AF25 AG25 AH25 AJ25
DT14 DT10 VSS_DDR2_115 VSS_DDR2_133
AMDQ15 AMDQ12
DT11
AB24 AC24 AD24 AE24 AF24 AG24 AH24 AJ24
DT15 VDDIO_DDR2_61 VSS_DDR2_121 VDDIO_DDR2_76 AMDQ9
AMDQ14
AMDQS1 AMDQS0
DT16 AMDM0
AB23 AC23 AD23 AE23 AF23 AG23 AH23 AJ23
VSS_DDR2_109 VDDIO_DDR2_84
VDDIO_DDR2_51
VDDIO_DDR2_65
AMDQ5 AMDQ1
AMDM1
AB22 AC22 AD22 AE22 AF22 AG22 AH22 AJ22
VSS_DDR2_103
VSS_DDR2_132
VSS_DDR2_95 VDDIO_DDR2_70
VDDIO_DDR2_60
AMDQ3
AB21 AC21 AD21 AE21 AF21 AG21 AH21 AJ21AMDQ4
VSS_DDR2_94 VDDIO_DDR2_50 D0_VREFA VSS_DDR2_114 AMDQ2
VDDIO_DDR2_75
AMDQ0
AB20 AC20 AD20 AE20 AF20 AG20 AH20 AJ20
VSS_DDR2_93 VSS_DDR2_102 VDDIO_DDR2_59 VSS_DDR2_120 AMDQ6
VDDIO_DDR2_83
AMWEN
AMODT
AMRASN
AB19 AC19 AD19 AE19 AF19 AG19 AH19 AJ19
VSS_DDR2_92 VDDIO_DDR2_49 VSS_DDR2_108 VSS_DDR2_126
VDDIO_DDR2_87
AMCKE R0_RODTA
AJ18 AMCK
AB18 AC18 AD18 AE18 AF18 AG18 AH18
VSS_DDR2_91 VDDIO_DDR2_58 VSS_CLK4
VSS_DDR2_101 VDDIO_DDR2_69
VSS_CLK3
AB17 AC17 AD17 AE17 AF17 AG17 AH17 AJ17
VSS_DDR2_90 VSS_DDR2_100 R0_VCALA VSS_DDR2_113 AMCASN VDDIO_DDR2_74 AMCKN
R0_RDRVA
AB16 AC16 AD16 AE16 AF16 AG16 AH16 AJ16
VSS_DDR2_89 VDDA_A0 VDDIO_DDR2_57 VSS_DDR2_119 AMCS0N
VDDIO_DDR2_82
AB15 AC15 AD15 AE15 AF15 AG15 AH15 AJ15
VSS_DDR2_88 VDDA_A1 VSS_DDR2_107 VDDIO_DDR2_64 AMBA2 VSS_DDR2_125
AMA1
AB14 AC14 AD14 AE14 AF14 AG14 AH14 AJ14 AMA0
VSS_DDR2_87 VSS_DDR2_99 VDDIO_DDR2_56 AMA4 VDDIO_DDR2_68 AMA5 VSS_DDR2_131
AB13 AC13 AD13 AE13 AF13 AG13 AH13 AJ13
VSS_DDR2_86 VDDIO_DDR2_48 VSS_DDR2_106 VSS_DDR2_112 AMA11 VDDIO_DDR2_73 AMA3 AMA2
AJ12 AMA7
AB12 AC12 AD12 AE12 AF12 AG12 AH12
VSS_DDR2_85 VSS_DDR2_98 VDDIO_DDR2_55 AMA12 VSS_DDR2_118 AMA6 VDDIO_DDR2_81
AB11 AC11 AD11 AE11 AF11 AG11 AH11 AJ11
VSS_DDR2_84 VDDIO_DDR2_47 VSS_DDR2_105 VDDIO_DDR2_63 AMA8 VSS_DDR2_124 AMA9 AMA10
AB10 AC10 AD10 AE10 AF10 AG10 AH10 AJ10
VSS_DDR2_83 VSS_DDR2_97 VDDIO_DDR2_54 AMDQ25 VDDIO_DDR2_67 VSS_DDR2_130
AMDQ28 AMDQ31
A M D Q 2 6
A M D Q 2 9
AB9 AC9 AD9 AE9 AF9 AG9 AH9 AJ9
V S S _ D D R 2 _ 8 2 V D D I O _ D D R 2 _ 4 6 V S S _ D D R 2 _ 1 1 1 V D D I O _ D D R 2 _ 7 2 A M D Q 3 0
D 1 _ V R E F A
AMDM3 AMDQ24
AB8 AC8 AD8 AE8 AF8 AG8 AH8 AJ8AMDQ27
VSS_DDR2_81 VSS_DDR2_96 VDDIO_DDR2_53 VSS_DDR2_117 VDDIO_DDR2_80
AMDM2
AB7 AC7 AD7 AE7 AF7 AG7 AH7 AJ7AMDQS3
RSYNC VDDIO_DDR2_45 AMDQS2
VDDIO_DDR2_62
VSS_DDR2_129
VSS_DDR2_104
AMDQ23 AMDQ16
TAP_SELECT AMDQ17
AB6 AC6 AD6 AE6 AF6 AG6 AH6 AJ6
VDDIO_DDR2_52
RDVD VSS_DDR2_116
VDDIO_DDR2_71
STATUS0
VSSO51 AMDQ21 AMDQ20
AB5 AC5 AD5 AE5 AF5 AG5 AH5 AJ5AMDQ19
UDVD VDDIO_DDR2_79
VSS_DDR2_110
STCSTA
VSS_DDR2_123
AB4 AC4 AD4 AE4 AF4 AG4 AH4 AJ4
UFSD STCD ATDO VDDIO_DDR2_66 AMDQ22 AMDQ18
AB3 AC3 AD3 AE3 AF3 AG3 AH3 AJ3
USDD STCLST STCTCK ATDI ATMS VSSO55 VDDIO_DDR2_78 VSS_DDR2_136
AB2 AC2 AD2 AE2 AF2 AG2 AH2 AJ2
USCKD RCLK STCLK TRESETN RESETN ATRST VDDIO_DDR2_86
VSS_DDR2_128
RERR
VSSO56
AB1 AC1 AD1 AE1 AF1 AG1 AH1 AJ1
VSSC52 VSSC54 VSSO50 GDCLK ARTCK VSS_DDR2_135
GNDD
GNDD RESETN
TP2084
RSYNC TP2080
TP2081
RDVD
TP2082
RCLK
RSTOP TP2079
TP2083
R 2 0 8 3 4 . 7 k
GNDD
FPGA_SARADEC
4:13C
A 4/18
x ao
y
TP2163
14I
i
LAAT
V+3.3_3LAIO
N M
GNDD
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6
8
1:15B;2:10C;3:10I;3:11B;3:13B;3:13E;3:5G;4:13C;4:3D;7:6K;9:2C
R 2 0 8 4
N M
R 2 0 8 5
TP2157
4 . 7 k
R 2 0 8 6
TP2158
4 . 7 k
R 2 0 8 7
TP2159
4 . 7 k
SHIRQ
S H I R Q 1:1K A
EHIRQ
E H I R Q 1:1L
WHIRQ
W H I R Q
1:1K
WHACK
W H A C K 1:7L
EHACK
E H A C K 1:8L
SHACK
MAIN_CPU
S H A C K 1:6L
R 2 0 8 8
TP2160
4 . 7 k
V+1.2_3LADR
GNDD
C 2 1 0 1
3_AMDATA13
0 . 1 u / 1 0
C 2 1 0 2
3_AMDATA10
0 . 1 u / 1 0
C 2 1 0 3
0 . 1 u / 1 0
C 2 1 0 4
3_AMDATA15
AMDQ10
0 . 1 u / 1 0
C 2 1 0 5
3_AMDATA12
0 . 1 u / 1 0
3_AMDATA11 C 2 1 0 6
0 . 1 u / 1 0
C 2 1 0 7
0 . 1 u / 1 0
C 2 1 0 8
AMDQ11
0 . 1 u / 1 0
3_AMDATA14 C 2 1 0 9
3_AMDATA9
0 . 1 u / 1 0
C 2 1 1 0
3_AMDATA8
0 . 1 u / 1 0
C 2 1 1 1
0 . 1 u / 1 0
C 2 1 1 2
3_AMDM0
AMDQ8
0 . 1 u / 1 0
3_AMDQS1 C 2 1 1 3
3_AMDQS0
0 . 1 u / 1 0
C 2 1 1 4
0 . 1 u / 1 0
C 2 1 1 5
0 . 1 u / 1 0
3_AMDM1
C 2 1 1 6
3_AMDATA5
0 . 1 u / 1 0
C 2 1 1 7
3_AMDATA1
VRef+0R9D_DDR2A
0 . 1 u / 1 0
C 2 1 0 0
TP2150 0 . 1 u / 1 6
3_AMDATA2 GNDD
3_AMDATA3
GNDD
3_AMDATA4
3_AMDATA0
3_AMDATA6
3_AMDATA7
AMDQ7
3_AMODT
3_AMRASN
V+1.8_3LADR
3_AMWEN
R 2 1 0 5
RN1/10SE3000D-T
VRef+0R9D_DDR2A
TP2146
3_AMCKE
3_AMCK
TP2147
3_AMCASN
3_AMCKN
TP2149 TP2148
R 2 0 9 0 R 2 1 0 3
RS1/10SR270J-T RS1/10SR470J-T
Q Q 3_AMCS0N
GNDD
3_AMBA1
3 6 7 1 3
AMBA1
3_AMBA2
3_AMADRS1
3_AMBA0
AMBA0
3_AMADRS4
3_AMADRS5
3_AMADRS0
3_AMADRS11
3_AMADRS3
3_AMADRS2
3_AMADRS12
3_AMADRS6
3_AMADRS7
3_AMADRS8
3_AMADRS9
3_AMADRS10
3_AMDATA25 VRef+0R9D_DDR2A
3_AMDATA28
3_AMDATA31
3_AMDATA26
3_AMDATA29
3_AMDATA30
3_AMDM3 GNDD
3_AMDATA24
3_AMDATA27
3_AMDM2
3_AMDQS2
3_AMDQS3
3_AMDATA23
3_AMDATA17
3_AMDATA16
Note DDR2 DATA/CLK/ADRS/Control signal Line
Same Length, 50 Inpeadance control
3_AMDATA21
3_AMDATA20
3_AMDATA19
TP2085
TP2087
A 6/18
3_AMDATA22
TP2086
3_AMDATA18
TP2088
6:9B
TP2092
DDR2_A
TP2138
R 2 0 9 1
4 7 k
R 2 0 9 9 4 7 k
TO IC2005
TP2141
TP2089 IC2006
TP2093
TP2090
TP2094
TP2091
R 2 0 9 2 4 7 k
R 2 1 0 1 4 7 k
R 2 0 9 3 4 7 k
R 2 1 0 2 4 7 k
TP2142 LAAT
TP2143
11L
TP2144
TP2145
GNDD
1:10L
# R E S E T _ S A R A D E C
R 2 2 4 4 0
A 1/18
GNDD
FROM FPGA
STREAM I/F
u163
.
TO CN2002 (JTAG-ARM)
HD-V9000
6
7
2 9 9 4 2 8
A
5/18
DECM SERVICE ASSY
(DXX2610)
• MPEG DEC (1/2) BLOCK
FROM MAIN_CPU
HOST_BUS I/F
HOST_BUS
A 1,3,4,7,9/18
V+1.2_3LAV D
1/18
C 2 1 1 8
0 . 1 u / 1 0
C 2 1 1 9
0 . 1 u / 1 0
C 2 1 2 0
0 . 1 u / 1 0
C 2 1 2 1
0 . 1 u / 1 0
C 2 1 2 2
0 . 1 u / 1 0
C 2 1 2 3
0 . 1 u / 1 0
C 2 1 2 4
0 . 1 u / 1 0
C 2 1 2 5
0 . 1 u / 1 0
C 2 1 2 6
0 . 1 u / 1 0
C 2 1 2 7
0 . 1 u / 1 0
C 2 1 2 8
0 . 1 u / 1 0
C 2 1 2 9
0 . 1 u / 1 0
C 2 1 3 0
0 . 1 u / 1 0
C 2 1 3 1
0 . 1 u / 1 0
C 2 1 3 2
0 . 1 u / 1 0
C 2 1 3 3
0 . 1 u / 1 0
C 2 1 3 4
0 . 1 u / 1 0
C 2 1 3 5
0 . 1 u / 1 0
C 2 1 3 6
0 . 1 u / 1 0
C 2 1 3 7
0 . 1 u / 1 0
C 2 1 3 8
0 . 1 u / 1 0
C 2 1 3 9
0 . 1 u / 1 0
C 2 1 4 0
0 . 1 u / 1 0
C 2 1 4 1
0 . 1 u / 1 0
C 2 1 4 2
0 . 1 u / 1 0
C 2 1 4 3
0 . 1 u / 1 0
C 2 1 4 4
0 . 1 u / 1 0
C 2 1 4 5
0 . 1 u / 1 0
GNDD
(AD)
: Audio Data Signal Route
(VD)
: Video Data Signal Route
1 5 0 5 8 2 9 9 4
ARM JTAG
V+3.3_3LAIO
C 2 1 5 1
0 . 0 1 u / 1 6
(RYB)
C 2 1 5 0
1 u / 1 0
C N 2 0 0 2
V+3.3D
1
TP2323
2 GNDD
TP2324
3_ATREST
ATREST
3
TP2126
GNDD
4
TP2325
3_ATDI
ATDI
5
TP2127
6 GNDD
TP2326
3_ATMS
ATMS
7
TP2128
GNDD
8
TP2327
3_ATCK
9 ATCK
TP2129
GNDD
1 0
m
TP2328
3_ARTCK
ARTCK
1 1
TP2130
GNDD
1 2
TP2329
3_ATDO
1 3 ATDO
TP2131
N M
co
GNDD
7
8
9 9
A
Large size
A-a A-b
SCH diagram
A-a A-b
Guide page
B
Detailed page
A-a A-b
C
2 8 9 9
D
E
NOTES
is Standby
NM
without instruction
RS1/16SS***J [ ]
RAB4CQ***J [ ]
(CH)
CCSSCH***J [F/V ]
(RYB)
CKSRYB***K
[F/V ]
(QYB)
CKSQYB***K
[F/V ]
without instruction
CKSSYB***K
[F/V ]
F
A
5/18
73
8