Decm Service Assy (5/18) - Pioneer HD-V9000 Service Manual
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Also See for HD-V9000:
- Specification sheet (2 pages) ,
- Operating instructions manual (152 pages) ,
- Technical manual (27 pages)
Table of Contents
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1
10.3 DECM SERVICE ASSY (3/18)
QQ
3 7 63 1515 0
A
after RESISTORS from MainCPU
A
1,2/18
1:12A;2:1B;13J;5A
V+3R3D_CON
HOST_BUS
HOST_CPU_R/#W
HOST_CPU_DATA0
HOST_CPU_DATA1
HOST_CPU_DATA2
HOST_CPU_DATA3
C 1 1 6 5
0 . 1 u / 1 0
HOST_CPU_DATA4
HOST_CPU_DATA5
HOST_CPU_DATA6
HOST_CPU_DATA7
HOST_CPU_DATA8
HOST_CPU_DATA9
HOST_CPU_DATA10
B
HOST_CPU_DATA11
C 1 1 6 6
0 . 1 u / 1 0
HOST_CPU_DATA12
HOST_CPU_DATA13
HOST_CPU_DATA14
HOST_CPU_DATA15
GNDD
V+3R3D_CON
HOST_CPU_DATA16
HOST_CPU_DATA17
HOST_CPU_DATA18
HOST_CPU_DATA19
C 1 1 6 9
0 . 1 u / 1 0
HOST_CPU_DATA20
C
HOST_CPU_DATA21
HOST_CPU_DATA22
HOST_CPU_DATA23
HOST_CPU_DATA24
HOST_CPU_DATA25
HOST_CPU_DATA26
HOST_CPU_DATA27
TE
C 1 1 7 0
L 13942296513
0 . 1 u / 1 0
HOST_CPU_DATA28
HOST_CPU_DATA29
HOST_CPU_DATA30
HOST_CPU_DATA31
GNDD
D
#HOST_CPU_CS0
#HOST_CPU_CS3
GNDD
E
www
F
A
3/18
68
1
http://www.xiaoyu163.com
2
HOST BUS BUFFER
I C 1 0 0 8
1
4 8
1 D I R
1 O E
2
4 7
R 1 0 7 2
1 B 1
1 A 1
8
1
3
4 6
1 B 2
1 A 2
2
7
4
4 5
G N D 1
G N D 8
3
6
5
4 4
1 B 3
1 A 3
4
5
6
4 3
1 B 4
1 A 4
2 2
C 1 1 6 7
7
4 2
0 . 1 u / 1 0
V C C 1
V C C 4
8
4 1
R 1 0 7 4
1 B 5
1 A 5
1
8
9
4 0
1 B 6
1 A 6
2
7
1 0
3 9
G N D 2
G N D 7
3
6
1 1
3 8
1 B 7
1 A 7
4
5
1 2
3 7
1 B 8
1 A 8
2 2
1 3
3 6
R 1 0 7 6
2 B 1
2 A 1
1
8
1 4
3 5
2 B 2
2 A 2
2
7
1 5
3 4
G N D 3
G N D 6
3
6
1 6
3 3
2 B 3
2 A 3
4
5
1 7
3 2
2 B 4
2 A 4
2 2
1 8
3 1
C 1 1 6 8
V C C 2
V C C 3
0 . 1 u / 1 0
1 9
3 0
R 1 0 7 7
2 B 5
2 A 5
8
1
2 0
2 9
2 B 6
2 A 6
2
7
2 1
2 8
G N D 4
G N D 5
3
6
2 2
2 7
2 B 7
2 A 7
4
5
2 3
2 6
2 B 8
2 A 8
2 2
2 4
2 5
2 D I R
2 O E
T C 7 4 L C X 1 6 2 4 5 F T
I C 1 0 0 9
1
4 8
1 D I R
1 O E
2
4 7
R 1 0 8 0
1 B 1
1 A 1
1
8
3
4 6
1 B 2
1 A 2
7
2
4
4 5
G N D 1
G N D 8
3
6
5
4 4
1 B 3
1 A 3
4
5
6
4 3
1 B 4
1 A 4
C 1 1 7 1
2 2
7
4 2
0 . 1 u / 1 0
V C C 1
V C C 4
8
4 1
R 1 0 8 1
1 B 5
1 A 5
1
8
9
4 0
1 B 6
1 A 6
2
7
1 0
3 9
G N D 2
G N D 7
3
6
1 1
3 8
1 B 7
1 A 7
5
4
1 2
3 7
1 B 8
1 A 8
2 2
1 3
3 6
R 1 0 8 3
2 B 1
2 A 1
1
8
1 4
3 5
2 B 2
2 A 2
2
7
1 5
3 4
G N D 3
G N D 6
3
6
1 6
3 3
2 B 3
2 A 3
4
5
1 7
3 2
2 B 4
2 A 4
2 2
1 8
3 1
C 1 1 7 2
V C C 2
V C C 3
0 . 1 u / 1 0
1 9
3 0
R 1 0 8 5
2 B 5
2 A 5
1
8
2 0
2 9
2 B 6
2 A 6
2
7
2 1
2 8
G N D 4
G N D 5
3
6
2 2
2 7
2 B 7
2 A 7
4
5
2 3
2 6
2 B 8
2 A 8
2 2
2 4
2 5
2 D I R
2 O E
T C 7 4 L C X 1 6 2 4 5 F T
V+3R3D_CON
C 1 1 7 3
0 . 1 u / 1 0
IC1012
1
5
I N B
V C C
2
I N A
TP1380
3
4
G N D
O U T Y
TC7SZ08FU
#CS0
#CS3
OUTY
L
L
L
L
H
L
H
L
L
H
H
H
x
ao
y
.
i
2
http://www.xiaoyu163.com
3
8
CPU side bus signal
from MainCPU
1:12A;1:1F;2:1B;1A
HOST_BUS
TP1335
A
1,2/18
HOST_DATA0
TP1336
HOST_DATA1
TP1337
HOST_DATA2
TP1338
HOST_DATA3
TP1339
HOST_DATA4
TP1340
HOST_DATA5
TP1341
HOST_DATA6
TP1342
HOST_DATA7
TP1343
HOST_DATA8
TP1344
HOST_DATA9
TP1345
HOST_DATA10
TP1346
HOST_DATA11
TP1347
HOST_DATA12
TP1348
HOST_DATA13
TP1349
HOST_DATA14
TP1350
HOST_DATA15
TP1351
HOST_DATA16
TP1352
HOST_DATA17
TP1353
HOST_DATA18
TP1354
HOST_DATA19
TP1355
HOST_DATA20
TP1356
HOST_DATA21
TP1357
HOST_DATA22
TP1358
HOST_DATA23
TP1359
HOST_DATA24
TP1360
HOST_DATA25
TP1361
HOST_DATA26
TP1362
HOST_DATA27
Q Q
3
6 7
1 3
TP1363
HOST_DATA28
TP1364
HOST_DATA29
TP1365
HOST_DATA30
TP1366
HOST_DATA31
A
1,4,5/18
1:15B;11B;13B;4:3D;5:13B
HOST_BUS
DEVICE side bus signal
to FPGA/SARADEC BLOCK
u163
.
HD-V9000
3
4
2 9
9 4
2 8
V+3R3D_CON
I C 1 0 2 2
1
4 8
1 D I R
1 O E
2
4 7
HOST_CPU_ADRS0
1 B 1
1 A 1
3
4 6
HOST_CPU_ADRS1
1 B 2
1 A 2
4
4 5
G N D 1
G N D 8
HOST_CPU_ADRS2
5
4 4
1 B 3
1 A 3
6
4 3
HOST_CPU_ADRS3
1 B 4
1 A 4
C 1 1 7 5
7
4 2
0 . 1 u / 1 0
V C C 1
V C C 4
8
4 1
HOST_CPU_ADRS4
1 B 5
1 A 5
HOST_CPU_ADRS5
9
4 0
1 B 6
1 A 6
1 0
3 9
G N D 2
G N D 7
1 1
3 8
HOST_CPU_ADRS6
1 B 7
1 A 7
1 2
3 7
HOST_CPU_ADRS7
1 B 8
1 A 8
HOST_CPU_ADRS8
1 3
3 6
2 B 1
2 A 1
1 4
3 5
HOST_CPU_ADRS9
2 B 2
2 A 2
1 5
3 4
G N D 3
G N D 6
1 6
3 3
HOST_CPU_ADRS10
2 B 3
2 A 3
HOST_CPU_ADRS11
1 7
3 2
2 B 4
2 A 4
1 8
3 1
C 1 1 7 6
V C C 2
V C C 3
0 . 1 u / 1 0
1 9
3 0
HOST_CPU_ADRS12
2 B 5
2 A 5
2 0
2 9
HOST_CPU_ADRS13
2 B 6
2 A 6
2 1
2 8
G N D 4
G N D 5
2 2
2 7
HOST_CPU_ADRS14
2 B 7
2 A 7
2 3
2 6
HOST_CPU_ADRS15
2 B 8
2 A 8
2 4
2 5
2 D I R
2 O E
T C 7 4 L C X 1 6 2 4 5 F T
GNDD
V+3R3D_CON
I C 1 0 1 0
1
4 8
1 D I R
1 O E
2
4 7
HOST_CPU_ADRS16
1 B 1
1 A 1
3
4 6
HOST_CPU_ADRS17
1 B 2
1 A 2
4
4 5
G N D 1
G N D 8
5
HOST_CPU_ADRS18
4 4
1 B 3
1 A 3
HOST_CPU_ADRS19
6
4 3
1 B 4
1 A 4
C 1 1 4 5
7
4 2
0 . 1 u / 1 0
V C C 1
V C C 4
8
4 1
HOST_CPU_ADRS20
1 B 5
1 A 5
9
4 0
HOST_CPU_ADRS21
1 B 6
1 A 6
1 0
3 9
G N D 2
G N D 7
1 1
3 8
HOST_CPU_ADRS22
1 B 7
1 A 7
1 2
3 7
HOST_CPU_ADRS23
1 B 8
1 A 8
1 3
3 6
HOST_CPU_ADRS24
2 B 1
2 A 1
HOST_CPU_ADRS25
1 4
3 5
2 B 2
2 A 2
1 5
3 4
G N D 3
G N D 6
1 5
0 5
8
1 6
2 9
3 3
9 4
#HOST_CPU_CS0
2 B 3
2 A 3
1 7
3 2
#HOST_CPU_CS3
2 B 4
2 A 4
1 8
3 1
C 1 1 4 6
V C C 2
V C C 3
0 . 1 u / 1 0
1 9
3 0
#HOST_CPU_BS
2 B 5
2 A 5
TP1325
2 0
2 9
R 1 0 6 4
TP1320
2 B 6
2 A 6
4 . 7 k
2 1
2 8
G N D 4
G N D 5
TP1326
2 2
2 7
R 1 1 0 9
TP1321
2 B 7
2 A 7
4 . 7 k
TP1327
2 3
2 6
R 1 1 3 9
TP1322
2 B 8
2 A 8
4 . 7 k
2 4
2 5
2 D I R
2 O E
T C 7 4 L C X 1 6 2 4 5 F T
GNDD
V+3R3D_CON
IC1021
C 1 1 7 4 0 . 1 u / 1 0
1
2 0
O E 1
V C C
2
1 9
HOST_CPU_R/#W
A 1
O E 2
3
1 8
#HOST_CPU_RD
A 2
Y 1
#HOST_CPU_WE0
4
1 7
A 3
Y 2
5
1 6
#HOST_CPU_WE1
A 4
Y 3
6
1 5
#HOST_CPU_WE2
A 5
Y 4
7
1 4
#HOST_CPU_WE3
A 6
Y 5
TP1323
8
1 3
R 1 0 6 7
A 7
Y 6
4 . 7 k
TP1324
9
1 2
R 1 0 7 0
TP1328
A 8
Y 7
4 . 7 k
1 0
1 1
TP1329
G N D
Y 8
TC74LCX541FTS1
V+3R3D_CON
L 1 0 0 7
A T L 7 0 1 0 - A
IC1023
C 1 1 7 9
1
5
I N _ B
V C C
HOST_BUF_CLKOUT
2
0 . 1 u / 1 0
I N _ A
3
4
G N D
O U T _ Y
TC7SZ32FU
GNDD
V+3R3D_CON
IC1024
C 1 1 8 1
1
5
HOST_CPU_ADRS25
I N _ B
V C C
#HOST_CPU_CS3
2
0 . 1 u / 1 0
I N _ A
3
4
G N D
O U T _ Y
TC7SZ32FU
GNDD
#CS3
ADRS25
OUTY
L
L
L
L
H
H
H
L
H
m
H
H
H
co
V+3R3D_CON
IC1025
C 1 1 8 2
1
5
I N _ B
V C C
2
#HOST_CPU_BS
0 . 1 u / 1 0
I N _ A
3
4
G N D
O U T _ Y
TC7SZ32FU
GNDD
4
9 9
R 1 0 9 4
TP138
1
8
TP138
2
7
TP138
6
3
TP138
4
5
C 1 1 7 7
2 2
0 . 1 u / 1 0
R 1 0 9 6
TP138
8
1
TP138
2
7
TP138
3
6
TP139
4
5
2 2
R 1 0 9 7
TP139
1
8
TP139
2
7
TP139
3
6
TP139
5
4
2 2
C 1 1 7 8
0 . 1 u / 1 0
R 1 1 0 6
TP139
1
8
TP139
2
7
TP139
3
6
TP139
4
5
2 2
R 1 0 6 0
TP116
1
8
TP116
2
7
TP133
3
6
TP133
4
5
2 2
C 1 1 4 7
0 . 1 u / 1 0
R 1 0 8 6
TP133
1
8
TP136
7
2
TP136
3
6
TP136
4
5
2 2
R 1 0 8 7
TP137
8
1
TP137
2
7
TP137
3
6
2 8
9 9
TP138
4
5
2 2
C 1 1 4 8
0 . 1 u / 1 0
R 1 0 8 9
TP137
3 3
R 1 0 9 3
TP
1
8
TP
2
7
TP
3
6
TP
4
5
R 1 0 6 2
TP
2 2
TP
R 1 0 6 3
2 2
2 2
GNDD
TP140
R 1 2 4 4
2 2
TP137
R 1 0 9 1
2 2
GNDD
R 1 1 4 0
N M
R 1 2 1 4
6 8
TP1400
GND
Ti
R 1 2 1 5
2 2
R 1 1 4 1
N M
R 1 2 1 7
6 8
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