Pioneer HD-V9000 Service Manual page 61

5
QQ
3 7 63 1515 0
L22 M22 N22 P22 R22
D16 DQMLL D6 D4 D2
L21 M21 N21 P21 R21
D17 DQMUL D7 D5 D3
L20 M20 N20 P20 R20
D30 DQMLU D8 D10 D12
L19 M19 N19 P19 R19
D31 DQMUU D9 D11 D13
L18 M18 N18 P18
R18
VDDQ16 VDDQ18 VDDQ20 VSS69 VSS70 VSS72
AIN CPU
IC1001
R5S77640N300BG
L15 M15 N15 P15 R15
VDD15 VDD17 VDD19 VDD21 VDD30
L14 M14 N14 P14 R14
VSS49 VSS55 VSS61 VSS68 VDD29
TE
L13 M13 N13 P13 R13
L 13942296513
VSS48 VSS54 VSS60 VSS67 VDD28
L12 M12 N12 P12 R12
VSS47 VSS53 VSS59 VSS66 VDD27
L11 M11 N11 P11 R11
VSS46 VSS52 VSS58 VSS65 VDD26
L10 M10 N10 P10 R10
VSS45 VSS51 VSS57 VSS64 VDD25
L9 M9 N9 P9 R9
VSS44 VSS50 VSS56 VSS63 VDD24
L8 M8 N8 P8 R8
VDD14 VDD16 VDD18 VDD20 VDD23
L5 M5 N5 P5 R5
VSS43 VDDQ17 VDDQ19 VSS62 VDD22 VSS71
L4 M4 N4 P4 R4
RQOUT#/DREQ1# STATUS0/CTS2#/PA6 FCE#/PA5 FALE/PC0
D1# STATUS1/RTS2#/PA7 FRE#/PA4
AUDIO_CLK3/PH7
L3 M3 N3 P3 R3
SSIWS0 SSIDATA0 SSIWS1 SSIDATA1 FWE#/PA3
H5
SSIDATA4/IDED3_M/PE1
L2 M2 N2 P2 R2
MDC/PF0/IDED4_M SSISCK1 PJ4/IDED6_M
ED2_M/PE3 SSISCK0 PJ6/IDED5_M
UDIO_CLK4/IDED12_M/PE0
L1 M1 N1 P1 R1
MDIO/PF1/IDED11_M AUDIO_CLK1/PC6 PJ5/IDED9_M
ED13_M/PE2 AUDIO_CLK0/PC7 PJ7/IDED10_M
www
.
GNDD
HOST_BUS
15B;4:3D
5
http://www.xiaoyu163.com
SDRAM/BUS BUFFER IF
#RDY_MainCPU
H WAIT
L READY
GNDD
V+3R3D_CON
TP1190
A22/PB4/CTS1# PRESET#
T22 U22 V22 W22 Y22 AA22 AB22
D0 A20/PB2 A24/PB6/DACK0#/CTS0# VSS94 XTAL
VSS90
A23/PB5/DTEND0#/RTS1#
T21 U21 V21 W21 Y21 AA21 AB21
D1 A19/PB1 ASEBRKAK#/BRKACK/TCLK/PC1 VSS93 EXTAL
T20 U20 V20 W20 Y20 AA20 AB20
D14 A18/PB0 A21/PB3 VSS87 BS# VSS-PLL1 VDD-PLL1
A25/PB7/DREQ0#/RTS0#
T19 U19 V19 W19 Y19 AA19 AB19
D15 A17 VSS86 BREQ# VSS-PLL2 VDD-PLL2
V18 W18 Y18 AA18 AB18
T18 U18
VDDQ22 VDDQ30 CS0# VSS89 BACK# VSS97
V17 W17 Y17 AA17 AB17
VDDQ29 CS3# RD# NMI RDY#
V16 W16 Y16 AA16 AB16
VSS76 VSS85 PI0/COM/CDE VSS92 VSS96
LCD_DATA0/DB0/BT_DATA0
V15 W15 Y15 AA15 AB15
VSS75 VSS84 LCD_DON/DCLKOUT/PH2
LCD_CL2/DE_V/CLS/PH3
LCD_DATA2/DB2/BT_DATA2
V14 W14 Y14 AA14 AB14
VDDQ28 VSS83 LCD_DATA1/DB1/BT_DATA1
LCD_DATA3/DB3/BT_DATA3
LCD_DATA5/DB5/BT_DATA5/PI2
V13 W13 Y13 AA13 AB13
VDDQ27 VSS82 LCD_DATA4/DB4/BT_DATA4/PI1
LCD_DATA6/DG0/BT_DATA6/PI3
LCD_DATA8/DG2/PG0
V12 W12 Y12 AA12 AB12
VDD32 VSS81 LCD_DATA7/DG1/BT_DATA7/PI4
LCD_DATA9/DG3/PG1
LCD_DATA11/DG5/PG3
V11 W11 Y11 AA11 AB11
VDD31 VSS80 LCD_DATA10/DG4/PG2
LCD_DATA12/DR0/PG4
LCD_DATA14/DR2/PG6
V10 W10 Y10 AA10 AB10
VDDQ26 VSS79 LCD_DATA13/DR1/PG5
LCD_DATA15/DR3/PG7
LCD_M_DISP/DE_H/DE_C/BT_DE_C
V9 W9 Y9 AA9 AB9
VDDQ25 VSS78 LCD_CLK/DCLKI N
LCD_VCPWC/DR4/PH1
LCD_FLM/VSYNC/SPS/EX_VSYNC/BT_VSYNC
V8 W8 Y8 AA8 AB8
VDDQ24 VSS77 LCD_CL1/HSYNC/SPL/EX_HSYNC/BT_HSYNC
LCD_VEPWC/DR5/PH0
V7 W7 Y7 AA7 AB7
VSS74 TRST# VSS88 VSS91 VSS95
V6 W6 Y6 AA6 AB6
VSS73 TDO TMS TDI TCK
WDTOVF#/IRQ1/AUDCK/DACK1#
T5 U5 V5 W5 Y5 AA5 AB5
VDDQ21 VDDQ23 RXD0/AUDATA0 SCK0/AUDSYNC/FCLE
TXD0/AUDATA1
T4 U4 V4 W4 Y4 AA4 AB4
MODE8/FD7 MODE4/FD4 VDDQ31 RXD1/AUDATA2 SCK1/FR/B#
TXD1/AUDATA3
T3 U3 V3 W3 Y3 AA3 AB3
MODE7/FD6 MODE5/FD5 MODE1/FD1 VDDQ32 MODE0/FD0 SDA
T2 U2 V2 W2 Y2 AA2 AB2
PJ0/DIRECTION_M RXD2/PA1 VDDQ33 SCL
PJ3/IDED7_M MODE2/FD2
T1 U1 V1 W1 Y1 AA1 AB1
PJ1/IDERST_M# TXD2/PA2 SCK2/PA0 VDDQ34
PJ2/IDED8_M MODE3/FD3
GNDD GNDD
x ao
GNDD y
i GNDD
http://www.xiaoyu163.com
6
8
A 2,3/18
A
1/18
15B;2:1B;3:11F;3:1A;3:5A
HOST_BUS
TC7SA00FU
V+3R3D_CON
O U T Y 4 G N D
3
I N A
2
V C C I N B
5 1
IC1002
A 7/18
C 1 0 3 0 0 . 1 u / 1 0 G D C _ R D Y
GNDD 7:6K
A 4/18
TO CN1006
F P G A _ R D Y
JTAG 4:7L
15H
V+3R3D_CON
(Reset input from DEBUGGER)
DKF1003-A-T
R 1 1 2 2 R 1 1 4 8
K1002
R 1 1 2 6
0 TP1221
4 . 7 k
4 . 7 k
IC1003
A 18/18
I N B 1 5 V C C C 1 0 4 0
R 1 1 2 0
I N A 2 0 . 1 u / 1 0
# R E S E T _ S T O M
18:4F
0 G N D 3 4
O U T Y
(GND for DEBUGGER)
TC7SH08FUS1
DKF1003-A-T
K1001 RESET SELECTOR
GNDD
R 1 1 4 9
TP1238
TP1210
0
TP1208
TP1304
C 1 0 3 4
1 2 p / 5 0
R 1 1 1 8 (CH)
RESET_JTAG
1 . 5 k
X 1 0 0 2
GNDD
D S S 1 1 6 0 - A
25MHz
C 1 0 3 5
1 0 p / 5 0 (CH)
V+1R25D
TP1209
TP1299
CCG1160-A F1008
TP1306 TP1305 GNDD
R 1 1 3 3 2 1
1 0
(1/8W)
D+1.25 PLL
3
TP1298
R 1 1 3 4
1 0
(1/8W) GNDD GNDD
V+3R3D_CON
R 1 1 1 7 V+1R25D
4 . 7 k
V+1R25D_CON CCG1160-A F1007
D+1.25 CPU
2 1
TP1259
3
TP1307
GNDD
R 1 1 2 7
TP1223
1 8
TP1228
2 7
TP1224
3 6
5
4
TP1215 TP1220
TP1197
2 2 V+3R3D_CON
TP1198
TP1199
TP1200
Q Q
R 1 1 2 8
TP1226
1 8
3 6 7 1 3
TP1225
2 7
TP1227
6
3
TP1222
4 5
2 2
R 1 2 0 6 TP1201
R 1 2 0 7
2 2 R 1 1 2 9
4 . 7 k
TP1064
1 8 R 1 1 8 3
TP1231
2 7 4 . 7 k
TP1230
3 6
TP1232
4 5
2 2
R 1 1 3 0
TP1235
1 8
TP1062
2 7
TP1233
3 6
TP1111
TP1202 4 5
2 2
R 1 1 3 6
TP1203
4 . 7 k
TP1237
R 1 1 3 2
R 1 1 3 5
2 2 V+3R3D_CON
1 k
GNDD
R 1 1 2 3
TRST
R 1 0 4 1
TP1239
TP1204
2 2 1 8
2 7
TP1205
3 6
R 1 1 2 1 4 5
TP1240
1 8 TDO
4 . 7 k TP1242
2 7 TCK
TP1241
3 6 TDI
TP1243
5 TMS
4
2 2 R 1 1 4 2 TP1244
R 1 1 1 9
4 . 7 k
2 2
R 1 1 3 7 TP1246
R 1 1 9 0
1 8 MCPU_SCK0
4 . 7 k
R 1 1 9 1 TP1245
7 MCPU_TXD0
2 4 . 7 k
R 1 1 8 7
TP1249
4 . 7 k
3 6 MCPU_SCK1
R 1 1 8 9 TP1247
4 5 MCPU_RXD0
4 . 7 k
R 1 1 2 4 TP1248
R 1 1 8 8
1 8 MCPU_TXD1
5 6 4 . 7 k
TP1250
MCPU_RXD1
2 7
TP1211 3 6
TP1216
TP1212 4 5
TP1217
2 2
R 1 1 4 3
R 1 1 3 1 TP1251
1 . 2 k
TP1252
R 1 1 1 6
2 2
1 . 2 k
R 1 1 2 5
R 1 1 4 4
2 2
1 8 TP1218
TP1213
2 7 TP1219
TP1214 R 1 1 4 5 TP1253
3 6 MCPU_RXD2
4 . 7 k
TP1254
5 MCPU_TXD2
4 4 . 7 k
R 1 1 4 6
2 2
2:14C;4:3H;4:3J;12:5F;14:2B;15:2E;15:2F;18:4G
NOTES
NM is Standby
RS1/16SS***J [ ]
(D) RS1/16SS****D [ ]
(1/8W) RS1/8SQ***J
[ ]
RAB4CQ***J [ ]
u163
CKSSYB***K [F/V]
(RYB)
CKSRYB***K [F/V]
(CH)
CCSSCH***J [F/V]
.
***/** without instruction
CEHVAW***M** [F/V]
HD-V9000
6
7
2 9 9 4 2 8
DECM SERVICE ASSY (DXX2610)
• MAIN CPU (1/3) BLOCK
PIN HEADER
BUS BUFFER IF
A 2,11/18
A 2-5,7,9/18
2:10D;11:11J;11:13D;11:4D
#RESET_FLASH
HOST_BUS
12A;8L;2:10C;2:10G;2:1B;3:10I;3:11B
;3:13B;3:13E;3:5G;4:3D;5:13B;7:6K;9:2C
HOST_ADRS0
HOST_ADRS1
HOST_ADRS2
JTAG
15H HOST_ADRS3
HOST_ADRS4
TO CN1006
HOST_ADRS5
HOST_ADRS6
HOST_ADRS7
DEMITAS
HOST_ADRS16
HOST_ADRS17
HOST_ADRS18
HOST_ADRS19
HOST_ADRS20
HOST_ADRS21
HOST_ADRS22
HOST_ADRS23
HOST_DATA0
HOST_DATA1
HOST_DATA2
HOST_DATA3
HOST_DATA4
HOST_DATA5
HOST_DATA6
HOST_DATA7
A 18/18
HOST_DATA16
# D T R
HOST_DATA17
18:4G A 11/18
R E F _ L O S T
HOST_DATA18
11:12C
S T O P _ S T
18:4G HOST_DATA19
A 18/18
HOST_DATA20
HOST_DATA21
HOST_DATA22
HOST_DATA23
A 12/18
# C S _ O S D
1 5 0 5 8 2 9 9 4
12:6D
A 11/18 #HOST_WE0
# C S _ G S 4 9 1 1
11:11E
#HOST_WE1
# C S _ G S 4 9 0 0
11:5D
A 14/18
#HOST_WE2
# C S _ A D A C
14:2B
A 2/18
#HOST_WE3
E N A _ C O M M
1K;2:14C;2:14E #HOST_DREQ1
A 2/18
A 18/18
# O S C _ S T P #CS_FLASH
18:7G 2:12E;2:16G
# G E N L O C K
11:5E A 2,9/18 2:16H;9:3I
A 11/18
G S P I _ S C K
11:11E
G S P I _ D O U T
11:11E
# R E S E T _ C L K C H N G
4:7L
A 4/18
# R E S E T _ F P G A
4:7L
L E D _ S D A C T _ C P U JTAG CONNECTOR
A 18/18
18:4G
A 2/18 12B;14C;14H
L T 1
JTAG
2:14E
JTAG
15H
TO CN1006
TP1310
TCK
TP1311
TRST
TP1312
TDO
TP1313
ASEBRKAK
TP1314
TMS
TP1315
TDI
TP1316
RESET_JTAG
A 4/18
I R Q 1 _ F P G A
4:7L
A 8,10,12,13,16/18
8:8A;10:8C;12:1F;13:1G;16:1F
I2C
SDA
SCL
TP1317
M P M D
7K
SCIF
A 2,4,12,14,15,18/18
TP1318
D I P _ 0
9L
TP1319
D I P _ 1
7L
CN1008 OPEN=CPU CHIP MODE
CN1009 OPEN=IPL NORMAL MODE
R1253 OPEN=PRODUCT NORMAL MODE SHORT=PRODUCT INSPECTION MODE
DEFAULT SETTI NG=ALL OPEN
m
co
7
8
9 9
A
CN1001
1 2 HOST_ADRS15
3 4
HOST_ADRS14
5 6
HOST_ADRS13
7 8 B
HOST_ADRS12
9 1 0 HOST_ADRS11
1 1 1 2
HOST_ADRS10
1 3 1 4
HOST_ADRS9
1 5 1 6
HOST_ADRS8
NM
CN1002
1 2 #HOST_CS0
3 4
#HOST_CS1
5 6
#HOST_CS2
7 8 #HOST_CS3
9 1 0 #HOST_RAS
1 1 1 2
#HOST_CAS
1 3 1 4
HOST_ADRS25
1 5 1 6 HOST_ADRS24
NM
CN1003
1 2
HOST_DATA15
3 4
HOST_DATA14
5 6 HOST_DATA13
7 8 HOST_DATA12
9 1 0
HOST_DATA11
1 1 1 2
HOST_DATA10
1 3 1 4 HOST_DATA9
1 5 1 6 HOST_DATA8
NM
CN1004 C
1 2
HOST_DATA31
3 4
HOST_DATA30
5 6 HOST_DATA29
7 8
HOST_DATA28
9 1 0
HOST_DATA27
1 1 1 2 HOST_DATA26
1 3 1 4 HOST_DATA25
1 5 1 6
HOST_DATA24
NM
CN1005
2 8 9 9
1 2
HOST_R/#W
3 4 #HOST_RD
5 6
#HOST_BS
7 8
HOST_CKE
9 1 0
2:4D
HOST_DQMLU
1 1 1 2
2:2D
HOST_DQMLL
1 3 1 4
#CS_LAN 2:6D
HOST_DQMUL
1 5 1 6
2:8D
HOST_DQMUU
NM A 2/18
GNDD
D
V+3R3D_CON
C N 1 0 0 6
TCK N.C.
1 8
TRST GND
2 9
TDO GND
3 1 0
ASEBRK UVCC
4 1 1
TMS GND
5 1 2
TDI GND
6 1 3
RESET GND
7 1 4
N M
7614-6002
GNDD
V+3R3D_CON
R 1 1 5 0
1 8
2 7
3 6
4 5
TP1256 TP1257
1 0 k
A2-2PA-2.54DSA(71) E
C N 1 0 0 8 N M
1 2
A2-2PA-2.54DSA(71)
C N 1 0 0 9 N M
1 2
R 1 2 5 4
N M
R 1 2 5 3
N M
GNDD
TEST MODE SET
SHORT=CPU EMU MODE
SHORT=IPL MONITOR MODE
F
A
1/18
61
8