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AN-6094
added in to Equation (23), considering the V
caused by Burst Mode operation at no-load condition.
N
+
(
)
P
V
V
O
F
N
S
V
DL
N
+
S
V
V
DL
O
N
P
Figure 10. Voltage Stress on MOSFET and Diode
Figure 11. V
and Winding Voltage
DD
© 2012 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/27/12
ripple
DD
(Design Example)
For a 700 V MOSFET to have 35% margin on V
the reflected output voltage should be:
=
nom
373
V
DS
∴
V
RO
Setting V
=71 V, N
RO
N
V
=
P
RO
+
(
N
V
S
o
Then, the voltage stress of diode is obtained as:
N
=
nom
S
V
D
N
P
The allowable minimum V
tolerances of UVLO. Considering voltage ripple on V
caused by burst operation at no-load condition, a 2 V
margin is added for V
condition, calculated as:
N
min
=
A
V
DD
N
S
N
+
A
(5 0.35) 0.7
N
S
N
∴
>
1.5
A
N
S
To minimize the power consumption of the IC by
minimizing V
determined as 1.6.
[STEP-4] Design the Transformer
Figure 12 shows the MOSFET conduction time (t
diode current discharge time (t
conduction time (t
determine how much non-conduction time (t
DCM operation. The diode current discharge time
increases as the output voltage drops in CC Mode. Even
though t
decreases as output voltage drops, t
ON
proportional to the square root of the output voltage, while
t
is inversely proportional to the output voltage. Thus,
DIS
the sum of t
ON
the t
, forcing the flyback converter with a fixed
OFF
switching frequency into CCM operation as the output
voltage drops.
Thus, operating point B, where the frequency reduction
starts, is the worst case for determining the non-
conduction time (t
should be large enough to cover the transformer variation
and frequency hopping. However, too large t
RMS current of the primary side current. It is typical to
set t
as 15-20% of the switching period.
OFF
7
+
<
×
=
0.65 700 455
V
RO
<
82
V
/ N
is obtained as:
P
S
71
=
=
13.27
)
5.35
V
F
max
+
=
33.13
V
V
V
DL
O
is 5.3 V, considering the
DD
voltage calculation at no-load
DD
max
+
−
>
+
(
)
V
V
V
V
O
F
FA
UVLO
−
>
+
5.3 2
at no-load condition, N
DD
), and diode non-
DIS
). For the transformer design, first
OFF
and t
tends to increase, which reduces
DIS
), as illustrated in Figure 12. t
OFF
www.fairchildsemi.com
nom
,
DS
V
DD
V
MRGN
/ N
is
A
S
),
ON
) is used in
OFF
is
ON
OFF
increases
OFF
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