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AN-6094
[STEP-2] Determine the DC Link Capacitor
(C
) and the DC Link Voltage Range
DL
It is typical to select the DC link capacitor as 2-3 µF per
watt of input power for universal input range (90-
264 V
) and 1 µF per watt of input power for European
AC
input range (195~265 V
). With the DC link capacitor
rms
chosen, the minimum DC link voltage is obtained as:
min
min 2
=
⋅
2 (
)
V
V
@
DL
A
LINE
min
where V
is the minimum line voltage; C
LINE
DC link capacitor; f
is the line frequency; and D
L
the DC link capacitor charging duty ratio defined as
shown in Figure 9, which is typically about 0.2.
The maximum DC link voltage is given as:
max
max
=
⋅
2
V
V
DL
LINE
max
where V
is the maximum line voltage.
LINE
The minimum DC link voltage and its ripple change with
input power. The minimum input DC link voltage at
operating point B is given as:
min
=
⋅
min 2
2 (
)
V
V
@
DL
B
LINE
The minimum input DC link voltage at operating point C
is given as:
min
=
⋅
min 2
2 (
V
V
@
DL
C
LINE
Figure 9. DC Link Voltage Waveforms
By choosing two 6.8 µF capacitors
(Design Example)
in parallel for the DC link capacitor, the minimum and
maximum DC link voltages for each condition are
obtained as:
min
min 2
=
⋅
2 (
)
V
V
@
DL
A
LINE
8.22(1 0.2)
2
=
⋅
−
2 (90)
⋅
2 6.8 10
max
=
⋅
=
2 264 373
V
V
DL
min
=
⋅
min 2
2 (
)
V
V
@
DL
B
LINE
−
7.07(1 0.2)
2
=
⋅
−
2 (90)
⋅
×
2 6.8 10
© 2012 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/27/12
−
(1
)
P
D
@
−
IN
A
ch
(15)
⋅
C
f
DL
L
is the
DL
ch
(16)
−
(1
)
P
D
@
−
IN
B
ch
(17)
⋅
C
f
DL
L
−
(1
)
P
D
@
−
)
IN
C
ch
(18)
⋅
C
f
DL
L
−
(1
)
P
D
@
−
IN
A
ch
⋅
C
f
DL
L
−
=
90
V
−
×
6
⋅
60
−
(1
)
P
D
@
−
IN
B
ch
⋅
C
f
DL
L
=
96
V
−
6
⋅
60
min
=
⋅
2 (
V
V
@
DL
C
LINE
2.46(1 0.2)
2
=
⋅
−
2 (90)
⋅
2 6.8 10
[STEP-3] Determine Transformer Turns
Ratio
Figure 10 shows the MOSFET drain-to-source voltage
waveforms. When the MOSFET is turned off, the sum of
the input DC link voltage (V
is
reflected to the primary side is imposed across the
MOSFET, calculated as:
=
max
+
nom
V
V
V
DS
DL
where V
is reflected output voltage, defined as:
RO
N
=
+
p
(
N
V
V
V
RO
O
F
N
s
where N
and N
are number of turns for the primary
P
S
side and secondary side, respectively.
When the MOSFET is turned on; the output voltage,
together with input voltage reflected to the secondary, are
imposed across the secondary-side rectifier diode
calculated as:
N
=
max
+
nom
S
V
V
D
DL
N
P
As observed in Equations (19), (20), and (21); increasing
the transformer turns ratio (N
stress on the MOSFET while reducing voltage stress on
the rectifier diode. Therefore, the N
determined by the trade-off between the MOSFET and
diode voltage stresses.
The transformer turns ratio between the auxiliary winding
and the secondary winding (N
determined by considering the allowable IC supply
voltage (V
) range. The V
DD
condition, as shown in Figure 11, where the minimum
V
typically occurs at minimum load condition. Due to
DD
the voltage overshoot of the auxiliary winding voltage
caused by the transformer leakage inductance; the V
operating point C tends to be higher than the V
minimum load condition.
The V
at minimum load condition is obtained as:
DD
N
min
≅
+
(
A
V
V
V
DD
O
N
S
where V
is the diode forward-voltage drop of the
FA
auxiliary winding diode.
The transformer turns ratio should be determined such
min
that V
is higher than the V
DD
N
+
−
(
)
A
V
V
V
O
F
FA
N
S
min
Since the V
is related to standby power consumption,
DD
smaller
N
/ N
leads
A
S
consumption. However, 2~3 V margin (V
6
−
(1
)
P
D
@
min 2
−
IN
C
ch
)
⋅
C
f
DL
L
−
=
117
V
−
6
×
⋅
60
) and the output voltage
DL
RO
)
N
V
O
/ N
) increases voltage
P
S
/ N
should be
P
S
/ N
) should be
A
S
voltage varies with load
DD
−
)
V
F
FA
UVLO voltage, such as:
DD
max
>
+
V
V
UVLO
MRGN
to
lower
standby
) should be
MRGN
www.fairchildsemi.com
(19)
(20)
(21)
at
DD
at
DD
(22)
(23)
power
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