ON Semiconductor Fairchild FAN302HL Design Manualline page 15

AN-6094
In STEP-8, the post LC filter is
(Design Example)
designed with two 330 µF capacitors and a 1.8 µH
inductor. Since the resonance frequency of the post LC
filter is 9.2 kHz, the bandwidth of the feedback loop
should be less than 1/3 of the cut-off frequency to
minimize the phase drop caused by the post LC filter.
Thus, the target bandwidth of the feedback loop is
determined as around 3 kHz.
To simplify analysis, the inductor of the post filter is
ignored, since the bandwidth is below the cutoff
frequency of post LC filter. The effective output
capacitance and its effective series resistance are given as:
μ μ
= × =
330 2 660
C F
OUT
= Ω = Ω
100 / 2 50
R m m
ES
The slope of current sensing signal for high line is
obtained as:
⋅
⋅
373 1.2
V R V
= =
DL CS
m
μ
530
L H
m
The slope of internal slope compensation is obtained as:
0.3 0.3
V
= =
m
a × μ
1/ 7.14
f D
max
S
Then, the gain G for high line and maximum load
V
condition is obtained as:
N
1
m V
= ⋅ ⋅
O
G
V
3 +
PK
m m
R I
a
CS DS
The system pole and zero are obtained as:
2
ω
= =
727 /
rad s
p
R C
L OUT
1
ω
= =
30,300
Z
R C
ES OUT
With R =0 Ω, C =10 nF, R
F FR
C =4nF (including output capacitance of opto-
FB
transistor), and R =42 kΩ; 3 kHz bandwidth with 53
FB
phase margin is obtained. For C
an opto-transistor is assumed to be 3 nF and a 1 nF
external capacitor is used.
© 2012 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/27/12
F
μ
=
0.845 /
V s
V
μ
=
0.066 /
V s
×
0.64
s
=
3
/
rad s
=1 kΩ, R =50 kΩ,
bias F1
, output capacitance of
FB
[STEP-11] Choose Startup Resistor for HV Pin
Figure 22 shows the high-voltage (HV) startup circuit for
FAN302 applications. Internally, the JFET is used to
implement the high-voltage current source, whose
characteristics are shown in Figure 23. Technically, the
HV pin can be directly connected to the DC link (V
However, to improve reliability and surge immunity, it is
typical to use a ~100 k Ω resistor between the HV pin and
the DC link. The actual HV current with a given DC link
voltage and startup resistor is determined by the
intersection point of V-I characteristics line and load line,
as shown in Figure 23.
During startup, the internal startup circuit is enabled and
the DC link supplies the current, I
up capacitor, C , through R
DD
reaches V , the internal HV startup circuit is disabled
DD-ON
and the IC starts PWM switching. Once the HV startup
circuit is disabled, the energy stored in C
the IC operating current until the transformer auxiliary
winding voltage reaches the nominal value. Therefore,
C should be properly designed to prevent V
DD
dropping to V before the auxiliary winding builds up
DD-OFF
enough voltage to supply V
The startup time with a given C
C V
=
.
DD DD ON
t
−
start
(
I I
−
HV DD ST
°
Figure 22. HV Startup Circuit
I
HV
3.5mA
V
DL
R
HV
1.5mA
0.8mA
100V
V
DL
Figure 23. V-I Characteristics of HV Pin
With 100 kΩ HV resistor and 33 µF
(Design Example)
V capacitor, the maximum startup time is:
DD
C V
=
.
DD DD ON
t
−
start (
I I
−
HV DD ST
14
, to charge the hold-
HV
. When the V
HV DD
should supply
DD
DD
.
DD
capacitor is given as:
DD
)
−
V V
=
DL HV
I
HV
R
HV
200V 300V 400V
500V
V
HV
μ
⋅
33 16
V
= =
1.32 s
−
) 0.8 0.4
mA mA
www.fairchildsemi.com
).
DL
voltage
from
(53)