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Summary of Contents for Nuvoton ISD2360
- Page 1 ISD2360 Design Guide ISD ChipCorder ISD2360 Design Guide Publication Release Date:Nov 20, 2014 Revision V1.14...
- Page 2 Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result in or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
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Page 3: Table Of Contents
ISD2360 Design Guide Table of Contents- LIST OF TABLES- ............................VII GENERAL DESCRIPTION ........................1 ................................1 VERVIEW ................................1 EATURES PIN CONFIGURATIONS ........................3 ............................3 IAGRAMS ..........................4 ESCRIPTIONS BLOCK DIAGRAM ..........................7 DEVICE STATUS ........................... 8 ........................8... - Page 4 ISD2360 Design Guide 7.1.1 Memory Format .......................... 24 7.1.2 Memory Protection ........................25 ............................. 26 OICE ROMPT ............................26 OICE ACRO 7.3.1 Voice Macro Commands ......................26 7.3.2 System-Reserved Voice Macros ....................28 Sample Project Voice Macros ....................28 7.3.3 Sample_1: A Simple Trigger-To-Play Project ..................
- Page 5 ISD2360 Design Guide 11.2.2 Speaker Outputs ......................... 59 11.2.3 DC Parameters ........................... 60 11.2.4 SPI Timing ........................... 60 12. PACKAGE DIMENSIONS ........................62 13. ORDERING INFORMATION ....................... 64 14. REVISION HISTORY ........................... 65 Release Date: Nov 20, 2014 - v -...
- Page 6 ISD2360 Design Guide List of Figures- Figure 2-1 ISD2360 QFN 32-Lead Package .................. 3 Figure 2-2 ISD2360 SOP 16-Lead 300 mil Package ..............4 Figure 3-1 ISD2360 Block Diagram ....................7 Figure 5-1 GPIO Pad Structure ....................11 Figure 5-2 ISD2360 Signal Path ....................12 Figure 5-3 PWM Output Thermal Shutdown ................
- Page 7 ISD2360 Design Guide List of Tables- Table 2-1 32-Lead QFN Pin Descriptions ..................4 Table 2-2 SOP 16-Lead Pin Descriptions ..................6 Table 4-1 Device Status Register Description ................8 Table 4-2 Interrupt Status Register Description ................9 Table 5-1 AF1/AF0 Bit Combinations for GPIO Pin Function Mode ..........10 Table 5-2 GPIO Pin Function Modes ...................
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Page 8: General Description
Flash storage, an integrated audio signal path with up to 3 channel concurrent playback and a Class D speaker driver capable of delivering 1 W of power. The ISD2360 utilizes Flash memory, in 1-Kbyte sectors, to provide non-volatile audio playback for a single- chip audio playback solution for up to 64 seconds duration (based on 8 kHz/4-bit ADPCM compression). - Page 9 ISD2360 Design Guide Enhanced ADPCM: 2, 3, 4 or 5 bits per sample Variable bit-rate optimized compression allows best possible compression given a metric of Signal-to-Noise Ratios (SNR) and background noise levels Clock Source: Internal oscillator with internal reference, factory trimmed to ±1% deviation at room temperature ...
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Page 10: Pin Configurations
ISD2360 Design Guide Pin Configurations Pin Diagrams The ISD2360 ChipCorder is available in QFN 32-Lead and SOP 16-Lead 300 mil packages, as shown in Figure 2-1 and Figure 2-2. GPIO0/MOSI GPIO0/MOSI GPIO4/RDY/BSYB GPIO4/RDY/BSYB ISD2360 VSSD VSSD GPIO3/INTB GPIO3/INTB ISD2360 QFN32... -
Page 11: Pin Descriptions
Figure 2-2 ISD2360 SOP 16-Lead 300 mil Package 2.2 Pin Descriptions The pin descriptions for the ISD2360 in QFN 32-Lead package and in SOP 16-Lead 300 mil package are provided in Table 2-1 and Table 2-2, respectively. Table 2-1 32-Lead QFN Pin Descriptions... - Page 12 GPIO3/INTB Can be configured as a General Purpose I/O pin. Output pin reports the status of data transfer on the SPI interface. ―High‖ indicates the ISD2360 is ready to accept new GPIO4/RDY/ BSYB SPI commands or data. Can be configured as a General Purpose I/O pin.
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Page 13: Table 2-2 Sop 16-Lead Pin Descriptions
GPIO3/INTB Can be configured as a General Purpose I/O pin. Output pin reports the status of data transfer on the SPI interface. ―High‖ indicates the ISD2360 is ready to accept new GPIO4/RDY/ BSYB SPI commands or data. Can be configured as a General Purpose I/O pin. -
Page 14: Block Diagram
ISD2360 Design Guide Block Diagram The major functional blocks of the ISD2360 ChipCorder, as shown in Figure 3-1 include: SPI and GPIO Interfaces Memory Management and Command Interpreters De-Compression Digital Signal Path Filtering, Mixing, Sampling and Volume Control ... -
Page 15: Device Status
During an SPI transaction, for all commands except digital reading commands, the device status byte is sent back from device via MISO for every byte of data sent to the ISD2360.The details of the device status bits are shown in Table 4-1. -
Page 16: Device Interrupt Register
ISD2360 Design Guide 4.2 Device Interrupt Register Whenever the ISD2360 generates an interrupt, the Interrupt Status Register holds flags that indicate the type of interrupt that was generated. The interrupt bits are shown in Table 4-2. These flags will remain set until a READ_INT command clears them and the hardware interrupt pin (INTB) is set. -
Page 17: Device Configuration
All configuration registers are reset to their default values when there is a reset condition. When the ISD2360 is in Power Down Mode, a group of 3 V registers will retain their values while all other registers lose their content. Note the difference between Power Down and Power Off: Power Down means the device is entering the standby state with the PD bit set;... -
Page 18: Special 3 V Registers
5.3.2 Special 3 V Registers The ISD2360 device contains a group of special registers that can keep their value during power down. This special group includes registers in the range of 0x14-0x16 and 0x19-0x2F, and they are powered by an internal regulated 3V power supply. -
Page 19: Signal Path Configuration
Transitions on the GPIO pins can generate a GPIO_INT interrupt. At the moment when the ISD2360 goes into a power down state, the status of the GPIO pins are latched. If the GPIO pin is configured as a triggering pin (interrupt enabled) and toggling on the pin is the valid triggering type indicated by AF1 and AF0, then when the toggling happens the ISD2360 device will execute a wake-up event. -
Page 20: Device Checksum
ISD2360 Design Guide 5.5 Device Checksum The ISD2360 is able to calculate the hardware checksum from the beginning of memory to a specified end address. To start a checksum calculation, the user should first reset the circuit by writing one followed by a zero, to the RST_CHECKSUM bit in Checksum Reset Register, and then issue the SPI CHECKSUM command to initiate the calculation. -
Page 21: Indirect Reference Registers
SPI when the FIFO has data – when RDY/BSYB is high. For digital write operations, the host controller should only try to write into ISD2360 via SPI when the FIFO has vacant space – when RDY/BSYB is high. -
Page 22: Fast De-Bounce For Gpio Trigger
The default value of FAST_DEB bit in the De-bounce Time Control Register is zero, which gives 20 ms de-bounce time for the ISD2360 GPIO trigger. Writing one to this bit enables the fast de-bounce feature, and the de-bounce time will be reduced to 8 ns. Fast de-bounce time should be used only in such situations in which fast speed is desired, and more importantly, the triggering signal is very clean without glitches –... -
Page 23: Operational Description
Operational Description Overview In almost all cases, the ISD2360 needs to be programmed before being put into use in the field. A GUI software, ISD-VPE2360 (Voice Prompt Editor for ISD2360 device) can be used to generate the application image file. Once the image file is ready, the user can choose to program the devices before populating them onto target systems, or to perform in-system programming in field. -
Page 24: Audio Compression And De-Compression
Power-On Initialization (POI) sequence and executes the POI Voice Macro, VM#0. When the ISD2360 receives a Power Up command (PU) under power down state, it begins a power-up initialization (PU) sequence and executes PU Vocie Macro, VM#1. Note that if the... -
Page 25: Gpio Trigger
(powered up). Figure 6-1 shows the device initialization execution flow. Once powered on, no matter if it is in PU or PD state, the ISD2360 device constantly detects edge transition on all GPIO pins. If an edge transition is detected and it meets the triggering condition defined by the AF1 and AF0 registers, then it a valid trigger occurs. -
Page 26: Spi Or Gpio Trigger
6.6.2.1 Pulling SSB low automatically claims the SPI interface Each of the six ISD2360 GPIO pins can be configured to work at the one of the following four function modes: GPIO pin, alternate function pin, falling-edge triggering pin or falling-and- rising-edge triggering pin. -
Page 27: Pulling Ssb Low Does Not Affect The Triggering Capability
SPI operation, the user must check the device status before sending the SPI commands. Unlike the SPI operation, in GPIO Trigger operation, the ISD2360 always executes the associated VM in the assigned channel, regardless the current status of the channel. That is,... -
Page 28: Volume Control Via Gpio Trigger
ISD2360 Design Guide When the power supply drops to ~1.9 V, the 3 V registers of the ISD2360 start to lose their values. If the power supply continues to drop to a level lower than the POR (Power On Reset) voltage, which is about 0.9 V, then once the power supply rises back to normal working... -
Page 29: Vm Jump And Channel Counter Commands
A GPIO triggering associated VM preempts only its own channel; the execution in other channels is not affected. In total, the ISD2360 device can have 3 channels running in parallel. If a trigger VM is assigned to ―all channels‖, i.e. 0x11 being written into the corresponding GPIOn_TRIG_VH_SEL bits, the result is that the VM will preempt all 3 channels when triggered;... -
Page 30: Memory Management
ISD2360 Design Guide Memory Management The internal Flash memory of the ISD2360 provides 2 Mbits of storage space. Its 2, 097, 152 bits of memory are organized into 256-sectors of 1024-bytes each. The ISD2360 is a playback-only device and usually must be pre-programmed before use. A GUI software ISD-VPE2360, provided by Nuvoton, can be used to generate the ISD2360 Flash image file. -
Page 31: Memory Header
ISD2360 Design Guide Memory Header 7.1.1 Memory Format The memory header is located from address 0x000000 and holds all the critical information about the memory organization upon which the device depends for all kinds of operations. Table 7-1 shows the typical memory data organization, including the memory header format, when there is no user data involved. -
Page 32: Memory Protection
It may be desirable to protect portions of the internal memory from write/erase or interrogation (read) operations. The ISD2360 allows this by setting a Protection Memory Pointer (PMP) with which the user can protect an address range from the beginning of memory to the sector containing the PMP pointer. -
Page 33: Voice Prompt
ISD2360. Once it gets running, the command data in the script will be read from memory and executed by the device. For the ISD2360, VM can be called upon to run either by an SPI command or by a GPIO trigger event. -
Page 34: Table 7-4 Voice Macro Commands
FINISH Finish the Voice Macro and exit. The GUI software ISD-VPE2360 provided by Nuvoton can be used to generate the VM command scripts for a project. The user can rely on this GUI software to implement all necessary VMs when creating the device image file needed for pre-programming before the device is put into use. -
Page 35: System-Reserved Voice Macros
―two‖ when the GPIO1 button is pressed, and so on. How to configure: Create a falling edge when a button is pressed, and let the ISD2360 respond to the button-press event by executing the GPIO trigger associated Voice Macro. -
Page 36: Figure 7-2 Sample_Project_1 Configuration
ISD2360 Design Guide In the associated VM, simply play a VP then power down. See Figure 7-2 for detailed configuration information. Figure 7-2 Sample_Project_1 Configuration The following exlpains the POI VM: REG2, 0x44) write 0x44 into reg0x02; enable Decoder and PWM output path;... -
Page 37: Sample_2: Channel Mixing With Volume Control
ISD2360 Design Guide Once executed, at the end of POI VM, the device will play a sound effect ―FastBeep‖ then power down. As long as there is power applied, all 3 V registers configured in this VM will retain their values except the Path Control Register. This enables the device to continue detecting a falling edge during PD. -
Page 38: Figure 7-3 Sample_Project_2 Configuration
ISD2360 Design Guide Figure 7-3 Sample_Project_2 Configuration The following exlpains the POI VM: REG2, 0x44) write 0x44 into reg0x02; enable Decoder and PWM output path; CFG( VOLC, 0x04) write 0x04 into reg0x03; set attenuation at 4*(-0.25)dB value; CFG( ... -
Page 39: Sample_3: Driving Gpio Using The Channel Counter
Pressing the GPI1 button once starts loop play of a sound effect; pressing the button twice stops the play. This ―play-stop-play-stop‖ pattern repeats. During play, the ISD2360 also drives the GP104 and GP105 LED on and off, as determined by Channel Counter 0. The GPI1 trigger play pattern is replicated on GP102, the volume is increase by pressing the GP100 button and the volume is decreased by pressing the HP104 button. -
Page 40: Figure 7-4 Sample_Project_3 Configuration
ISD2360 Design Guide Figure 7-4 Sample_Project_3 Configuration The following exlpains the POI VM: REG2, 0x44) write 0x44 into reg0x02; enable Decoder and PWM output path; CFG( CFG(GPIO_TRIG_CH_SEL_L, 0x24) write 0x24 into reg0x14, assign channel 0 to VM associated with GPIO0;... -
Page 41: User Data
That is, for every Voice Prompt or Voice Macro script, the data chunk must be continuous and should not be separated by reserved sections. Thus, the ISD2360 device hardware can successfully fetch data and finish the play for audio operation or VM execution. -
Page 42: Serial Peripheral Interface
Out - MISO). Also, for some transactions requiring data flow control, a RDY/BSYB signal (pin) is available. The ISD2360 supports SPI Mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data is sampled at the rising edge of SCLK. An SPI transaction begins on the falling edge of SSB and its waveform is illustrated in Figure 8-1. -
Page 43: Figure 8-2 Rdy/Bsyb Timing For Spi Write Transactions
The INT pin will go low to indicate (1) data overrun/overflow when sending data to the ISD2360; or (2) invalid data from ISD2360. Refer to Figure 8-3 for the timing diagram in which RDY/BSYB is ignored. -
Page 44: Spi Commands
ISD2360 Design Guide SPI Commands The ISD2360 provides SPI commands to play audio, query device status, perform digital memory operations and configure the device. Table 8-1 provides a list of all SPI commands and their function descriptions. Table 8-1 SPI Commands Byte 4 …... -
Page 45: Spi Command Vs Tatus
ISD2360 Design Guide Byte 4 … Byte n Instructions Byte 0 Byte 1 Byte 2 Byte 3 Description RD_CLK_CFG 0xB6 Read clock configuration register. Write data D0…Dn to WR_CFG_REG 0xB8 REG[7:0] configuration register(s) starting D0[7:0], …Dn[7:0] at configuration register REG. -
Page 46: Spi Command Descriptions
ISD2360 Design Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Instructions Op Code DBUF_RDY CH2_BSY CH1_BSY CH0_BSY DIG_BSY ERASE_MEM 0x24 CHIP_ERASE 0x26 CHECKSUM 0xF2 PWR_UP 0x10 PWR_DN 0x12 SET_CLK_CFG 0X34 RD_CLK_CFG... -
Page 47: Play_Vp@Rn - Play Voice Prompt @ Rn
ISD2360 Design Guide PLAY_VP@Rn – Play Voice Prompt @ Rn 8.4.1.2 PLAY_VP@Rn Host Controller 0xAE Rn[7:0] Byte Sequence: ISD2360 Status Byte Status Byte Description: Play Voice Prompt with Index stored in Rn register Interrupt CMD_ERR if not accepted. CMD_FIN when playback is finished. -
Page 48: Exe_Vm -Execute Voice Macro
ISD2360 Design Guide command will be ignored. If the command is terminated after the command byte is sent, no interrupt will be generated. Once playback is finished a CMD_FIN interrupt will be generated. This command will be ignored when SPI_CMD_CH=3. -
Page 49: Stop - Stop The Play Operations
Generation: generates the interrupt. This command stops the audio command active on a given channel in the ISD2360. If a PLAY_MSG@, PLAY_VP, EXE_VM or PLAY_SIL command is active, playback is stopped immediately. The STOP command flushes the audio command buffer, so that any command queued in the buffer when a STOP is issued will not be executed. -
Page 50: Spi_Snd_Dec - Spi Send Compressed Data For Decoding
ISD2360 Design Guide commands include PLAY_VP, PLAY_VP@Rn, PLAY_VP_LP, PLAY_VP_LP@Rn, EXE_VM and EXE_VM@Rn. (3) The SPI_PCM_READ command follows. Multiple SPI_PCM_READ commands can be sent. (4) To finish receiving data, a STOP command is sent and the device will generate a CMD_FIN interrupt. -
Page 51: Device Status Commands
Description: Query device status. This command queries the ISD2360 device status. For details, see Section 4 Device Status. If the device is powered up, the two status bytes will be repeated for each two dummy bytes sent to the SPI interface. If the device is powered down, only one status byte, 8oh, goes to the SPI interface at the same time the command is sent. -
Page 52: Read_Id - Read Device Id
Byte Description: Return ID of ISD2360 This command queries the ISD2360 and returns four bytes to identify the ISD2360 part, the manufacturer, and the size and type of internal memory of the device. The bytes returned are: One byte ISD2360 Family ID, which is 0x05. -
Page 53: Dig_Write - Digital Write
OVF_ERR interrupt will be generated. Once the SPI transaction has ended, the ISD2360 will finish the Flash write operation. When this operation is complete, the ISD2360 will generate a WR_FIN interrupt. While the device is actively writing to Flash memory, the CMD_BSY bit will be active. -
Page 54: Chip_Erase - Erase Entire Memory
ISD2360 Design Guide CHIP_ERASE – Erase Entire Memory 8.4.3.4 CHIP_ERASE Host Controller 0x26 0x01 Byte Sequence: ISD2360 Status Byte Status Byte Description: Initiate a mass erase of memory. Interrupt CMD_ERR if the device is busy and cannot accept a command. CMD_FIN when Generation: the erase operation completes. -
Page 55: Device Configuration Commands
ISD2360 Design Guide 8.4.4 Device Configuration Commands Six commands are used to configure the ISD2360. These commands are used to set up the clocking regime of the device (including the clock source and setting the master sample rate) and to configure the audio signal path, compression and sample rate. The signal path, compression and sample rate configuration are controlled by 48 bytes of the configuration register. -
Page 56: Rd_Clk_Cfg - Read Clock Configuration Register
ISD2360 Design Guide RD_CLK_CFG – Read Clock Configuration Register 8.4.4.4 RD_CLK_CFG Host Controller 0xB6 0xXX Byte Sequence: ISD2360 Status Byte CFG_CLK[7:0] Description: Reads the clock configuration register. This command reads the Clock Configuration Register. WR_CFG_REG – Write Configuration Register 8.4.4.5 WR_CFG_REG …... -
Page 57: Register Operations
ISD2360 Design Guide Register Operations Table 9-1 Register Operations Register Function Name Description 7 6 5 4 3 2 1 Reserved Select system clock source. Use SET_CLK_REG and RD_CLK_REG to access this register. Clock 00 = Internal Oscillator with internal Resistor... - Page 58 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 Sample Rate: 000 = 4 KHz 001 = 5.33 KHz 010 = 6.4 KHz 011 = 8 KHz Sample Rate 100 = 12.8 KHz Overwrite 101 = 16 KHz...
- Page 59 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 VOLC[7:0] sets the PWM output attenuation. 0.25dB for each step. 0000 0000 = 0dB attenuation. Maximum volume. 0000 0001 = -0.25dB. Volume VOLC 0000 0010 = -.50 dB.
- Page 60 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 Time Division Multiplexing control TDM_OFF 0 = enable. enable multi- channel feature. 1 = disable multiple-channel feature. Reserved Channel Channel control via SPI interface Control 00 = Channel 0 is selected.
- Page 61 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 Reserved Assign a channel(s) in which the GPIO5 trigger VM executes. 00 = Channel 0 GPIO5_TRIG_CH 01 = Channel 1 GPIO _SEL 10 = Channel 2...
- Page 62 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 Reserved GPIO_PE[5] 0 = disable GPIO5 pull ; 1 = enable GPIO5 pull GPIO_PE[4] 0 = disable GPIO4 pull; 1 = enable GPIO4 pull Pull Enable GPIO_PE[3] 0 = disable GPIO3 pull;...
- Page 63 ISD2360 Design Guide Register Function Name Description 7 6 5 4 3 2 1 R1_H Indirect Reference Register R1 high byte value R1_H Default >> 0x00 reset value. Read/Write. R2_L Indirect Reference Register R2 low byte value R2_L Default >>...
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Page 64: Application Diagrams
A standard four-wire Serial Peripheral Interface (SPI) is used for communication between the ISD2360 and the host. The interface consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master Out Slave In - MOSI), and a data output (Master In Slave Out - MISO). -
Page 65: Gpio Trigger Standalone Application
ISD2360 Design Guide 10.2 GPIO Trigger Standalone Application The ISD2360 can operate in standalone mode by triggers applied to the device’s six General Purpose Input/Output (GPIO) pins. Voice Prompt and Voice Macro commands facilitate fast programming. VCCD GPIO0/MOSI VCCD 0.01 0.001... -
Page 66: Electrical Characteristics
ISD2360 Design Guide 11. Electrical Characteristics 11.1 Operating Conditions Table 11-1 Operating Conditions (Industrial Packaging) Condition Value Operating temperature range (Case temperature) -40° C to +85° C Supply voltage (V +2.4 V to +5.5 V Ground voltage (V Input voltage (V 0 V to 5.5 V... -
Page 67: Dc Parameters
ISD2360 Design Guide 11.2.3 DC Parameters Parameter SYMBOL typ [1] Max Units Conditions Supply Voltage VSS- 0.3x Input Low Voltage 0.7x Input High Voltage VSS- 0.3x IOL = 1mA Output Low Voltage 0.7x IOH = -1mA Output High Voltage kΩ... -
Page 68: Table 11-2 Spi Timing
ISD2360 Design Guide Table 11-2 SPI Timing Symbol Description Unit SCLK Cycle Time SCLK High Pulse Width SCKH SCLK Low Pulse Width SCKL Rise Time for All Digital Signals RISE Fall Time for All Digital Signals FALL SSB Falling Edge to first SCLK Falling Edge Setup Time... -
Page 69: Package Dimensions
ISD2360 Design Guide 12. Package Dimensions The ISD2360 is available in a QFN 32-Lead package, as shown in Figure 12-1 and an SOP 16-Lead package, as shown in Figure 12-2. Figure 12-1 QFN 32-Lead Package Release Date: Nov 20, 2014 - 62 - Revision v1.14... -
Page 70: Figure 12-2 Sop 16-Lead Package
ISD2360 Design Guide Figure 12-2 SOP 16-Lead Package Release Date: Nov 20, 2014 - 63 - Revision v1.14... -
Page 71: Ordering Information
ISD2360 Design Guide 13. Ordering Information I23XX Y Y I Temperature Duration I: Industrial -40 C to 85 C 60: 64 Seconds * Based on 8 kHz/4-bit ADPCM Lead-Free Y: Green Package Type Y: 32-Lead QFN S: 16-Lead SOP 300 mil... -
Page 72: Revision History
ISD2360 Design Guide Revision History Version Date Description December 21, 2011 Initial draft July 05, 2012 First release 1.11 August 23, 2012 SOP 16-Lead device: Replaced pin diagram, added pin descriptions. Commercial Parts Operating Conditions removed. Linguistic and format changes.