Digital Audio Input - Cirrus Logic CDB43131-GBK Manual

2.2 Digital Audio Input

2.2.1 Serial Audio I/O Headers
Headers J25 and J26, labeled ASP and XSP respectively, provide an interface for serial audio clocks and data. The
source of the clocks and data can be an external audio source such as an Audio Precision audio analyzer. The header
signals are described in the table below. The logic level on these pins is selectable by jumping J28 to 3.3 V or 1.8V.
Reference Designator
Audio signals to/from these headers are routed to/from the CS43131 using voltage-level translation buffers. The direction
of clock and data through these buffers is controlled using on-board TCA6424 I/O Expander IC. U9, U12, and U15
translate the signals on J25 and J26 from a voltage of 3.3 V or 1.8 V to the operational voltage of 1.8 V. The ASP signals
are then fed into J24, while the XSP signals are fed into J44. These 3x3 pin headers are for passing the I
CS8422 S/PDIF transceiver to the DUTs.
To avoid the latency caused by buffers for higher clock frequencies like 352.8 kHz or 384 kHz, the user can connect the
external audio source directly to pins on headers J24 and J44. The pinouts for headers J24 and J44 are shown in the
following tables.
6
Table 1 Serial Audio Header Pinout
Pins Pin Designation
J25 7
5
3
1
2,4,6,8
J26 7
5
3
1
2,4,6,8
Table 2 Pinouts for Header J24
Pin #
1
2
4
5
7
8
3,6,9
Table 3 Pinouts for Header J44
Pin #
1
2
4
5
7
8
3,6,9
Direction
MCLK I/O
SCLK I/O
LRCLK I/O
RXDAT Input
Ground Ground reference
MCLK I/O
SCLK I/O
LRCLK I/O
RXDAT Input
Ground Ground reference
Signal
SCLK1 from Buffer
SCLK1 to DAC
LRCLK1 from Buffer
LRCLK1 to DAC
SDIN1 from Buffer
SDIN1 to DAC
Ground
Signal
SCLK2 from Buffer
SCLK2 to DAC
LRCLK2 from Buffer
LRCLK2 to DAC
SDIN2 from Buffer
SDIN2 to DAC
Ground
CDB43131-GBK
Description
Master clock
Bit clock
Frame clock
Serial data
Board ground
Master clock
Bit clock
Frame clock
Serial data
Board ground
2
S data from the
DS1155V2DB1