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CL-PS7500FE Development Kit
Hardware User's Guide
Embedded Processors Division
Copyright © 1999 – Cirrus Logic Inc. All rights reserved.
This document describes the CL-PS7500FE development board provided by Cirrus Logic Inc. No warranty is given
for the suitability of this design for any purpose other than demonstrating functional operation of the CL-PS7500FE.
The information contained in this document is subject to change without notice.
Version 1.0
March 1999
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Summary of Contents for Cirrus Logic CL-PS7500FE
- Page 1 This document describes the CL-PS7500FE development board provided by Cirrus Logic Inc. No warranty is given for the suitability of this design for any purpose other than demonstrating functional operation of the CL-PS7500FE. The information contained in this document is subject to change without notice.
- Page 2 CL-PS7500FE Development Kit – Hardware User’s Guide ® March 1999 Version 1.0...
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Page 3: Table Of Contents
CL-PS7500FE Development Kit – Hardware User’s Guide ® Table of Contents Introduction................................6 Terms and Definitions............................6 Development Board .............................. 6 Main Feature Set ............................6 Population Options............................7 Board Set-up ..............................7 Power ................................8 Jumpers ................................. 8 Hardware Design Details ............................8 DRAM................................. - Page 4 Sources of Additional Information........................37 List of Tables Table 1: Chip Select Usage ............................10 Table 2: Interrupt request usage on the CL-PS7500FE....................11 Table 3: Recommended FLASH SIMMs........................11 Table 4: Boot ROM Enable/Disable Jumper - JP12 ....................12 Table 5: Boot ROM Size Selection Jumper –...
- Page 5 Figure 1: Null modem connection..........................8 Figure 2: Development Board Functional Block Diagram.................... 9 Figure 3: Physical Memory Map of the CL-PS7500FE ....................10 Figure 4: JP2 Jumper Pin Numbering ......................... 13 Figure 5: CS8900A Serial EEPROM Configuration Sequence .................. 28 Figure 6: Video Data Word Format ..........................
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Page 6: Introduction
® 1 Introduction The CL-PS7500FE development board is targeted at system designers who are developing CL-PS7500FE based hardware platforms. This document defines the baseline board-level hardware elements that comprise the Cirrus Logic CL-PS7500FE development board. This document references other documents for more specific details of processors and other devices (ICs) used on the design. -
Page 7: Population Options
ROM is enabled via a jumper and when selected, moves FLASH from an initial location of 0x0000:0000 in the CL-PS7500FE’s memory to 0x0100:0000, while switching the boot ROM into location 0x0000:0000. When the boot ROM is not selected, it will not be addressable by the CPU. -
Page 8: Power
SnA status select. This line is a processor clock control line used to set the relationship between MCLK and FCLK for the CL-PS7500FE processor. If a jumper is installed on this pin, the memory system clock and the CPU clock run at different rates. If low, the two clocks are driven by the clock signal entering on the MCLK pin. -
Page 9: Figure 2: Development Board Functional Block Diagram
CL-PS7500FE Development Kit – Hardware User’s Guide ® Figure 2: Development Board Functional Block Diagram Figure 3 illustrates how physical devices are mapped into the CL-PS7500FE’s memory space. Version 1.0 March 1999... -
Page 10: Table 1: Chip Select Usage
CL-PS7500FE Development Kit – Hardware User’s Guide ® Figure 3: Physical Memory Map of the CL-PS7500FE Table 1 lists the peripheral chip selects and interrupt request lines to the CL-PS7500FE used by each external device. Table 1: Chip Select Usage... -
Page 11: Dram
Although standard FLASH SIMMs are available up to 32MBytes, this design does not support SIMMs larger than 16MBytes. The reason for this is that although the ROM space of the CL-PS7500FE has a maximum of 32MBytes, when booting from the on-board boot ROM, a FLASH burning utility may be loaded. In this event, the FLASH is re-mapped to the upper 16MBytes of the ROM space. -
Page 12: Boot Rom
The CL-PS7500FE supports different clocks for the memory CPU and I/O subsystems. The simplest means of clocking the CL-PS7500FE is to use the same clock for all three of the above inputs. In the case of the development board, the CPU clock is run from a Chrontel CH9294G clock generator chip whose frequency is determined by JP2, while the MEMORY clock runs from Y1 at 56MHz. -
Page 13: Power Management Modes
Power Management Modes The CL-PS7500FE supports three different modes of operation: Normal, Suspend, and Stop. The development board has only limited capability in this regard (the Normal mode is the only one fully supported). The key missing point is that the oscillators on the board cannot be stopped under software control. If the developer’s application requires this functionality, please contact Cirrus Logic regarding specific implementation... -
Page 14: Logic Analyzer Headers
This is an unfortunate problem with some LCDs. An active low pulse on either of the nEVENT pins or on the nPOR pin of the CL-PS7500FE will cause the processor to exit the Suspend or Stop mode. One difference between the Stop and Suspend modes is that the Suspend mode may be exited via an IRQ or a FIQ. -
Page 15: Table 12: Jp5 Logic Analyzer Header Definition
CL-PS7500FE Development Kit – Hardware User’s Guide ® Table 12: JP5 Logic Analyzer Header Definition Description Description VCC (+5V) VCC (+5V) D16 (main data bus bit) D15 (main data bus) D14 (main data bus) D13 (main data bus) D12 (main data bus) -
Page 16: Keyboard And Mouse
Ground Keyboard and Mouse The keyboard and mouse ports in the CL-PS7500FE are identical. Each is intended for connection to a PS/2 style mouse or keyboard. The mouse port consists of MSCLK (CL-PS7500FE pin 165) and MSDATA (CL-PS7500FE pin 167), which are brought out to J3. -
Page 17: Table 19: Ps2 Control Register Write Bit Mapping
CL-PS7500FE Development Kit – Hardware User’s Guide ® Table 19: PS2 Control Register Write Bit Mapping Name Table 20: PS2 Control Register Write Bit Definition Description Unspecified. Enable line. Set this pin high to enable the PS2 interface being used. Set low to disable. -
Page 18: Sound
4.8.1 Physical Details The sound system in the CL-PS7500FE consists of a serial interface intended for driving a 16-bit stereo DAC. In the case of the development board, the sound system pins are connected to a Crystal Semiconductor CS4333 16-bit stereo DAC. -
Page 19: Programming Details
DMA controller is reading data from another. All sound data must be written into a 4Kbyte page in the CL-PS7500FE’s memory. DMA data is transferred in blocks of four 32- bit words, or Qwords;... -
Page 20: Event Switches
Which buffer? This bit indicates 0 for buffer A, 1 for buffer B as the buffer currently being accessed by the DMA controller. For further details on the programming the sound system, please consult the CL-PS7500FE Advance Data Book V2.0, sections 9.3.3-4, 10.3.28, 10.3.51-56, 13, 14.1.7, 16.29-30, 21.1.1, and 22.8. -
Page 21: Cl-Ps7500Fe Memory Mapping
Whereas the ISA bus in a PC has I/O mapped registers at the bottom of the x86’s memory map, the ISA bus is mapped into a section of memory of the CL-PS7500FE. Although the organization of ISA address space was hinted at in Figure 3, further details on decoding are given here. -
Page 22: Smsc 37C665 Pc Combo Chip
Note that the programming of configuration registers as discussed here is not exhaustive. Developers who want to move devices around in the CL-PS7500FE’s address space, or enable/disable different devices should consult the 37C665 specification. -
Page 23: Serial Port #1 (Com1)
4.11.1 Serial Port #1 (COM1) COM1 is a standard 16C550A-compatible UART. The maximum data rate of this port is 115,200 baud. Port registers are addressed in the CL-PS7500FE’s memory at the following locations: Table 38: COM1 Address Registers Name Location... -
Page 24: Serial Port #2 (Com2)
4.11.2 Serial Port #2 (COM2) COM2 is also a standard 16C550A-compatible UART. The maximum data rate of this port is 115,200 baud. Port registers are addressed in the CL-PS7500FE’s memory at the following locations: Table 39: COM2 Address Registers Name... -
Page 25: Parallel Port (Lpt)
0x0301:09FC Parallel EPP mode data port 3 In addition to the above registers, the LPT port uses interrupt request 2 on the CL-PS7500FE. This port is capable of supporting normal, ECP, EPP and PS2 type operation. 4.12 CS8900A Ethernet (10BASE-T) The Ethernet controller on the development board is a Cirrus Logic CS8900A 10BASE-T controller. -
Page 26: Memory Mapped Interface
When an event requiring interrupt service occurs, the CS8900A will assert the appropriate interrupt to the CL- PS7500FE and place a 16-bit value in the ISQ register. The CL-PS7500FE is then able to read this value and perform the appropriate action. This register is similar to a FIFO in that the CS8900A may write several interrupt events to this queue. -
Page 27: Local Eeprom
DRQ0 from the CS8900A is the only channel connected to the CL-PS7500FE. The DMA channel is only used for receiving data. Since the CL-PS7500FE does not possess an external set of DMA request/acknowledge lines, the DMA request line is connected to INT5. To acknowledge requests, a write or read must be performed to 0x0301:2000. -
Page 28: Table 43: Eeprom Data For Default Ethernet Operation
CL-PS7500FE Development Kit – Hardware User’s Guide ® Figure 5: CS8900A Serial EEPROM Configuration Sequence Following the above flow chart, and noting that the “issue write command” step involves setting the address in the EEPROM being written to, write the following sequence to the EEPROM:... -
Page 29: Video Subsystem
4.13 Video Subsystem The video subsystem on the development board is partly built into the CL-PS7500FE and partly made up of external components. The following sections detail each of the operating modes of the video interface. Since there are so many different interfaces, each of which can be connected to different devices, this text is not to be considered exhaustive. -
Page 30: Vga
4.13.2 The CL-PS7500FE has the ability to directly drive a VGA monitor. The controller supports multiple resolutions and display formats. A standard video set-up of a 640x480, 256-color display is presented here. In order to keep the discussion simple the color scheme presented will be a simple grey scale. -
Page 31: Configuring The Palette
(0x8400:nnnn = 0x8400:02E2) Horizontal border end (0x8500:nnnn = 0x8500:02E8) Horizontal cursor start (0x8600:nnnn = 0x8600:004F) The details of how each of calculating each of these values can be found in the CL-PS7500FE Advance Data Book, Chapter 16. Version 1.0 March 1999... -
Page 32: Video Dma Configuration
Video DMA Configuration Video data to be displayed on the screen is normally stored in a section of the CL-PS7500FE’s memory. The DMA controller in the CL-PS7500FE must be configured to point to the location of the display information in memory and how many pixels worth of information are to be maintained in the video macrocell FIFO. -
Page 33: Vidmux Register
640/4 or 160, or 0xA0. In keeping with the conventions used in this section, set (0x3400:0000 = 0x0000:00A0). One final point about configuring the DMA controller. The CL-PS7500FE contains an MMU which will most likely be turned on by the developer (it is extremely useful). When programming the locations of the frame buffer into the DMA controller, use physical addresses for the locations. -
Page 34: Local 5V Switching Regulator
CL-PS7500FE Development Kit – Hardware User’s Guide ® 4.15.1 Local 5V Switching Regulator The local regulator for producing +5V is a switching type configured for operation in a “Buck” topology that operates at ~500kHz by default. The device is capable of producing up to 4.5A of current at +5V. This is unlikely, as the wall mounted transformer will only source 1.5A at 12V unregulated. -
Page 35: Optional Pc/At Power Supply Connection
CL-PS7500FE Development Kit – Hardware User’s Guide ® 4.15.5 Optional PC/AT Power Supply Connection If an AT supply is used to power the development board, three power connections are required. A standard supply will have all required connectors. The first is J24, which is a floppy drive power supply connector (4 pins on 0.200” centers). This connector supplies +12V and +5V. -
Page 36: Operating And Storage Environments
CL-PS7500FE development board will function reliably in an ambient operating temperature of 0-70°C, inclusive. Humidity The CL-PS7500FE development board is reliable in storage and operating in relative humidity of 10% to 95% (non- condensing) in the appropriate temperature ranges specified above. -
Page 37: Sources Of Additional Information
CL-PS7500FE Development Kit – Hardware User’s Guide ® 7 Sources of Additional Information Web page addresses for suppliers of parts used on the development board: http://www.mmm.com/interconnects/ Advanced Micro Devices http://www.amd.com/ Advanced RISC Machines http://www.arm.com/ http://connect.amp.com/ Coiltronics http://www.coiltronics.com/ Chrontel http://www.chrontel.com/ Cirrus Logic, Inc http://www.cirrus.com/... - Page 38 (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent...
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