1. Manuals
  2. Brands
  3. Cirrus Logic Manuals
  4. Microcontrollers
  5. CDB43131-GBK
  6. Manual

Cirrus Logic CDB43131-GBK Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Features
• Configurable serial audio headers for PCM, DSD and DoP audio
• Headphone and line outputs
• Analog and S/PDIF audio input
• USB audio module capability
• WISCE™ I
2
C-based software control
• Windows® compatible
Description
The CDB43131-GBK is a dedicated platform for testing and evaluating the CS43131. The CS43131 is a high-performance
audio DAC with integrated impedance detection and headphone drivers. To allow comprehensive testing and evaluation
of the performance of the CS43131, extensive software-configurable options are available through the CDB43131
evaluation kit. The kit also included the CDB-HDR-MEAS, for measuring the 130 dB dynamic range performance of the
CS43131.
Software options, such as register settings for the CS43131, are configured via the WISCE software tool, which
communicates with the CDB43131-GBK via an Aardvark I
cable.
http://www.cirrus.com
CDB43131-GBK Kit Manual
2
C/SPI host adapter from a Windows computer, or via Mini-USB
Figure 1 CDB43131 Board Block Diagram
Copyright © 2018 Cirrus Logic, Inc. and
Cirrus Logic International Semiconductor Ltd.
All rights reserved.
CDB43131-GBK
DS1155V2DB1
JUL '18

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the CDB43131-GBK and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Cirrus Logic CDB43131-GBK

Summary of Contents for Cirrus Logic CDB43131-GBK

  • Page 1 • Windows® compatible Description The CDB43131-GBK is a dedicated platform for testing and evaluating the CS43131. The CS43131 is a high-performance audio DAC with integrated impedance detection and headphone drivers. To allow comprehensive testing and evaluation of the performance of the CS43131, extensive software-configurable options are available through the CDB43131 evaluation kit.

  • Page 2: Table Of Contents

    CDB43131-GBK Table of Contents CDB43131-GBK Kit Overview ............................3 1.1 CDB43131 Board ................................3 1.2 CDB-HDR-MEAS Board ............................... 3 CDB43131 Board Overview ............................4 2.1 Power Supply Circuitry ..............................5 2.2 Digital Audio Input ................................. 6 2.3 Analog Audio Input ............................... 9 2.4 Analog Audio Output ..............................

  • Page 3: Cdb43131-Gbk Kit Overview

    CDB43131-GBK 1 CDB43131-GBK Kit Overview The CDB43131-GBK kit consists of an evaluation board, a high dynamic range (HDR) measurement board, and a USB cable. Each of these component boards is described in the following sections. 1.1 CDB43131 Board The CDB43131 is shown in the following figure.

  • Page 4: Cdb43131 Board Overview

    CDB43131-GBK 2 CDB43131 Board Overview The CDB43131 is the board for evaluating the performance of the CS43131. It supports multiple power supplies and signal I/O configurations. The CDB43131 board uses five buffers with direction control to direct clock from the digital input sources to/from the CS43131 DUTs.

  • Page 5: Power Supply Circuitry

    CDB43131-GBK 2.1 Power Supply Circuitry The CDB43131 board is powered from a 5-volt, 1.2-amp AC adapter or via the +5-volt bus from the USB connector. All the supply rails for both the smart codec and the CS43131s are generated using a combination of switched-mode power supplies (switchers) and LDOs.

  • Page 6: Digital Audio Input

    CDB43131-GBK 2.2 Digital Audio Input 2.2.1 Serial Audio I/O Headers Headers J25 and J26, labeled ASP and XSP respectively, provide an interface for serial audio clocks and data. The source of the clocks and data can be an external audio source such as an Audio Precision audio analyzer. The header signals are described in the table below.
  • Page 7 CDB43131-GBK To source the signals from the output of the buffers to the DAC, place jumpers between the two columns of pins labeled BRD and DUT. For example, in order to send SCLK1, LRCLK1 and SDIN1 signals from the buffer to the DAC, place jumpers between pins of the BRD and DUT group as shown in the following figure.
  • Page 8 CDB43131-GBK To source the signals from external audio source like an Audio Precision APx555, connect the cable that fits onto a 2-pin header onto the pins labeled DUT and GND. For example, in order to send SCLK1, LRCLK1 and SDIN1 signals from an...

  • Page 9: Analog Audio Input

    CDB43131-GBK 2.3 Analog Audio Input The CDB43131 features a 1/8" headphone jack for each the CSP (J16) and QFN (J34). Situated next to each headphone jack are a pair of testpoints (J18/J19 and J35/J36, respectively) for connecting to an APx.

  • Page 10: Analog Audio Output

    CDB43131-GBK 2.4 Analog Audio Output The CDB43131 board has one 1/8" stereo headphone output jack (J1) for the CSP and one XLR cable output jack (J60) for the QFN. Figure 10 1/8" Headphone Jack/APx Connectors/Loading Jumpers for CSP Figure 11 XLR Output/APx Connectors/Loading Jumpers for QFN 2.5 I...

  • Page 11: Leds

    CDB43131-GBK 2.6 LEDs The status LEDs on the CDB43131 board show the status of the power rails and S/PDIF input. A summary of the LEDs is shown in the table below. Table 5 Status LEDs LED Function LED Reference LED Color...

  • Page 12: List Of Headers And Jumper Settings

    CDB43131-GBK 2.7 List of Headers and Jumper Settings The following table lists all the available headers, jacks, and plugs on CDB43131 board. Table 6 Header and Jumper Settings Reference Connection Type Description Designator CSP-HPOUT 3.5-mm The headphone out jack for the CS43131 CSP device headphone jack —...
  • Page 13 CDB43131-GBK Reference Connection Type Description Designator Test Point QFN-HPINA 2x1 header 2-pin test point for Audio Precision Test Point — VP Source 3x1 header Jumper between 1-2 to get VP from VP banana jack (J13). Jumper between Select 2-3 to get VP from 3.6-V LDO —...

  • Page 14: Codec Mclk Selection

    CDB43131-GBK 2.7.1 Current Measurement Headers The table below shows a list of current measurement headers and the associated rails. To measure current of a particular voltage rail, remove the jumper and place a current probe across the pins of the header.

  • Page 15: Board Control Register Quick Reference

    CDB43131-GBK 3 Board Control Register Quick Reference Figure 14 CDB43131 IO EXP Registers 3.1 Register Descriptions 3.1.1 Output Port 0 Address: 0x04 Default: 0xFC Position Bitfield XTI_OSC_24p5 XTI_OSC_22p5792 XTI_CLKOU XTI_CLKOUT_CS RESER RESET_S RESER RESER Name 76MHZ_EN MHZ_EN T_EN P/QFN PDIF...
  • Page 16 CDB43131-GBK 3.1.2 Output Port 2 Address: 0x05 Default: 0x0F Position Bitfield XSP_DSD/ ASP_PCM/SP XSP_M ASP_M MCLK2_HDR_ MCLK1_HDR_ XTI_MCLK2_BR XTI_MCLK1_BR Name SPDIF D_EN D_EN Default Value Bits Name Description XSP_DSD/SPDIF Set Codec in DSD/SPDIF Mode 0 DSD 1 SPDIF (Default) ASP_PCM/SPDIF...
  • Page 17 CDB43131-GBK 3.1.3 Output Port 3 Address: 0x06 Default: 0xFF Bit Position Bitfield Name Reserved MCLK_QFN_OE MCLK_CSP_OE Default Value Bits Name Description — Reserved MCLK_QFN_OE Set Codec as Master to CSP 1 Master (Default) 0 Slave MCLK_CSP_OE Set Codec as Master to QFN...
  • Page 18 CDB43131-GBK 3.1.5 Port Config 2 Address: 0x0D Default: 0x00 Position Bitfield XSP_DSD ASP_DSD/SP XSP_M/ ASM_M/ MCLK2_HDR_ MCLK1_HDR_ XTI_MCLK2_BR XTI_MCLK1_BR Name /SPDIF_D DIF_DIR S_DIR S_DIR M/S_DIR M/S_DIR D_EN_DIR D_EN_DIR Default Value Bits Name Description XSP_DSD/SPDIF_DIR Direction of the XSP_DSD/SPDIF signal 0 Output (Default)

  • Page 19: Cdb-Hdr-Meas High Dynamic Range Measurement Preamplifier

    CDB43131-GBK 4 CDB-HDR-MEAS High Dynamic Range Measurement Preamplifier The CDB-HDR-MEAS is an ultralow-noise preamplifier circuit with +13.66 dB of gain. The CDB-HDR-MEAS is designed to be used as a preamplifier to a high-performance audio analyzer to allow measurement of the high dynamic range (DNR) of the CS43131.

  • Page 20: How The Cdb-Hdr-Meas Works

    CDB43131-GBK 4.2 How the CDB-HDR-MEAS Works Since the noise floor of the APx555 is around –124 dB, and the CS43131 has a DNR of 130 dB, the signal needs to be amplified to make it measurable. The following image illustrates this issue. In an ideal situation, the –60 dB signal during DNR tests would yield a total dynamic range of 130 dB.

  • Page 21: Testing The Cs43131 Using Wisce Software

    The WISCE™ software interactive setup and configuration environment is an interactive tool for setting up and configuring Cirrus Logic devices and software. The following sections show how to use WISCE software to configure and test CS43131 and using the CDB43131 board and the CDB43131 Board.

  • Page 22: Loading The Cdb43131 Board Panel And Register Map

    CDB43131-GBK The WISCE software is configured, by default, to scan the I C bus and report the presence of any devices attached to this bus. When the WISCE software is launched, it will report the presence of four unknown devices, one each at address 0x22, 0x44, 0x60 and 0x62 respectively.
  • Page 23 CDB43131-GBK Click "Accept" to load the CDB43131 board Panel and Register Map shown in the following figures. Figure 21 TCA6424 Panel Figure 22 TCA6424 Register Map DS1155V2DB1...

  • Page 24: Loading The Cs43131 Plugins And Register Map

    CDB43131-GBK 5.3 Loading the CS43131 Plugins and Register Map To load the CS43131 Plugin and Register Map, launch the "Change Device" pop-up window by either double clicking on Unknown Device or right clicking on Unknown Device at address 0x60 and selecting Properties. Select "CS43131 Rev A1"...
  • Page 25 CDB43131-GBK To view CS43131 plugin, click on Tuning and select "CS43131_Plugin." Figure 26 CS43131 Plugin DS1155V2DB1...

  • Page 26: Initializing The Devices On The Cdb43131 Board

    CDB43131-GBK 5.4 Initializing the Devices on the CDB43131 Board The following steps show how to detect the presence of the CS43131s on the CDB43131 Board. 1. Under the CDB431XX_I2C_GPIP_EXP menu, click on QUICK_START, and click CDB_INIT.txt. This will reset the board into a default mode.

  • Page 27: Cs43131 Plugin

    CDB43131-GBK 5.5 CS43131 Plugin The CS43131 plugin has multiple tabs. Each tab provides an interface to configure and control specific IP Block(s) in the CS43131. The following sections describe each tab and its function. The user can configure the CS43131 using these tabs.
  • Page 28 CDB43131-GBK 5.5.2 Sys_Config Tab This tab allows user to configure the CS43131 clock input settings. It also allows the user to configure CLKOUT and Class-H amplifier settings. Figure 29 Sys_Config Tab DS1155V2DB1...
  • Page 29 CDB43131-GBK The example below shows the sequence of steps that should be followed to select On-board Crystal as MCLK source using the Sys_Config tab. 1. XTAL bias is set by default to 12.5 µA. 2. Click on the Enable XTAL Interrupts check box to enable crystal interrupts.
  • Page 30 CDB43131-GBK 5.5.3 PLL Tab This tab allows the user to configure the CS43131 PLL. The PLL can be used as an alternate source for the CS43131 MCLK. Figure 31 PLL Tab DS1155V2DB1...
  • Page 31 CDB43131-GBK 5.5.4 Headphone Tab This tab allows the user to perform the following functions: 1. Enable/disable headphone output 2. Enable analog passthrough 3. Enable headphone presence detection 4. Initiate headphone impedance measurement Figure 32 Headphone Tab 5.5.4.1 Enabling Headphone Output The following steps show how to enable the headphone output using the Headphone tab.
  • Page 32 CDB43131-GBK 5.5.4.2 Disabling Headphone Output The following steps show how to disable the headphone output using the Headphone tab. 1. If the CS43131 just came out of reset, the headphone output is already disabled, so the remaining steps can be skipped.
  • Page 33 CDB43131-GBK 5.5.4.5 Headphone Impedance Measurement The plugin supports both DC and AC impedance measurement. For AC impedance measurement, it supports both measurement at one frequency or measurement across entire audio band. Any jumpers on headers J28 and J29 should be removed before starting impedance measurement.
  • Page 34 CDB43131-GBK 5.5.4.5.2 Measuring AC Impedance The following steps show how to measure AC Impedance. A headphone should be connected to headphone jack J1 on the CDB43131 board to do the measurement. DC impedance should be measured before measuring AC Impedance.
  • Page 35 CDB43131-GBK 5.5.4.5.3 Measuring AC Impedance Across a Range of Frequencies The following steps show how to measure AC impedance across a range of frequencies. A headphone should be connected to headphone jack J1 on the CDB43131 to do the measurement. DC impedance should be measured before measuring AC impedance.
  • Page 36 CDB43131-GBK 5.5.5 ASP Config Tab This tab allows the user to configure the ASP port. The following figure shows ASP Config tab contents when ASP is configured to operate in Slave mode. Figure 36 ASP Config Tab DS1155V2DB1...
  • Page 37 CDB43131-GBK The following figure shows the contents of ASP Config tab when ASP is configured to operate in Master mode. Figure 37 ASP Config Tab in Master Mode DS1155V2DB1...
  • Page 38 CDB43131-GBK Click the Calculate button to determine the frequencies of the SCLK and LRCLK signals. When this button is clicked, the SCLK and LRCLK values will be calculated based on the selected frequency of Internal MCLK (MCLK_INT) and the values in ASP Numerator, ASP Denominator, LRCLK high Time and LRCLK Period text boxes. The value in the LRCLK Frequency text box will be used to set the new sample rate (if it is not already set by user) when the ASP is powered up.
  • Page 39 CDB43131-GBK 5.5.6 XSP Config Tab This tab allows the user to configure the XSP port. The following figure shows XSP Config tab contents when XSP is configured to operate in Slave mode. Figure 39 XSP Config Tab in Slave Mode...
  • Page 40 CDB43131-GBK The following figure shows the contents of XSP Config tab when XSP is configured to operate in Master mode. Figure 40 XSP Config Tab in Master mode DS1155V2DB1...
  • Page 41 CDB43131-GBK Click the Calculate button to determine the frequencies of the SCLK and LRCLK signals. When this button is clicked, the SCLK and LRCLK values will be calculated based on the selected frequency of Internal MCLK (MCLK_INT) and the values in XSP Numerator, XSP Denominator, LRCLK high Time and LRCLK Period text boxes. The value in the LRCLK Frequency text box will be used to set the new sample rate (if it is not already set by user) when the XSP is powered up.
  • Page 42 CDB43131-GBK 5.5.7 PCM Playback Tab This tab allows the user to configure PCM playback path. This tab allows the user to change PCM filter dynamically during playback. The impulse and magnitude responses of the selected filter are displayed. It is recommended to use a profile script to configure this part since each field will be preconfigured correctly for the proper mode.
  • Page 43 CDB43131-GBK 5.5.8 DSD Playback Tab This tab allows the user to configure the DSD/DoP playback path. It is recommended to use a profile script to configure this port. Figure 43 DSD Playback Tab DS1155V2DB1...

  • Page 44: Testing Various Use Cases

    CDB43131-GBK 6 Testing Various Use cases Profile scripts are provided along with the plugin to allow the user to test various common use cases. The profile scripts for CS43131 can be found in {WISCE_INSTALL_FOLDER}/Profiles/CS43131. If needed, users can create their own profile scripts to suit their requirements.

  • Page 45: Data Flow For Various Use Cases

    CDB43131-GBK 6.1 Data Flow for Various Use Cases The following sections depict the flow of data, in red, for various common use cases. 6.1.1 PCM Playback Figure 44 PCM Playback Data Flow DS1155V2DB1...
  • Page 46 CDB43131-GBK 6.1.2 DSD Playback Figure 45 DSD Playback Data Flow DS1155V2DB1...
  • Page 47 CDB43131-GBK 6.1.3 Analog Audio Playback Figure 46 Analog Audio Playback Data Flow DS1155V2DB1...

  • Page 48: Measuring Dynamic Range And Thd+N For The Cs43131

    CDB43131-GBK 6.2 Measuring Dynamic Range and THD+N for the CS43131 This section describes the test setup and the procedure to measure dynamic range and THD+N for CS43131. 6.2.1 Test Program Setup The following steps show how to setup the CDB43131 for THD+N measurement. Please make sure that the CDB4131 jumpers are set to factory default mode.
  • Page 49 CDB43131-GBK 6.2.2 APx Setup The following steps show how to configure the APx for running the tests. This procedure was tested using an APx555. 1. Run the APx software. (APx500 v4.2 if using an APx555) 2. Set the APx Output to Digital Serial and Input to Analog Balanced.
  • Page 50 CDB43131-GBK 4. In the Signal Path Setup panel, click on the settings button next to Connector drop-down menu and configure Digital Serial Settings as shown below. Figure 49 Digital Serial Settings DS1155V2DB1...
  • Page 51 CDB43131-GBK 5. To launch the Dynamic Range Measurement test, click on Project-> Add Measurement -> Meters -> Dynamic Range - AES17. This will launch the dynamic range test screen. Figure 50 Launch Dynamic Range Test DS1155V2DB1...
  • Page 52 CDB43131-GBK 6. To run the Dynamic Range Measurement test, configure the Input Level and Bandwidth as shown below. Click on the "Start" button to run the test. Dynamic Range values will be displayed for both channels. Figure 51 Dynamic Range Test...
  • Page 53 CDB43131-GBK 7. To launch THD+N test, click on Project-> Add Measurement -> Meters ->THD+N to launch THD+N measurement window. Figure 52 Launch THD+N Test DS1155V2DB1...
  • Page 54 CDB43131-GBK 8. To run THD+N test, configure the Input Level and Bandwidth as shown below. Click on the "Generator" button to run the test. THD+N ratio will be displayed for both channels. THD+N ratio is typically displayed in Percentage (%).
  • Page 55 CDB43131-GBK 6.2.3 Measuring Dynamic Range for the CS43131 To measure dynamic range in the WISCE software, click File->Load and select XTAL_In_ASP_Slave_PCM_Playback_48K_1v7.txt file from {WISCE_INSTALL_FOLDER}/profiles/CS43131 to configure CS43131 for audio playback in Slave Mode. Note that this method only works when measuring the CSP device. The QFN device (with mono output) does not interface easily with the CDB-HDR-MEAS board.
  • Page 56 CDB43131-GBK 6.2.4 Measuring THD+N for the CS43131 To measure THD+N in the WISCE software, click File->Load and select XTAL_In_ASP_Slave_PCM_Playback_48K_1v7.txt file from {WISCE_INSTALL_FOLDER}/profiles/CS43131 to configure CS43131 for audio playback in Slave Mode. 6.2.4.1 Measuring THD+N on CSP Device The following steps show the procedure to measure THD+N.
  • Page 57 CDB43131-GBK 6.2.4.2 Measuring THD+N on QFN Device The following steps show the procedure to measure THD+N. 1. Place a jumper connecting the 600-Ω load on J17. 2. Place a jumper connecting the 600-Ω load on J31. 3. Connect a XLR cable between QFN-OUT(J60) and the Balanced XLR port on Analog input 1 on the APx.

  • Page 58: Measured Results

    CDB43131-GBK 6.3 Measured Results This section shows some measured dynamic range and THD+N results from the CDB43131 kit. 6.3.1 Test Waveforms All test waveforms were generated using the APx Waveform Generator Utility that can be found on the Audio Precision website.

  • Page 59: Revision History

    CDB43131-GBK 7 Revision History Revision Changes • Initial release JUL '18 DS1155V2DB1...
  • Page 60 IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic, and you may not use this document in connection with any legal analysis concerning Cirrus Logic products described herein. No license to any technology or intellectual property right of Cirrus Logic or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property rights.

Table of Contents