Board Control Register Quick Reference; Register Descriptions - Cirrus Logic CDB43131-GBK Manual

3 Board Control Register Quick Reference

3.1 Register Descriptions

3.1.1 Output Port 0
Bit 7
Position
Bitfield XTI_OSC_24p5
Name 76MHZ_EN
Default 1
Value
Bits
7
6
5
4
3
2
1:0
DS1155V2DB1
Figure 14 CDB43131 IO EXP Registers
Address: 0x04
6
XTI_OSC_22p5792 XTI_CLKOU
MHZ_EN
1
Name
XTI_OSC_24p576MHZ_EN
XTI_OSC_22p5792MHZ_EN
XTI_CLKOUT_EN
XTI_CLKOUT_CSP/QFN
Reserved
Reset_SPDIF
Reserved
Default: 0xFC R/W
5 4
XTI_CLKOUT_CS
T_EN P/QFN
1 1
Description
Enable 24.576 MHz CLK to be used as input to CODEC
0 Enabled
1 Disabled (Default)
Enable 22.5792 MHz CLK to be used as input to CODEC
0 Enabled
1 Disabled (Default)
Select SPDIF Clock Master
0 External CLK
1 CS43131 CLKOUT (Default)
Select Device to be SPDIF Clock Master
0 CSP CLKOUT
1 QFN CLKOUT (Default)
—
Enable SPDIF Buffer
0 Disabled
1 Enabled (Default)
—
CDB43131-GBK
3 2
RESER RESET_S RESER
VED PDIF VED
X 1
1 0
RESER
VED
X X
15