Timer 4 Current Count Register (Tmrccr4); Timer 1 Irq Clear (T1Ic); Timer 2 Irq Clear (T2Ic); Timer 3 Irq Clear (T3Ic) - GE VMIVME-7805 Hardware Reference Manual

the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.

3.4.9 Timer 4 Current Count Register (TMRCCR4)

The current count of Timer 4 may be read via the Timer 4 Current Count Register
(TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits
in this register are as follows:
Field
Timer 4 Count
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.

3.4.10 Timer 1 IRQ Clear (T1IC)

The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by
Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2,
causes the interrupt from Timer 1 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (CSR1). This register is write only and the data written is irrelevant.

3.4.11 Timer 2 IRQ Clear (T2IC)

The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by
Timer 2. Writing to this register, located at offset 0x34 from the address in BAR2,
causes the interrupt from Timer 2 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (CSR1). This register is write only and the data written is irrelevant.

3.4.12 Timer 3 IRQ Clear (T3IC)

The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by
Timer 3. Writing to this register, located at offset 0x38 from the address in BAR2,
causes the interrupt from Timer 3 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (CSR1). This register is write only and the data written is irrelevant.

3.4.13 Timer 4 IRQ Clear (T4IC)

The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by
Timer 4. Writing to this register, located at offset 0x3C from the address in BAR2,
causes the interrupt from Timer 4 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (CSR1). This register is write only and the data written is irrelevant.
Bits Read or Write
TMRCCR4[31..0] Read Only
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