Nvram; Vme Control; Table 3-3 Register Definitions Offset From Bar0 - GE VMIVME-7805 Hardware Reference Manual

3.6 NVRAM

3.7 VME Control

The VMIVME-7805/VME-7805RC provide 32 KByte of nonvolatile SRAM. This
memory is mapped in 32k of address space starting at the address in BAR1. This
memory is available at any time and supports byte, short word and long word
accesses from the PCI bus. The contents of this memory is retained when the
power to the board is removed.
The following table shows the register definitions for the VMIVME-7805/
VME-7805RC (offset from BAR0).

Table 3-3 Register Definitions Offset From BAR0

Register Name
VMECOMM
Bit Name
MEC_SEL
SEC_SEL
ABLE
BTO
BTOV [1:0]
BERRI
BERRST
SFENA
Unused
BPENA
VBENA
Unused
VBAR
VME_ADDR
VBAM
VME_ADDR
Unused
SEC_SEL
Please refer to Table 3-2, PCI Configuration Space Registers, on page 41 for more
information concerning BAR0.
Offset
0x00
Bit Definition
0 Master big-endian enable bit 1=Big Endian 0=Little
Endian bit
1 Slave Big-Endian enable bit 1=Big Endian 0=Little Endian
2 Auxiliary BERR logic enable bit
1=Aux. BERR enabled 0=Aux. BERR disabled
3 Bus error timer enabled 1=enabled 0=disabled
5:4 Timeout value
00 - 16 µs
01 - 64 µs
10 -256 µs
11 - 1.00 ms
6 BERR interrupt enable 1=Interrupt enabled 0=Interrupt
disabled
7 BERR status read/clear bit
1=Clear BERR status 0=Do nothing
8 Enables generation of VME SYSFAIL upon WDT timeout
1= Enable SYSFAIL generation 0=Disable
9 Not Used
10 Endian conversion bypass bit
1 = bypass 0 = not bypassed
11 VME enable bit
1 = enabled 0 = disabled
31:12 Not Used
0x08
All Latched VME Address
0x04
5:0 Latched VME Address Modifier
31:6 Not Used
0x001
Embedded PC/RTOS Features 47