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LPC Connector
LPC
The Low Pin Count Interface was defined by Intel
sition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O com-
ponents within the system, which are typically provided by a Super I/O controller. Furthermore,
it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin fuctions of the LPC connector.
Pin
Function
CLK
1
RST#
3
FRAME#
5
LAD3
7
LAD2
9
SERIRQ
11
5VSB
13
Chapter 2 Hardware Installation
Chapter 2
14 13
2 1
Corporation to facilitate the industry's tran-
®
Pin
Function
LAD1
2
LAD0
4
3V3
6
GND
8
10
---
12
GND
5V
14
SMBus Connector
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
27
SMBus
5
1
2
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