E
S
LECTRICAL
PECIFICATION
I/O Access Write Timing
A[10::0]
____
REG
CE
_____
IOWR
______
IOIS16
D[15::0]
Symbol
t
IGHDX
t
IGHQX
t
IGLIGH
t
AVIGL
t
AXIGH
t
CLIGL
t
CHIGH
t
RLIGL
t
RHIGH
t
AVISL
t
AXISH
Note: (1) IOIS16 and INPACK are not supported.
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
3600D-04DSR
t
RLIGL
t
CLIGL
__
t
AVIGL
t
AVISL
Figure 5: I/O Access Write Timing Diagram
Table 13: I/O Access Write Timing
Parameter
Data Hold following IOWR
Data Setup before IOWR
IOWR Pulse Width
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
CE Hold following IOWR
REG Setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
S
S
ILICON
YSTEMS
All unauthorized use and/or reproduction is prohibited.
SSD-D
t
IGLIGH
t
IGHQX
Minimum
5
20
65
25
10
5
10
5
0
-
-
P
ROPRIETARY
P
12
AGE
(I)-3600 D
XXX
ATA
t
AXIGH
t
RHIGH
t
CHIGH
t
AXISH
t
IGHDX
Maximum
-
-
-
-
-
-
-
-
-
(1)
(1)
F
EBRUARY
S
HEET
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 2009
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