Maxim Integrated MAX32650 User Manual

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MAX32650–MAX32652 USER GUIDE

UG6766; Rev 0; 9/18

Abstract:

This user guide provides application developers information on how to use the memory and

peripherals of the MAX32650–MAX32652 microcontroller. Detailed information for all registers and fields in

the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the

device family.

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Summary of Contents for Maxim Integrated MAX32650

Page 1 This user guide provides application developers information on how to use the memory and peripherals of the MAX32650–MAX32652 microcontroller. Detailed information for all registers and fields in the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the...
Page 2: Table Of Contents
MAX32650–MAX32652 User Guide MAX32650–MAX32652 User Guide Table of Contents Overview ..........................23 Block Diagram ............................24 Memory, Register Mapping, and Access ................26 Memory, Register Mapping, and Access Overview ................26 Standard Memory Regions........................28 Code Space ................................. 28 SRAM Space ............................... 29 Peripheral Space ..............................
Page 3 MAX32650–MAX32652 User Guide 32.768kHz External Crystal Oscillator ........................ 38 8kHz Ultra-Low Power Nano-Ring Internal Oscillator ..................38 System Oscillators Reset ........................39 Power Management..........................40 Operating Modes ........................... 40 ACTIVE Mode ..............................40 SLEEP Low Power Mode ............................. 40 BACKGROUND Low Power Mode ........................42 DEEPSLEEP Low Power Mode ..........................
Page 4 MAX32650–MAX32652 User Guide Interrupts and Exceptions ...................... 84 Features ..............................84 Interrupt Vector Table ........................... 84 General-Purpose I/O and Alternate Function Pins ..............87 Features ..............................87 General Description ..........................87 GPIO ............................... 99 Input mode configuration ..........................99 Output Mode Configuration ..........................99 Alternate Function Configuration ........................
Page 5 MAX32650–MAX32652 User Guide SPIXR Register Details ............................147 External Memory Cache Controller (EMCC) ..................157 Features ................................157 Enabling the EMCC ............................157 Disabling the EMCC ............................157 EMCC Registers ..............................157 EMCC Register Details ............................158 Secure Digital Host Controller ......................160 Overview ................................
Page 6 MAX32650–MAX32652 User Guide 8.11 Channel and Register Access Restrictions .................... 218 8.12 Memory-to-Memory DMA ........................218 8.13 Standard DMA Registers ........................218 8.14 Standard DMA Register Details ......................219 8.15 Standard DMA Channel Register Offsets ..................... 219 8.16 Standard DMA Channel Registers ......................220 8.17...
Page 7 MAX32650–MAX32652 User Guide 11.6 8-Bit Color STN Output Format ......................252 11.7 Panel/Pixel Clock Generation ....................... 253 11.8 LCD Panel Timing Generation ......................254 11.9 Interrupt Operation ..........................255 11.10 TFT Controller Registers ........................255 11.11 TFT Controller Register Details......................255 UART ..........................
Page 8 MAX32650–MAX32652 User Guide 13.13 C TX FIFO and RX FIFO Management ....................279 13.14 Interactive Receive Mode ........................279 13.15 C DMA Control ........................... 280 13.16 C Master Mode Transmit Operation ....................280 13.17 C Master Mode Transmit Bus Arbitration..................281 13.18...
Page 9 MAX32650–MAX32652 User Guide Counter Mode Timer Period ..........................322 Counter Mode Configuration ........................... 323 15.7 PWM Mode (011b) ..........................324 PWM Mode Timer Period ..........................324 PWM Mode Configuration ..........................324 15.8 Capture Mode (100b) ........................... 326 Capture Mode Timer Period ..........................326 Capture Mode Configuration ...........................
Page 10 MAX32650–MAX32652 User Guide Pin Configuration ............................. 343 I/O ..................................343 Pullup Enable ..............................343 17.3 Clock Configuration ..........................343 17.4 1-Wire Protocol ............................ 343 Networking Layers ............................344 Bus Interface (Physical Layer) .......................... 344 Reset, Presence Detect, and Data Transfer (Link Layer) .................. 344 17.5...
Page 11 MAX32650–MAX32652 User Guide Bulk IN Endpoints ............................. 361 Bulk OUT Endpoints ............................362 18.8 Interrupt Endpoints ..........................362 Interrupt IN Endpoints ............................. 362 Interrupt OUT Endpoints ..........................362 18.9 Isochronous Endpoints ......................... 363 Isochronous IN Endpoints ..........................363 Isochronous OUT Endpoints..........................363 18.10...
Page 12 MAX32650–MAX32652 User Guide Mono ................................402 Left Justify ................................ 403 20.5 Error Detection ............................. 403 Transmit Overrun ............................. 403 Mode Fault (Multi-Master Collision) ........................ 404 Slave Mode Abort ............................404 Receive Overrun ............................... 404 20.6 SPIMSS Interrupts ..........................404 Data Interrupt ..............................404 Forced Interrupt ...............................
Page 13 MAX32650–MAX32652 User Guide List of Figures Figure 1-1: MAX32650–MAX32652 Block Diagram ....................24 Figure 2-1: MAX32650–MAX32652 Code Memory Mapping .................. 27 Figure 2-2 Code Memory Mapping ......................... 28 Figure 3-1: Clock Block Diagram ..........................39 Figure 3-2: SLEEP Mode Clock Control ........................41 Figure 3-3: BACKGROUND Mode Clock Control ......................
Page 14 MAX32650–MAX32652 User Guide Figure 19-8: SPI Mode 3, Four-Wire Communication ................... 389 Figure 19-9: SPI Mode 3, Three-Wire Communication ..................389 Figure 20-1. SPIMSS Block Diagram ........................399 Figure 20-2. SPI Single-Master, Single-Slave ......................400 Figure 20-3. SPI Multi-Master, Multi-Slave ......................400 Figure 20-4.
Page 15 Table 3-36: Low Power USB Wakeup Enable Register .................... 82 Table 3-37: Low Power RAM Power Control Register ..................... 82 Table 4-1: MAX32650 Interrupt Vector Table ......................84 Table 5-1: GPIO Port, Pin Name and Alternate Function Matrix, 140 WLP............. 89 Table 5-2: GPIO Port, Pin Name and Alternate Function Matrix, 144 TQFP ............
Page 16 MAX32650–MAX32652 User Guide Table 5-7: GPIO Registers ............................101 Table 5-8: GPIO Port 0 Enable Register ......................... 103 Table 5-9: GPIO Port 1 to Port 3 Enable Registers ....................104 Table 5-10: GPIO Port 0 to Port 3 Enable Atomic Set Registers ................104 Table 5-11: GPIO Port 0 to Port 3 Enable Atomic Clear Registers .................
Page 17 MAX32650–MAX32652 User Guide Table 7-3: Encrypted Data Write Order to SPIX Flash Memory ................129 Table 7-4. SPIXF Master Controller Register Offsets, Names, Access and Description ......... 129 Table 7-5. SPIXF Controller Configuration Register ....................129 Table 7-6. SPIXF Controller Slave Select Polarity Register ..................131 Table 7-7.
Page 18 MAX32650–MAX32652 User Guide Table 7-51: Summary of how register settings determine type of data transfer ..........170 Table 7-52: SDHC Command Register ........................170 Table 7-53: Relationship between Parameters and the Name of Response Type ..........171 Table 7-54: SDHC Response 0 Register ........................171 Table 7-55: SDHC Response 1 Register ........................
Page 19 MAX32650–MAX32652 User Guide Table 7-99: HBMC Interrupt Enable Control Register ................... 207 Table 7-100: HBMC Interrupt Status Flags Register ....................208 Table 7-101: HBMC CS0# Memory Base Address Register ..................208 Table 7-102: HBMC Memory Configuration 0 Registers ..................209 Table 7-103: HBMC Memory Timing Register 0 ....................
Page 20 MAX32650–MAX32652 User Guide Table 11-4: CLCD Data Format Little Endian Byte, Big Endian Pixel (LBBP)............252 Table 11-5 Palette RAM Data Format for CLCD_PALETTE_RAM[0:255] Registers ..........252 Table 11-6 STN Data Output Format per Clock Cycle .................... 253 Table 11-7 LCD Panel Signals ..........................253 Table 11-8 PCLK to PIXEL Clock Divide Ratios .......................
Page 21 MAX32650–MAX32652 User Guide Table 14-2: Pulse Train Engine Global Enable/Disable Register ................300 Table 14-3: Pulse Train Engine Resync Register ....................302 Table 14-4:Pulse Train Engine Stopped Interrupt Flag Register ................305 Table 14-5: Pulse Train Engine Interrupt Enable Register ..................307 Table 14-6: Pulse Train Engine Safe Enable Register .....................
Page 22 MAX32650–MAX32652 User Guide Table 18-18: USBHS IN Endpoint Maximum Packet Size Register ................. 374 Table 18-19: USBHS IN Endpoint Lower Control & Status Register ..............374 Table 18-20: USBHS Endpoint 0 Control Status Register..................375 Table 18-21: USBHS IN Endpoint Upper Control Register ..................376 Table 18-22: USBHS OUT Endpoint Maximum Packet Size Register ..............
Page 23: Overview
The MAX32651 is a secure version of the MAX32650–MAX32652. It provides a trust protection unit (TPU) with encryption and advanced security features. These features include a modular arithmetic accelerator (MAA) for fast ECDSA and RSA- 4096 computation.
Page 24: Block Diagram
MAX32650–MAX32652 User Guide Block Diagram Figure 1-1: MAX32650–MAX32652 Block Diagram The device features five flexible power modes. A smart DMA engine reduces power consumption by executing data collection tasks while the Arm Cortex-M4 with FPU core is powered off. Application-controlled power gating combined with built-in, dynamic clock gating optimizes power consumption.
Page 25 MAX32650–MAX32652 User Guide External memory is supported using multiple industry standard interfaces. A HyperBus SRAM interface operating at a double-data rate of 96 MB/second can access up to 1 GB. A Secure Digital High Capacity (SDHC) interface provides support for large file data storage.
Page 26: Memory, Register Mapping, And Access
MAX32650–MAX32652 User Guide Memory, Register Mapping, and Access Memory, Register Mapping, and Access Overview The Arm Cortex-M4 architecture defines a standard memory space for unified code and data access. This memory space is addressed in units of single bytes but is most typically accessed in 32-bit (4 byte) units. It may also be accessed, depending on the implementation, in 8-bit (1 byte) or 16-bit (2 byte) widths.
Page 27: Figure 2-1: Max32650-Max32652 Code Memory Mapping
MAX32650–MAX32652 User Guide Figure 2-1: MAX32650–MAX32652 Code Memory Mapping Maxim Integrated Page 27 of 411...
Page 28: Standard Memory Regions
MAX32650–MAX32652 User Guide Figure 2-2 Code Memory Mapping Standard Memory Regions Several standard memory regions are defined for the Arm Cortex-M4 architecture; the use of many of these is optional for the system integrator. At a minimum Arm Cortex-M4-based devices must contain code and data memory for the application storage, variables and stack use, as well as certain components which are part of the instantiated core.
Page 29: Sram Space
The SRAM area on the MAX32650–MAX32652 can be used to contain executable code. Code stored in the SRAM is accessed directly for execution (using the system bus) and is not cached. The SRAM is also where the Arm Cortex-M4 stack must be...
Page 30: Peripheral Space
The external device space area of memory is intended for use in mapping off-chip device control functions onto the AHB bus. This memory space is defined from byte address range 0xA000 0000 to 0xDFFF FFFF (1GB maximum). The MAX32650– MAX32652 does not implement this memory area.
Page 31: System Area (Private Peripheral Bus)
The system area (vendor defined) memory space is reserved for vendor (system integrator) specific functions that are not handled by another memory area. It is defined from byte address range 0xE010 0000 to 0xFFFF FFFF. The MAX32650– MAX32652 does not implement this memory region.
Page 32: System Sram
TPU Memory The MAX32650–MAX32652 contains a specialized 128-bit memory that is designed to preserve critical data (such as a 128- bit AES key) even when the device is in the lowest power-saving state. As long as the RTC power supply is still available, the contents of this memory will be retained, even if the AES block and the main SRAM are shut down completely.
Page 33: Peripheral Register Map
MAX32650–MAX32652 User Guide 2.4.2.2 USB Endpoint Buffer Manager The USB AHB bus master is used to manage endpoint buffers in the SRAM. It has access to the SRAM (read/write, for storage and retrieval of endpoint buffer data), as well as the internal and/or external flash data contents (which can be used to contain static data for transmission by the USB).
Page 34 MAX32650–MAX32652 User Guide Peripheral Peripheral Register Name Register Prefix APB Base Address APB End Address GPIO Port 2 GPIO2_ 0x4000 A000 0x4000 AFFF GPIO Port 3 GPIO3_ 0x4000 B000 0x4000 BFFF Timer 0 TMR0_ 0x4001 0000 0x4001 0FFF Timer 1...
Page 35: Ahb Peripheral Base Address Map
MAX32650–MAX32652 User Guide AHB Peripheral Base Address Map Table 2-1, above, contains the base address for each of the AHB mapped peripherals. The base address for a given peripheral is the start of the register map for the peripheral. For a given peripheral, the address for a register within the peripheral is defined as the AHB peripheral base address plus the registers offset.
Page 36: System Clocks, Reset, And Power Management
MAX32650–MAX32652 User Guide System Clocks, Reset, and Power Management There are several clocks used by different peripherals and subsystems on the MAX32650–MAX32652. These clocks are highly configurable by firmware, allowing developers to select the combination of application performance and power savings required for the target systems.
Page 37: Oscillator Sources And Clock Switching
120MHz Internal Main High-Speed Oscillator The MAX32650–MAX32652 is available with a 120MHz internal high-speed oscillator. This is the fastest oscillator and draws the most power. This oscillator is automatically enabled after a Power-On Reset (POR) and following a System Reset.
Page 38: 32.768Khz External Crystal Oscillator
MAX32650–MAX32652 User Guide 32.768kHz External Crystal Oscillator This is a very low power internal oscillator that can be selected as SYSOSC. This oscillator can optionally use a 32.768kHz input clock instead of an external crystal. The internal 32.768kHz clock is available as an output on GPIO as an alternate function (32KCAL).
Page 39: System Oscillators Reset
MAX32650–MAX32652 User Guide System Oscillators Reset On Power-On Reset (POR) and System Reset, all oscillator states are reset to the default: The 40MHz, 120MHz, and 8kHz oscillators are enabled, while the 32.768kHz and 7.3728MHz oscillators are disabled. Oscillators are not reset on Soft Reset or Peripheral Reset.
Page 40: Power Management
CORE Operating Modes The MAX32650–MAX32652 supports five operating modes. ACTIVE is the highest performance operating mode. Any low power state can wake up to ACTIVE by a wakeup event. Wakeup events include any external or internal interrupt, USB wakeup, RTC wakeup, and Watchdog Interrupt.
Page 41: Figure 3-2: Sleep Mode Clock Control
MAX32650–MAX32652 User Guide Figure 3-2: SLEEP Mode Clock Control Maxim Integrated Page 41 of 411...
Page 42: Background Low Power Mode
MAX32650–MAX32652 User Guide BACKGROUND Low Power Mode This mode is suitable for the Smart DMA to operate in the background and perform background processing data transfers on peripheral and SRAM data. This is the same as SLEEP mode except both the CPU clock and CPU power (VCORE) are temporarily gated off. State Retention of the CPU is enabled, allowing all CPU registers to maintain their contents and the oscillators remain active if enabled.
Page 43: Figure 3-3: Background Mode Clock Control
MAX32650–MAX32652 User Guide Figure 3-3: BACKGROUND Mode Clock Control Maxim Integrated Page 43 of 411...
Page 44: Deepsleep Low Power Mode
MAX32650–MAX32652 User Guide DEEPSLEEP Low Power Mode This is like BACKGROUND mode except that all internal clocks are gated off. SYSOSC is gated off, so the two main bus clocks PCLK and HCLK are inactive. The CPU state is retained.
Page 45: Figure 3-4: Deepsleep Clock Control
MAX32650–MAX32652 User Guide Figure 3-4: DEEPSLEEP Clock Control Maxim Integrated Page 45 of 411...
Page 46: Backup Low Power Mode
MAX32650–MAX32652 User Guide BACKUP Low Power Mode This is the lowest power operating mode. All oscillators are disabled except for the 8kHz and the 32kHz oscillator. SYSOSC is gated off, so PCLK and HCLK are inactive. The CPU state is not maintained.
Page 47: Figure 3-5: Backup Mode Clock Control
MAX32650–MAX32652 User Guide Figure 3-5: BACKUP Mode Clock Control Maxim Integrated Page 47 of 411...
Page 48: Shutdown State
MAX32650–MAX32652 User Guide Shutdown State The Shutdown State is not a low-power mode. It is intended to wipe all volatile memory from the device. In the Shutdown state, internal logic gates off all internal power. There is no data, register, or RAM retention in this mode. All wakeup sources, wakeup logic, and interrupts are disabled.
Page 49: Table 3-1: Reset And Low Power Mode Effects
MAX32650–MAX32652 User Guide Table 3-1: Reset and Low Power Mode Effects BACK- Peripheral Soft System ACTIVE SLEEP GROUND DEEP- SLEEP BACKUP Reset Reset Reset Mode Mode Mode Mode Mode GCR Reset Reset Reset 8kHz Osc 32kHz Osc 7.3728 MHz Osc...
Page 50: Cache
¹ The Always On Domain (AOD) is only reset on power-cycling V Cache There are three cache controllers in the MAX32650–MAX32652. Each cache controller is independently managed. Figure shows the three cache controllers and their memory interfaces. Instruction Cache Controller 0 (ICC0) and Instruction Cache Controller 1 (ICC1) are used for instruction caching only.
Page 51: Instruction Cache Controller
MAX32650–MAX32652 User Guide Figure 3-6: MAX32650–MAX32652 Cache Controllers Diagram Instruction Cache Controller ICC0 and ICC1 are independent cache controllers and each is controlled directly using their respective register set. Enabling ICC0/ICC1 Perform the following steps to enable ICC0 or ICC1.
Page 52: Flushing The Icc0/Icc1 Cache
MAX32650–MAX32652 User Guide Flushing the ICC0/ICC1 Cache The System Configuration Register (GCR_SCON) includes a field for flushing both ICC0 and ICC1 simultaneously. Setting GCR_SCON.ccache_flush to 1 performs a flush of both ICC0 and ICC1 cache. Flush only one of the ICC caches by invalidating the cache contents.
Page 53: External Memory Cache Controller
MAX32650–MAX32652 User Guide Table 3-5: ICC Cache Control Register ICC Cache Control Register ICCn_CACHE_CTRL [0x0100] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. ready Ready This field is cleared by hardware anytime the cache as a whole is invalidated (including a Power On Reset event).
Page 54: Ram Low Power Modes
MAX32650–MAX32652 User Guide The following RAM memories can be zeroized: • The Internal Data RAMs 0 through 6.  Each of the internal data RAM segments can be zeroized independently by setting the GCR_MEM_ZERO.sram0z through GCR_MEM_ZERO.sram6z fields to 1. •...
Page 55: Global Control Register Details
MAX32650–MAX32652 User Guide Offset Register Name Access Description [0x0008] GCR_CLK_CTRL Clock Control Register [0x000C] GCR_PMR Power Management Register [0x0018] GCR_PCLK_DIV Peripheral Clocks Divisor [0x0024] GCR_PCLK_DIS0 Peripheral Clocks Disable 0 [0x0028] GCR_MEM_CLK Memory Clock Control [0x002C] GCR_MEM_ZERO Memory Zeroize Register [0x0040]...
Page 56 MAX32650–MAX32652 User Guide System Control Register GCR_SCON [0x0000] Bits Name Access Reset Description dcache_dis External Memory Cache Controller Disable This disables the EMCC used for SPIXR or HyperBus/Xccela Bus code and data cache. Setting this field disables the EMC and bypass the EMCC line buffer.
Page 57: Table 3-9: Reset Register 0
MAX32650–MAX32652 User Guide Table 3-9: Reset Register 0 Reset Register 0 GCR_RST0 [0x0004] Bits Name Access Reset Description sys_rst R/W1 System Reset This resets everything on the device except AoD and RAM retention. GCR are reset. 1: Write 1 to perform a System Reset.
Page 58 MAX32650–MAX32652 User Guide Reset Register 0 GCR_RST0 [0x0004] Bits Name Access Reset Description crypto R/W1 Cryptographic Reset This resets the AES block, SHA block, and DES block. Write 1 to reset the peripheral. 1: Reset peripheral or peripheral reset not yet complete.
Page 59: Table 3-10: System Clock Control Register
MAX32650–MAX32652 User Guide Reset Register 0 GCR_RST0 [0x0004] Bits Name Access Reset Description timer2 R/W1 Timer2 Reset Write 1 to reset the peripheral. 1: Reset peripheral or peripheral reset not yet complete. 0: Peripheral reset complete or not actively being reset.
Page 60 MAX32650–MAX32652 User Guide System Clock Control Register GCR_CLK_CTRL [0x0008] Bits Name Access Reset Description hircmm_rdy 120MHz Internal Oscillator Ready Status On POR or System Reset this field reads 1 until the oscillator is ready. 1: Oscillator not ready/warmed up and cannot be used.
Page 61: Table 3-11: Power Management Register
MAX32650–MAX32652 User Guide System Clock Control Register GCR_CLK_CTRL [0x0008] Bits Name Access Reset Description sysosc_rdy SYSOSC Select Ready When SYSOSC is changed by modifying sysosc_sel, there is a delay until the switchover is complete. This bit is cleared until the switchover is complete.
Page 62: Table 3-12: Peripheral Clock Divisor Register
MAX32650–MAX32652 User Guide Power Management Register GCR_PMR 0x000C Bits Name Access Reset Description usbwken USB Wakeup Enable When enabled, a USB wakeup event causes an exit from all low power modes and transitions directly to ACTIVE mode. 0: Wakeup from USB disabled.
Page 63: Table 3-13: Peripheral Clock Disable Register 0
MAX32650–MAX32652 User Guide Peripheral Clocks Divisor Register GCR_PCLK_DIV [0x0018] Bits Name Access Reset Description sdhcfrq SDHC Clock Frequency Configures the frequency of the SDHC as a divisor of the 120MHz high-speed oscillator. 120�� 0: �� _�� 120�� 1: ��...
Page 64 MAX32650–MAX32652 User Guide Peripheral Clocks Disable 0 GCR_PCLK_DIS0 [0x0024] Bits Name Access Reset Description timer5 Timer5 Clock Disable Write 0 to enable or 1 to disable. 0: Enabled 1: Disabled timer4 Timer4 Clock Disable Write 0 to enable or 1 to disable.
Page 65: Table 3-14: Memory Clock Control Register
MAX32650–MAX32652 User Guide Peripheral Clocks Disable 0 GCR_PCLK_DIS0 [0x0024] Bits Name Access Reset Description spi1 SPI1 Clock Disable Write 0 to enable or 1 to disable. 1: Disabled 0: Enabled spi0 SPI0 Clock Disable Write 0 to enable or 1 to disable.
Page 66 MAX32650–MAX32652 User Guide Memory Clock Control GCR_MEM_CLK [0x0028] Bits Name Access Reset Description cryptols Crypto RAM Light Sleep Enable Write 1 to enter Light Sleep low power state. Data is unavailable for read/write operations in light sleep mode but is retained. Write 0 put the RAM into active mode for read and write access.
Page 67: Table 3-15: Memory Zeroization Control Register
MAX32650–MAX32652 User Guide Memory Clock Control GCR_MEM_CLK [0x0028] Bits Name Access Reset Description sysram0ls System RAM 0 (0x2000 0000 - 0x2000 7FFF) Light Sleep Enable Write 1 to enter Light Sleep low power state. Data is unavailable for read/write operations in light sleep mode but is retained. Write 0 put the RAM into active mode for read and write access.
Page 68 MAX32650–MAX32652 User Guide Memory Zeroization Control Register GCR_MEM_ZERO [0x002C] Bits Name Access Reset Description scachedataz R/W1 External Memory Controller Cache (EMCC) Data Zeroization Write 1 to clear the EMCC Data RAM to 0. The bit is set to 0 when the operation is complete.
Page 69: Table 3-16: System Status Flag Register
MAX32650–MAX32652 User Guide Table 3-16: System Status Flag Register System Status Flag Register GCR_SYS_STAT [0x0040] Bits Name Access Reset Description 31:6 Reserved for Future Use Do not modify this field. scmemf HyperBus/Xccela Cache Memory Error Status Flag Indicates a memory fault has occurred in the cache while receiving data from the HyperBus/Xccela interface.
Page 70 MAX32650–MAX32652 User Guide Reset Register 1 GCR_RST1 [0x0044] Bits Name Access Reset Description R/W1 S (SPIMSS) Reset Write 1 to reset the peripheral state and reset the peripheral registers. When complete this field will read 0. 1: Write 1 to reset the peripheral. If this field reads 1, the peripheral is actively being reset by hardware.
Page 71: Table 3-18: Peripheral Clock Disable Register 1
MAX32650–MAX32652 User Guide Reset Register 1 GCR_RST1 [0x0044] Bits Name Access Reset Description spixip R/W1 SPI-XIPF Reset Write 1 to reset the peripheral state and reset the peripheral registers. When complete this field will read 0. Reserved for Future Use Do not modify this field.
Page 72 MAX32650–MAX32652 User Guide Peripheral Clock Disable Register 1 GCR_PCLK_DIS1 [0x0048] Bits Name Access Reset Description icachexipf SPI-XIPF Flash Clock Disable Write 1 to disable the clock to the corresponding peripheral. Disabling a clock peripheral makes the peripheral non-functional while also saving power. Reads and writes to peripheral registers are disabled.
Page 73: Table 3-19: Event Enable Register
MAX32650–MAX32652 User Guide Peripheral Clock Disable Register 1 GCR_PCLK_DIS1 [0x0048] Bits Name Access Reset Description HyperBus/Xccela Clock Disable Write 1 to disable the clock to the corresponding peripheral. Disabling a clock peripheral makes the peripheral non-functional while also saving power. Reads and writes to peripheral registers are disabled.
Page 74: Function Control Registers
MAX32650–MAX32652 User Guide Event Enable Register GCR_EVENT_EN [0x004C] Bits Name Access Reset Description dmaevent DMA CTZ Event Wake-Up Enable When set, when a DMA block transfer is completed and the DMA counter DMAn_CNT.cnt = 0, a CTZ DMA event occurs which generates an RXEV to wake-up the device from a low power mode entered with a WFE instruction.
Page 75: Function Control Register Details
MAX32650–MAX32652 User Guide Table 3-22: Function Control Registers Offset Register Name Access Description [0x0800] GCR_FCR Function Control Register [0x0804] GCR_AUTO_CAL Autocalibration Register [0x0808] GCR_AUTO_CAL_TRIM Autocalibration Trim Control Register [0x080C] GCR_AUTO_CAL_CNT Autocalibration Count Register [0x5810] AOD_HYP_CLK_CN HyperBus/Xccela Clock Control Register 3.16...
Page 76: Table 3-24: Autocalibration Function Control Register 1
MAX32650–MAX32652 User Guide Table 3-24: Autocalibration Function Control Register 1 Autocalibration Function Control Register 1 GCR_AUTO_CAL [0x0804] Bits Name Access Reset Description 31:20 Reserved for Future Use Do Not Modify this Field. 19:8 Auto Calibration Loop Gain atomic_cal_en R/W1 Atomic Mode Start Write 1 to start atomic mode calibration.
Page 77: Aes Key Registers
MAX32650–MAX32652 User Guide Autocalibration Function Control Register 2 GCR_AUTO_CAL_TRIM [0x0808] Bits Name Access Reset Description initial_trim See description Initial Trim Initial trim value for the device set during production test. This factory set field is used by auto-calibration to ensure the auto-calibration calculated trim is valid for the device.
Page 78: Aes Key Register Details
VCORE, VDDA, and VRTC have power failure monitors. When enabled, if that power supply drops below the power fail reset voltage the entire device goes into a Power-On Reset. See the MAX32650–MAX32652 data sheet for the trigger threshold values and power fail reset voltages. When any power supply monitor is tripped, a Power Fail Warning Interrupt is triggered.
Page 79: Aod Low Power Control Registers
MAX32650–MAX32652 User Guide 3.20 AOD Low Power Control Registers Refer to Table 2-1: APB Peripheral Base Address Map for the AoD Low Power Control (LP_) Register’s Base Peripheral Address. Note: These registers are in the Always-on Domain and are only reset on a Power-On Reset.
Page 80 MAX32650–MAX32652 User Guide Low Power Voltage Control Register LP_CTRL [0x0000] Bits Name Access Reset Description vddamd VDDA (V ) Analog Supply Power Monitor Disable Write 1 to disable the corresponding power monitor. With a power monitor enabled, if the voltage drops below the trigger threshold all registers in that power domain are reset.
Page 81: Table 3-33: Low Power Gpio Wakeup Interrupt Enable Registers
MAX32650–MAX32652 User Guide Table 3-33: Low Power GPIO Wakeup Interrupt Enable Registers GPIO0 Wakeup Interrupt Enable LP_GPIO0_WK_EN [0x0008] GPIO1 Wakeup Interrupt Enable LP_GPIO1_WK_EN [0x0010] GPIO2 Wakeup Interrupt Enable LP_GPIO2_WK_EN [0x0018] GPIO3 Wakeup Interrupt Enable LP_GPIO3_WK_EN [0x0020] Bits Name Access Reset...
Page 82: Table 3-36: Low Power Usb Wakeup Enable Register
MAX32650–MAX32652 User Guide Low Power USB Wakeup Flag Register LP_USB_WK_FL [0x0030] Bits Name Access Reset Description usbvbuswkst R/W1C USB V State Change Detect Flag 0: Normal operation 1: The USB has been powered on or off by plugging or unplugging an external USB Host.
Page 83 MAX32650–MAX32652 User Guide Low Power RAM Power Control LP_MEM_PWR [0x0040] Bits Name Access Reset Description scachesd External Memory Controller Cache (EMCC) RAM Shut Down Write 1 to shut off power to the External Memory Cache 16KB RAM. Note: Setting this field to 1 does not bypass the EMCC’s line buffer.
Page 84: Interrupts And Exceptions
Interrupt Vector Table Table 4-1 lists the interrupt and exception table for the MAX32650. There are 80 interrupt entries for the MAX32650, including reserved for future use interrupt place holders. Including the 15 system exceptions for the Arm Cortex-M4 with FPU, the total number of entries is 96.
Page 85 MAX32650–MAX32652 User Guide Exception Offset Name Description (Interrupt) Number [0x005C] TMR2_IRQHandler Timer 2 Interrupt [0x0060] TMR3_IRQHandler Timer 3 Interrupt [0x0064] TMR4_IRQHandler Timer 4 Interrupt [0x0068] TMR5_IRQHandler Timer 5 Interrupt [0x006C] Reserved for Future Use [0x0070] CLCD_IRQHandler CLCD Controller Interrupt [0x0074]...
Page 86 MAX32650–MAX32652 User Guide Exception Offset Name Description (Interrupt) Number [0x0128] GPIO3_IRQHandler GPIO Port 3 Interrupt [0x012C] PT_IRQHandler Pulse Train Interrupt [0x0130] SDMA_IRQHandler Smart DMA Interrupt [0x0134] HPB_IRQHandler HyperBus Interrupt 78:81 [0x0138]: [0x0144] Reserved for Future Use [0x0148] SDHC_IRQHandler SDHC Interrupt...
Page 87: General-Purpose I/O And Alternate Function Pins
General Description The MAX32650–MAX32652 includes four total GPIO ports; port 0 (P0), port 1 (P1), port 2 (P2) and port 3 (P3). P0, P1 and P2 support up to 32 GPIO pins each (P0[0:31], P1[0:31] and P2[0:31]) and P3 supports up to 10 GPIO pins (P3[0:9]). Each of the four ports maps to a GPIO register set with P0 mapped to GPIO0, P1 mapped to GPIO1, P2, mapped to GPIO2 and P3 mapped to GPIO3.
Page 88 Table 5-1, Table 5-2 Table 5-3, below, show the GPIO and the assigned AF1 and AF2 for the 140-WLP, 144-TQFP and 96-WLP packages of the MAX32650–MAX32652. Maxim Integrated Page 88 of 411...
Page 89: Table 5-1: Gpio Port, Pin Name And Alternate Function Matrix, 140 Wlp
MAX32650–MAX32652 User Guide Table 5-1: GPIO Port, Pin Name and Alternate Function Matrix, 140 WLP 140-WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO0[0] P0.0 SPIXF_SDIO2 GPIO0[1] P0.1 SPIXR_SDIO0 GPIO0[2] P0.2 SPIXR_SDIO2 GPIO0[3] P0.3 SPIXR_SCK GPIO0[4] P0.4 SPIXR_SDIO3 GPIO0[5] P0.5...
Page 90 MAX32650–MAX32652 User Guide 140-WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO0[31] P0.31 32KCAL SDHC_CDN GPIO1[0] P1.0 SDHC_CMD SPIXF_SDIO3 GPIO1[1] P1.1 SDHC_DAT2 SPIXF_SDIO1 GPIO1[2] P1.2 SDHC_WP SPIXF_SS0 GPIO1[3] P1.3 SDHC_DAT3 CLCD_CLK GPIO1[4] P1.4 SDHC_DAT0 SPIXF_SDIO0 GPIO1[5] P1.5 SDHC_CLK...
Page 91 MAX32650–MAX32652 User Guide 140-WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO2[0] P2.0 SPI2_SS2 GPIO2[1] P2.1 SPI2_SS1 PT10 GPIO2[2] P2.2 SPI2_SCK (I2S_BCLK)† CLCD_LEND GPIO2[3] P2.3 SPI2_MISO (I2S_SDI)† CLCD_PWREN GPIO2[4] P2.4 SPI2_MOSI (I2S_SDO)† GPIO2[5] P2.5 SPI2_SS0 (I2S_LRCLK)† PT11 GPIO2[6] P2.6...
Page 92: Table 5-2: Gpio Port, Pin Name And Alternate Function Matrix, 144 Tqfp
MAX32650–MAX32652 User Guide 140-WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO3[2] P3.2 SPI0_MOSI GPIO3[3] P3.3 SPI0_SCK GPIO3[4] P3.4 TMR0 GPIO3[5] P3.5 TMR2 GPIO3[6] P3.6 TMR4 GPIO3[7] P3.7 TMR1 GPIO3[8] P3.8 TMR3 GPIO3[9] P3.9 TMR5 Table 5-2: GPIO Port, Pin Name and Alternate Function Matrix, 144 TQFP...
Page 93 MAX32650–MAX32652 User Guide 144-Pin TQFP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO0[20] P0.20 SPI3_SDIO1 CLCD_G7 GPIO0[21] P0.21 SPI3_SDIO0 GPIO0[22] P0.22 SPI0_SS0 CLCD_VDEN GPIO0[23] P0.23 PT15 CLCD_CLK GPIO0[24] P0.24 RXEV CLCD_HSYNC GPIO0[25] P0.25 TXEV CLCD_B0 GPIO0[26] P0.26 GPIO0[27] P0.27...
Page 94 MAX32650–MAX32652 User Guide 144-Pin TQFP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO1[22] P1.22 GPIO1[23] P1.23 SPI1_SS0 CLCD_B1 GPIO1[24] P1.24 SPI1_SS2 CLCD_B2 GPIO1[25] P1.25 SPI1_SS1 CLCD_B3 GPIO1[26] P1.26 SPI1_SCK CLCD_B4 GPIO1[27] P1.27 SPI1_SS3 CLCD_B5 GPIO1[28] P1.28 SPI1_MISO CLCD_B6 GPIO1[29] P1.29...
Page 95: Table 5-3: Gpio Port, Pin Name And Alternate Function Matrix, 96 Wlp
MAX32650–MAX32652 User Guide 144-Pin TQFP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO2[22] P2.22 GPIO2[23] P2.23 SPIXR_SDIO3 GPIO2[24] P2.24 GPIO2[25] P2.25 PT11 GPIO2[26] P2.26 PT12 GPIO2[27] P2.27 GPIO2[28] P2.28 PT14 GPIO2[29] P2.29 GPIO2[30] P2.30 GPIO2[31] P2.31 GPIO3[0] P3.0...
Page 96 MAX32650–MAX32652 User Guide 96-Pin WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO0[9] P0.9 GPIO0[10] P0.10 GPIO0[11] P0.11 SPIXF_SDIO2 P0.11 GPIO0[12] P0.12 GPIO0[13] P0.13 SPI3_SS1 CLCD_G0 GPIO0[14] P0.14 SPI3_SS2 CLCD_G1 GPIO0[15] P0.15 SPI3_SDIO3 CLCD_G2 GPIO0[16] P0.16 SPI3_SCK CLCD_G3 GPIO0[17] P0.17...
Page 97 MAX32650–MAX32652 User Guide 96-Pin WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO1[10] P1.10 UART2_TX GPIO1[11] P1.11 SPIXR_SDIO0 GPIO1[12] P1.12 SPIXR_SDIO1 GPIO1[13] P1.13 SPIXR_SS0 GPIO1[14] P1.14 GPIO1[15] P1.15 SPIXR_SDIO2 GPIO1[16] P1.16 SPIXR_SCK GPIO1[17] P1.17 GPIO1[18] P1.18 GPIO1[19] P1.19 GPIO1[20] P1.20...
Page 98 MAX32650–MAX32652 User Guide 96-Pin WLP GPIO Port[pin] GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO2[10] P2.10 GPIO2[11] P2.11 UART0_RX PT13 GPIO2[12] P2.12 UART0_TX PT15 GPIO2[13] P2.13 UART1_CTS CLCD_R2 GPIO2[14] P2.14 UART1_RX CLCD_R3 GPIO2[15] P2.15 UART1_RTS CLCD_R4 GPIO2[16] P2.16 UART1_TX CLCD_R5 GPIO2[17] P2.17...
Page 99: Gpio
3. Set the output drive strength using the GPIOn_DS_SEL1[pin] and GPIOn_DS_SEL0[pin] bits. Refer to GPIO Drive Strength Selection for modes. Refer to the MAX32650–MAX32652 data sheet for the electrical characteristics for the drive strength selection modes. 4. Set the output high or low using the GPIOn_OUT[pin] bit.
Page 100: Input Modes And Pulldown/Pullup Strength Selection
MAX32650–MAX32652 User Guide Input Modes and Pulldown/Pullup Strength Selection Each GPIO pin supports selection between high-impedance input mode, weak or strong pullup mode, or weak or strong pulldown mode when the pin is set for I/O mode (GPIOn_EN[pin] = 1) and the input register is enabled (GPIOn_IN_EN[pin] = 1).
Page 101: Using Gpio For Wakeup From Low Power Modes
MAX32650–MAX32652 User Guide To handle GPIO interrupts in your interrupt vector handler, complete the following steps: 1. Read the GPIOn_INT_STAT register to determine the GPIO pin that triggered the interrupt. 2. Complete interrupt tasks associated with the interrupt source pin (application defined).
Page 102 MAX32650–MAX32652 User Guide Offset Register Name Description [0x0018] GPIOn_OUT GPIOn Output register [0x001C] GPIOn_OUT_SET Atomic set for GPIOn_OUT register [0x0020] GPIOn_OUT_CLR Atomic clear for GPIOn_OUT register [0x0024] GPIOn_IN GPIOn Input register [0x0028] GPIOn_INT_MODE GPIOn Interrupt mode register [0x002C] GPIOn_INT_POL GPIOn Interrupt polarity register...
Page 103: Gpio Register Details
MAX32650–MAX32652 User Guide GPIO Register Details Table 5-8: GPIO Port 0 Enable Register GPIO0_EN GPIO Port 0 Enable Register [0x0000] Bits Name Access Reset Description 31:30 GPIO Enable Each bit in this register controls the GPIO enable and alternate function enable for a pin on this GPIO port.
Page 104: Table 5-9: Gpio Port 1 To Port 3 Enable Registers
MAX32650–MAX32652 User Guide Table 5-9: GPIO Port 1 to Port 3 Enable Registers GPIO Port Enable Register GPIOn_EN [0x0000] Bits Name Access Reset Description 31:0 GPIO Enable Each bit in this register controls the GPIO enable and alternate function enable for a pin on this GPIO port.
Page 105: Table 5-13: Gpio Port 1 To Port 3 Output Enable Registers
MAX32650–MAX32652 User Guide GPIO Port 0 Output Enable Register GPIO0_OUT_EN [0x000C] Bits Name Access Reset Description GPIO Output Enable This pin defaults to output enabled if JTAG debug is available on the part and maps to alternate function JTAG TDO.
Page 106: Table 5-15: Gpio Port 0 To Port 3 Output Enable Atomic Clear Registers
MAX32650–MAX32652 User Guide Table 5-15: GPIO Port 0 to Port 3 Output Enable Atomic Clear Registers GPIO Port Output Enable Atomic Clear Register GPIOn_OUT_EN_CLR [0x0014] Bits Name Access Reset Description 31:0 GPIO Output Enable Atomic Clear Writing 1 to one or more bits in this register clears the corresponding bits in the GPIOn_OUT_EN register.
Page 107: Table 5-19: Gpio Port 0 To Port 3 Input Registers
MAX32650–MAX32652 User Guide Table 5-19: GPIO Port 0 to Port 3 Input Registers GPIO Port Input Register GPIOn_IN [0x0024] Bits Name Access Reset Description 31:0 GPIO Input Read the state of the corresponding input pin. The corresponding pin must be...
Page 108: Table 5-22: Gpio Port 0 To Port 3 Input Enable Registers
MAX32650–MAX32652 User Guide Table 5-22: GPIO Port 0 to Port 3 Input Enable Registers GPIO Port Input Enable Register GPIOn_IN_EN [0x0030] Bits Name Access Reset Description 31:0 GPIO Input Enable Connects the corresponding input pad to the specified input pin for reading the pin...
Page 109: Table 5-26: Gpio Port 0 To Port 3 Interrupt Status Registers
MAX32650–MAX32652 User Guide Table 5-26: GPIO Port 0 to Port 3 Interrupt Status Registers GPIO Port Interrupt Status Register GPIOn_INT_STAT [0x0040] Bits Name Access Reset Description 31:0 GPIO Interrupt Status An interrupt is pending for the associated GPIO pin when this bit reads 1.
Page 110: Table 5-30: Gpio Port 0 To Port 3 Wakeup Enable Clear Registers
MAX32650–MAX32652 User Guide Table 5-30: GPIO Port 0 to Port 3 Wakeup Enable Clear Registers GPIO Port Wakeup Enable Atomic Clear Register GPIOn_WAKE_EN_CLR [0x0054] Bits Name Access Reset Description 31:0 GPIO Wakeup Enable Atomic Clear Writing 1 to one or more bits in this register clears the corresponding bits in the GPIOn_WAKE_EN register.
Page 111: Table 5-34: Gpio Port 0 To Port 3 Alternate Function Select Registers
MAX32650–MAX32652 User Guide Table 5-34: GPIO Port 0 to Port 3 Alternate Function Select Registers GPIO Port AF Select Register GPIOn_AF_SEL [0x0068] Bits Name Access Reset Description 31:0 GPIO Alternate Select Function When the GPIOn_EN[pin] is set to 0 (Alternate Function Enabled), this bit selects either Alternate Function 1 or Alternate Function 2 for the pin.
Page 112: Table 5-37: Gpio Port 0 To Port 3 Drive Strength Selection 0 Registers
0: Weak (1MΩ) Pulldown/Pullup resistor for input pin. 1: Strong (25KΩ) Pulldown/Pullup resistor for input pin. Note: Refer to the MAX32650–MAX32652 data sheet for specific electrical characteristics of the Pulldown/Pullup resistances. Table 5-40: GPIO Port 0 Supply Voltage Select Register...
Page 113: Table 5-41: Gpio Port 1 Supply Voltage Select Register
MAX32650–MAX32652 User Guide Table 5-41: GPIO Port 1 Supply Voltage Select Register GPIO Port 1 Voltage Select Register GPIO1_VSSEL [0x00C0] Bits Name Access Reset Description 31:22 GPIO Supply Voltage Select Select the Supply Voltage for the pin. Set to 1 to select V...
Page 114 MAX32650–MAX32652 User Guide GPIO Port 3 Supply Voltage Select Register GPIO3_VSSEL [0x00C0] Bits Name Access Reset Description GPIO Supply Voltage Select GPIO3[0] (P3.0) is tied to the V supply and cannot be set to V for the DDIO DDIOH supply selection.
Page 115: Flash Controller
MAX32650–MAX32652 User Guide Flash Controller The MAX32650–MAX32652 Flash Controller is a peripheral that manages read, write, and erase accesses to the internal flash. Features • Up to 3 MB total internal flash memory  192 pages  16,384 bytes per page ...
Page 116: Lock Protection
MAX32650–MAX32652 User Guide Equation 6-1: Flash Controller Clock Frequency �� = 1�� _��. �� Lock Protection The Flash Controller provides a locking mechanism to prevent accidental writes and erases. All writes and erase operations require the FLC_CTRL.unlock field be set to 0x2 prior to starting the operation. Writing any other value to this field, FLC_CTRL.unlock, results in the flash remaining locked.
Page 117: Page Erase
MAX32650–MAX32652 User Guide Page Erase Perform the following to erase a page of internal flash memory: 1. If desired, enable flash controller interrupts by setting the FLC_INTR.access_error_ie and FLC_INTR.done_ie bits. 2. Set the FLC_ADDR register to a page address to erase. FLC_ADDR[11:0] are ignored by the Flash Controller to ensure the address is page aligned.
Page 118: Flash Controller Register Details
MAX32650–MAX32652 User Guide Offset Register Name Access Description [0x0024] FLC_INTR Flash Controller Interrupt Register [0x0030] FLC_DATA0 Flash Controller Data Register 0 [0x0034] FLC_DATA1 Flash Controller Data Register 1 [0x0038] FLC_DATA2 Flash Controller Data Register 2 [0x003C] FLC_DATA3 Flash Controller Data Register 3 Flash Controller Register Details Table 6-3.
Page 119 MAX32650–MAX32652 User Guide Flash Controller Control Register FLC_CTRL [0x0008] Bits Name Access Reset Description busy Flash Busy Flag When this field is set, writes to all flash registers except the FLC_INTR register are ignored by the Flash Controller. Note: If the Flash Controller is busy (FLC_CTRL.busy = 1), reads, writes and erase operations are not allowed and result in an access failure (FLC_CTRL.access_fail = 1).
Page 120: Table 6-5: Flash Controller Interrupt Register
MAX32650–MAX32652 User Guide Flash Controller Control Register FLC_CTRL [0x0008] Bits Name Access Reset Description write R/W1O Write If this field reads 0, no write operation is pending for the flash. To initiate a write operation, set this bit to 1 and the Flash Controller will write to the...
Page 121: Table 6-7: Flash Controller Data Register 1
MAX32650–MAX32652 User Guide Table 6-7: Flash Controller Data Register 1 Flash Controller Data Register 1 FLC_DATA1 [0x0034] Bits Name Access Reset Description 31:0 data1 Flash Data 1 Flash data for bits 63:32 Table 6-8: Flash Controller Data Register 2 Flash Controller Data Register 2...
Page 122: External Memory
MAX32650–MAX32652 User Guide External Memory Overview External memory can be accessed via multiple interfaces. There a four external memory interfaces, three of which are backed by 16KB of cache: • SPI Execute-in-Place FLASH (SPIXF)  16KB Dedicated Cache • SPI Execute-in-Place RAM (SPIXR) ...
Page 123: Spi Pin Configuration
MAX32650–MAX32652 User Guide The SPIXF Master Controller block shown in Figure 7-1 consists of transmit and receive shift registers (supported by FIFOs) and a control unit. Communication and interface configuration are set up using the APB registers. It contains one 16×16 FIFO (Transaction FIFO) to support the transmit direction and one 32×8 FIFO (Results FIFO) to support the receive direction.
Page 124: Table 7-1: Spi Header Format
MAX32650–MAX32652 User Guide 7.2.2.2 SPI Master Controller Transaction Once the SPI master is configured to communicate to a specific slave, SPI transactions are initiated by writing to the SPI Transaction FIFO mapped into the AHB system address map at 0x400BC000. The FIFO is 16-bits wide and expects a 16-bit header followed by an optional payload padded out to a word boundary.
Page 125 MAX32650–MAX32652 User Guide Name Bits Description Settings De-assert SS When asserted, de-assert Slave Select at the completion of this transaction. Header Type 15:14 Must be 00 7.2.2.3 Sample SPIXF Master Controller Example Here is an example how to set up the Master Controller: 1.
Page 126: Table 7-2: Clock Polarity And Phase Combinations
MAX32650–MAX32652 User Guide Table 7-2 details the SCK phase and polarity combinations supported. Table 7-2: Clock Polarity and Phase Combinations PHASE CLKPOL Transmit Edge Receive Edge Idle State Falling Rising Falling Rising High Note: Do not change the clock phase and polarity control while executing or reading from SPIXF space. This configuration should ideally be done prior to SPIXF transactions and remain unchanged while reading or executing from SPIXF space.
Page 127: Figure 7-2. Spixf Mode
MAX32650–MAX32652 User Guide Figure 7-2. SPIXF Mode 7.2.2.7 Slave Select The SPIXF Master Controller operates with one slave device. A dedicated select pin for slave #0 is provided and controlled by hardware. Both execute-in-place and data storage are supported on slave #0.
Page 128: Figure 7-3. Spixf Transaction Delay
MAX32650–MAX32652 User Guide Figure 7-3. SPIXF Transaction Delay SPIXF MODE 0 SPIXF MODE 3, SCKINH3 = 0 SCKINH3=0 SPIXF MODE 3, SCKINH3 = 1 SCKINH3 7.2.2.9 External SPI Flash Encryption The user may optionally store encrypted data or code in the external SPI flash. Encryption of the SPI flash data is achieved using the cryptographic accelerator to encrypt the data and the SPIXF Master Controller to write the data.
Page 129: Table 7-3: Encrypted Data Write Order To Spix Flash Memory
MAX32650–MAX32652 User Guide data_out = AES(data_in ^ ((addr_mask << 96) | ((addr_mask+4) << 64) | \ ((addr_mask+8) << 32) | (addr_mask+12))) where: data_in = word0:word1:word2:word3 (big endian format) When using the cryptographic accelerator, the input data should be loaded as follows:...
Page 130 MAX32650–MAX32652 User Guide SPIXF Controller Configuration Register SPIXFC_CFG [0x0000] Bits Name Access Reset Description 23:20 iosmpl Sample Delay Defines additional delay in SPI clock periods to wait before sampling SDIO input. This value must be less than or equal to the value set for HICLK (for SPI modes 0 and 3).
Page 131: Table 7-6. Spixf Controller Slave Select Polarity Register
MAX32650–MAX32652 User Guide SPIXF Controller Configuration Register SPIXFC_CFG [0x0000] Bits Name Access Reset Description mode SPI Mode. Defines the SPI mode. 00: SPI Mode 0. Clock Polarity = 0, Clock Phase = 0 01: Invalid 10: Invalid 11: SPI Mode 3. Clock Polarity = 1, Clock Phase = 1 Reserved for Future Use Do not modify this field.
Page 132 MAX32650–MAX32652 User Guide SPIXF Controller General Control Register SPIXFC_GEN_CTRL [0x0008] Bits Name Access Reset Description simplerx Simple Receive Enable Setting this bit to a 1 initiates a SPI transaction as defined in the Receive-Only Transaction Header when in Simple Mode.
Page 133: Table 7-8. Spixf Controller Fifo Control And Status Register
MAX32650–MAX32652 User Guide SPIXF Controller General Control Register SPIXFC_GEN_CTRL [0x0008] Bits Name Access Reset Description rfifoen Results FIFO Enable Setting this bit enables the Results FIFO. Clearing this bit disables the Results FIFO and places it into a reset state.
Page 134: Table 7-9. Spixf Controller Special Control Register
MAX32650–MAX32652 User Guide Table 7-9. SPIXF Controller Special Control Register SPIXF Controller Special Control Register SPIXFC_SP_CTRL [0x0010] Bits Name Access Reset Description 31:17 Reserved for Future Use Do not modify this field. sckinh3 SCK Inhibit mode 3 In SPI mode 3, some SPI flash read timing diagrams show the last SCK going low prior to de-assertion.
Page 135: Table 7-11. Spixf Controller Interrupt Enable Register
MAX32650–MAX32652 User Guide SPIXF Controller Interrupt Status Register SPIXFC_INT_FL [0x0014] Bits Name Access Reset Description rfifoaf R/W1C Results FIFO Almost Full Flag. This flag is set by hardware when the Results FIFO is almost full as defined by rfifolvl. 0: Results FIFO level below the Almost Full level 1: Results FIFO level at almost full level.
Page 136: Table 7-12. Spixf Master Controller Fifo Register Offsets, Names, Access And Description
MAX32650–MAX32652 User Guide SPIXF Controller Interrupt Enable Register SPIXFC_INT_EN [0x0018] Bits Name Access Reset Description tfifoaeie Transaction FIFO Almost Empty Interrupt Enable. Setting this bit enables interrupt generation when the SPIXFC_INT_FL.tfifoae flag is set. Clearing this bit means that no interrupt is generated.
Page 137: Spixf Master
MAX32650–MAX32652 User Guide Table 7-14. SPIXF Master Controller TX FIFO Register SPIXF Master Controller RX FIFO Register SPIXFC_FIFO_RX [0x0004] Bits Name Access Reset Description 31:0 data RX FIFO Reads from this register return the data from the SPIXF Master Controller RX FIFO.
Page 138: Figure 7-4. Supported Spi Configuration
MAX32650–MAX32652 User Guide Figure 7-4. Supported SPI configuration 7.2.3.2 Slave-Select Transaction Delay Configuration The transaction delay and slave-select timing with respect to the active or inactive slave-select edge is determined by a combination of the following register fields: • SPIXF_CFG.ssact •...
Page 139: Figure 7-5. Spixf Delay Configuration
MAX32650–MAX32652 User Guide Figure 7-5. SPIXF Delay Configuration 7.2.3.3 SPIXF Read Sequence Configuration and Control Assertion of SPIXF slave select followed by the read command, then the read address. After the read address is sent 0 or more clocks are generated (called dummy bytes or mode clocks) to allow the flash to access the data being addressed. The remainder of the SPI access is read data.
Page 140 MAX32650–MAX32652 User Guide 7.2.3.4 Sample SPIXF Master Configuration - Execute Code Complete the following steps to execute the SPIXF Master Configuration sample: 1. Turn on ICache XIP Clock (GCR_PCLK_DIS1.icachexipf = 1). The cache can be put into different power states. See GCR_MEM_CLK for options.
Page 141: Table 7-15. Spixf Master Register Addresses (Base Addr = 0X4002 6000)
MAX32650–MAX32652 User Guide 7.2.3.7 External SPI Flash Decryption If data in the SPI flash is encrypted when written, it might be transparently decrypted on read back using either code execution or data reads. Decryption is not enabled by default. Setting SPIXF_SEC_CTRL.decen = 1 enables the Memory Decryption Unit (MDU).
Page 142: Table 7-17. Spixf Fetch Control Register
MAX32650–MAX32652 User Guide SPIXF Configuration Register SPIXF_CFG [0x0000] Bits Name Access Reset Description 15:12 hiclk SCK High Clocks Number of system clocks that SCK is held high when SCK pulses are generated. 0: Invalid All other values: The number of system clocks that SCK is held high.
Page 143: Table 7-18. Spixf Mode Control Register
MAX32650–MAX32652 User Guide SPIXF Fetch Control Register SPIXF_FETCH_CTRL [0x0004] Bits Name Access Reset Description 11:10 addr_width Address Width Number of data I/O used to send address and mode/dummy clocks. 0b00: Single SDIO 0b01: Dual SDIO 0b10: Quad SDIO 0b11: Reserved...
Page 144: Table 7-19. Spixf Mode Data Register
MAX32650–MAX32652 User Guide Table 7-19. SPIXF Mode Data Register SPIXF Mode Data Register SPIXF_MODE_DATA [0x000C] Bits Name Access Reset Description 31:16 mdoe Mode Output Enable Output enable state for each corresponding data bit in SPIXF_MODE_DATA.mddata. 0: Output enable off, I/O is tristate stated.
Page 145: Table 7-22. Spixf Memory Security Control Register
MAX32650–MAX32652 User Guide SPIXF I/O Control Register SPIXF_IO_CTRL [0x001C] Bits Name Access Reset Description sck_ds SCK Drive Strength This bit controls the drive strength on the SCK pin. 0: Low Drive Strength. 1: Hi Drive Strength. Table 7-22. SPIXF Memory Security Control Register...
Page 146: Spi Execute-In-Place Ram
MAX32650–MAX32652 User Guide SPI Execute-in-Place RAM The SPI Execute-in-Place RAM Master Controller is an instantiation of the Quad SPI Interface with the following features: • Four SPI modes (mode 0, 1, 2, and 3) • Master mode only support •...
Page 147: Spixr Register Details
MAX32650–MAX32652 User Guide Offset Register Access Description [0x0008] SPIXR_CTRL2 SPIXR Transmit Packet Size Register [0x000C] SPIXR_CTRL3 SPIXR Static Configuration Register [0x0010] SPIXR_SS_TIME SPIXR Slave Select Timing Register [0x0014] SPIXR_BRG_CTRL SPIXR Master Baud Rate Register [0x001C] SPIXR_DMA SPIXR DMA Control Register...
Page 148: Table 7-27. Spixr Transmit Packet Size Register
MAX32650–MAX32652 User Guide SPIXR Master Signals Control Register SPIXR_CTRL1 [0x0004] Bits Name Access Reset Description start R/W1AC Master Start Data Transmission Set this field to 1 to start the transaction with the slave device. Hardware automatically clears this field after the transaction is started.
Page 149: Table 7-28. Spixr Static Configuration Register
MAX32650–MAX32652 User Guide Table 7-28. SPIXR Static Configuration Register SPIXR Static Configuration Register SPIXR_CTRL3 [0x000C] Bits Name Access Reset Description 31:27 Reserved for Future Use Do not modify this field. sspol Slave Select Polarity 0: SS is active low 1: SS is active high...
Page 150: Table 7-29. Spixr Slave Select Timing Register
MAX32650–MAX32652 User Guide Table 7-29. SPIXR Slave Select Timing Register SPIXR Slave Select Timing Register SPIXR_SS_TIME [0x0010] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 ssinact SS Inactive Clock Delay This is the time SS is inactive, and the bus is inactive between character transmission.
Page 151 MAX32650–MAX32652 User Guide SPIXR Master Baud Rate Generator Register SPIXR_BRG_CTRL [0x0014] Bits Name Access Reset Description 19:16 scale System Clock to SPIXR Clock Scale Factor Scales the system clock by 2scale to generate the internal SPIXR peripheral clock. SYS_CLK SPIXR_CLK scale ��...
Page 152: Table 7-31. Spixr Dma Control Register
MAX32650–MAX32652 User Guide Table 7-31. SPIXR DMA Control Register SPIXR DMA Control Register SPIXR_DMA [0x001C] Bits Name Access Reset Description rx_dma_en RX DMA Enable Enable or disable the RX DMA. 0: RX DMA is disabled. Any pending DMA requests are cleared...
Page 153: Table 7-32. Spixr Interrupt Status Flag Register
MAX32650–MAX32652 User Guide SPIXR DMA Control Register SPIXR_DMA [0x001C] Bits Name Access Reset Description tx_fifo_level 0x10 TX FIFO Threshold Level When the TX FIFO has fewer than this field, a DMA request is triggered and the SPIXR_INT_FL.tx_level interrupt flag is set.
Page 154: Table 7-33. Spixr Interrupt Enable Register
MAX32650–MAX32652 User Guide SPIXR Interrupt Status Flag Register SPIXR_INT_FL [0x0020] Bits Name Access Reset Description tx_level R/W1C TX FIFO Threshold Level Crossed Flag Set when the TX FIFO is less than the value in SPIXR_DMA.tx_fifo_level. Table 7-33. SPIXR Interrupt Enable Register...
Page 155: Table 7-34. Spixr Wakeup Flag Register
MAX32650–MAX32652 User Guide SPIXR Interrupt Enable Register SPIXR_INT_EN [0x0024] Bits Name Access Reset Description rx_level RX FIFO Threshold Level Crossed Interrupt Enable 1: Interrupt enabled 0: Interrupt disabled tx_empty TX FIFO Empty Interrupt Enable 1: Interrupt enabled 0: Interrupt disabled...
Page 156: Table 7-36. Spixr Active Status Register
MAX32650–MAX32652 User Guide SPIXR Wakeup Enable Register SPIXR_WAKE_EN [0x002C] Bits Name Access Reset Description tx_level Wake on TX FIFO Threshold Level Crossed Enable Set to 1 to wake up the device when this RX FIFO is full. 0: Wakeup Disabled for this condition.
Page 157: External Memory Cache Controller (Emcc)
MAX32650–MAX32652 User Guide External Memory Cache Controller (EMCC) The External Memory Cache Controller is a AHB block that has multiple interfaces. The address and data interface is connected to the AHB and the EMCC register interface is connected via the APB.
Page 158: Emcc Register Details
MAX32650–MAX32652 User Guide Table 7-38: External Memory Cache Controller Register Addresses and Descriptions Offset Register Name Access Description [0x0000] EMCC_CACHE_ID Cache ID Register [0x0004] EMCC_MEM_SIZE Cache Memory Size Register [0x0100] EMCC_CACHE_CTRL Cache Control Register [0x0700] EMCC_INVALIDATE Invalidate Register EMCC Register Details...
Page 159: Table 7-42: Emcc Invalidate Register
MAX32650–MAX32652 User Guide EMCC_CACHE_CTRL EMCC Cache Control Register [0x0100] Bits Name Access Reset Description ready Ready This field is cleared by hardware anytime the cache as a whole is invalidated (including a Power-On Reset event). Hardware automatically sets this field to 1 when the invalidate operation is complete and the cache is ready.
Page 160: Secure Digital Host Controller
Details of the SD communication and protocol are not part of the scope of this document. The MAX32650–MAX32652 SDHC only supports a single embedded SD card. SD memory card and SDIO card specifications are available at https://www.sdcard.org.
Page 161: Signals And Pins
MAX32650–MAX32652 User Guide Figure 7-6: SDHC Block Diagram Signals and Pins The MAX32650–MAX32652 SDHC pin mapping for the 144-pin TQFP and 96-WLP mapped to the SD Host Controller Standard Specification Version 3.0 are shown in Table 7-43, below. Table 7-43: SDHC Alternate Function Mapping to SDHC Specification Pin Names MAX32650–...
Page 162: Sdhc Peripheral Clock Selection
MAX32650–MAX32652 User Guide MAX32650– MAX32650– MAX32650– MAX32652 MAX32652 MAX32652 MAX32650– SDHC MAX32652 Alternate Function 144-TQFP 96-WLP Specification Alternate Function Number Pin Name Pin Name Pin Name Direction Signal Description SDHC_CMD P1.0 P1.0 SD bus command signal. SDHC_DAT0 P1.4 P1.4 DAT[0] SD data bus bit 0.
Page 163: Figure 7-7: Sd Bus Protocol - No Response And No Data Operations
MAX32650–MAX32652 User Guide Figure 7-7, Figure 7-8, and Figure 7-9 show the basic types of SD operations as described in the Physical Layer Simplified Specification Version 6.00 from the SD Card Association. Figure 7-7: SD Bus Protocol - No Response and No Data Operations...
Page 164: Sd Command Generation
MAX32650–MAX32652 User Guide Figure 7-9: SD Bus Protocol - Multi Block Write Operation SD Command Generation Table 7-44 shows the registers required for three transaction types: SDMA generated transactions, ADMA generated transactions, and CPU transactions (includes data transfers and Non-DAT transfers). When initiating a transaction, you...
Page 165 MAX32650–MAX32652 User Guide Offset Register Name Description [0x0008] SDHC_ARG_1 Argument 1 register [0x000C] SDHC_TRANS Transfer Mode register [0x000E] SDHC_CMD Command register [0x0010] SDHC_RESP_0 Response register 0 [0x0012] SDHC_RESP_1 Response register 1 [0x0014] SDHC_RESP_2 Response register 2 [0x0016] SDHC_RESP_3 Response register 3...
Page 166: Sdhc Register Details
MAX32650–MAX32652 User Guide Offset Register Name Description [0x0060] SDHC_PRESET_0 Preset Value for Initialization [0x0062] SDHC_PRESET_1 Preset Value for Default Speed [0x0064] SDHC_PRESET_2 Preset Value for High Speed [0x0066] SDHC_PRESET_3 Preset Value for SDR12 [0x0068] SDHC_PRESET_4 Preset Value for SDR25 [0x006A]...
Page 167 MAX32650–MAX32652 User Guide SDMA Block Size Register SDHC_BLK_SIZE [0x0004] Bits Name Access Reset Description 14:12 host_buf Host SDMA Buffer Size This field specifies the size of the contiguous buffer in the system memory for SDMA transfers. SDMA transfers larger than this buffer generates a SDHC DMA interrupt (SDHC_INT_STAT.dma) when the transfer reaches the host_buf size boundary.
Page 168: Table 7-48: Sdhc Sdma Block Count Register
MAX32650–MAX32652 User Guide Table 7-48: SDHC SDMA Block Count Register SDMA Block Count Register SDHC_BLK_CNT [0x0006] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. 15:0 trans 0x0200 Current Transfer Block Count Set to the total number of blocks to transfer prior to a block transfer operation. Set the Block Count Enable (SDHC_TRANS.blk_cnt_en) bit to 1 for a block transfer.
Page 169 MAX32650–MAX32652 User Guide SDMA Transfer Mode Register SDHC_TRANS [0x000C] Bits Name Access Reset Description multi Multi/Single Block Select Used for DAT line transfers and multiple-block commands. For all other commands, set this bit to 0. 1: Multiple-block or DAT line transfer...
Page 170: Table 7-51: Summary Of How Register Settings Determine Type Of Data Transfer
MAX32650–MAX32652 User Guide Table 7-51: Summary of how register settings determine type of data transfer Multi/Single Block Select Block Count Enable Block Count Function SDHC_TRANS.multi SDHC_TRANS.blk_cnt_en SDHC_BLK_CNT.trans N.A. N.A. Single transfer N.A. Infinite transfer ≠0 Multiple transfer Stop Multiple transfer...
Page 171: Table 7-53: Relationship Between Parameters And The Name Of Response Type
MAX32650–MAX32652 User Guide Command Register SDHC_CMD [0x000E] Bits Name Access Reset Description resp_type Response Type Select 0b00: No Response 0b01: Response Length 136 0b10: Response Length 48 0b11: Response Length 48, and check if busy after response Table 7-53: Relationship between Parameters and the Name of Response Type...
Page 172: Table 7-56: Sdhc Response 2 Register
Table 7-62 shows the mapping from the Response Registers to the SD Host Controller Standard Specification REP[127:0] notation for the MAX32650–MAX32652. Table 7-63 shows the SD types of response mapped to the MAX32650–MAX32652 Response registers. Table 7-57: SDHC Response 3 Register...
Page 173: Table 7-60: Sdhc Response 6 Register
MAX32650–MAX32652 User Guide Table 7-60: SDHC Response 6 Register Response 6 Register SDHC_RESP_6 [0x001C] Bits Name Access Reset Description 15:0 cmd_resp Response Register 6 Response 7 to Response 0 registers are referenced as a contiguous, single register in the SD Host Controller Spec V3.0.
Page 174: Table 7-64: Sdhc Buffer Data Port Register
MAX32650–MAX32652 User Guide Table 7-64: SDHC Buffer Data Port Register Buffer Data Port Register SDHC_BUFFER [0x0020] Bits Name Access Reset Description 31:0 data Buffer Data Pointer to the SDHC internal data buffer. Table 7-65: SDHC Present State Register Present State Register...
Page 175 MAX32650–MAX32652 User Guide Present State Register SDHC_PRESENT [0x0024] Bits Name Access Reset Description buffer_read Buffer Read Enable If this bit reads 1, then data is available in the buffer for non-DMA transfers. This bit is cleared when all available block data is read from the buffer. This bit transitions from 0 to 1 when block data is ready in the buffer resulting in a SDHC_IRQ interrupt, if enabled, with the SDHC_INT_STAT.buffer_rd_ready flag set.
Page 176: Table 7-66: Sdhc Host Control 1 Register
1. 1: Card Inserted 0: No card inserted ext_data_transfer_width Extended Data Transfer Width Extended data transfer width is not supported on the MAX32650–MAX32652. Always reads 0. 0: Bus width is selected by SHDC_HOST_CN_1.data_transfer_width field Maxim Integrated Page 176 of 411...
Page 177: Table 7-67: Sdhc Power Control Register
MAX32650–MAX32652 User Guide Host Control 1 Register SDHC_HOST_CN_1 [0x0028] Bits Name Access Reset Description dma_select DMA Select Sets the DMA mode. 0b00: SDMA mode 0b01: Reserved 0b10: 32-bit address ADMA2 mode 0b11: Reserved hs_en High Speed Enable 1: High-speed mode...
Page 178 MAX32650–MAX32652 User Guide Block Gap Control Register SDHC_BLK_GAP [0x002A] Bits Name Access Reset Description intr Interrupt at Block Gap Setting this bit to 1 enables interrupt detection at the block gap for a multiple block transfer. 1: Enabled 0: Disabled Note: This bit is only valid if SDHC_PWR.data_transfer_width=1 (4-bit mode).
Page 179: Table 7-69: Sdhc Wakeup Control Register
MAX32650–MAX32652 User Guide Block Gap Control Register SDHC_BLK_GAP [0x002A] Bits Name Access Reset Description stop Stop At Block Gap Request Setting this bit stops executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. This bit must remain set to 1 until the SDHC_INT_STAT.trans_comp bit is set to 1.
Page 180: Table 7-70: Sdhc Clock Control Register
MAX32650–MAX32652 User Guide Table 7-70: SDHC Clock Control Register Clock Control Register SDHC_CLK_CN [0x002C] Bits Name Access Reset Description 15:8 sdclk_freq_sel SDCLK Frequency Select Selects the SD Clock Frequency output on the SDHC_CLK pin. The SD Clock Frequency Select is a total of 10bits. The divisors shown below consist of the upper_sdclk_freq_sel bits as bits 9:8, and the sdclk_freq_sel bits as bits 7:0 of the divisor.
Page 181: Table 7-71: Sdhc Timeout Control Register
MAX32650–MAX32652 User Guide Clock Control Register SDHC_CLK_CN [0x002C] Bits Name Access Reset Description internal_clk_stable Internal Clock Stable This bit is set to 1 when the internal clock is stable. Note: The internal clock must be enabled (SDHC_CLK_CN.internal_clk_en = 1) before this field is used.
Page 182 MAX32650–MAX32652 User Guide Software Reset Register SDHC_SW_RESET [0x002F] Bits Name Access Reset Description reset_dat RWAC Software Reset for DAT Line 1: Reset 0: Ready The following registers and fields are cleared/initialized when this bit is set: Register Field SDHC_BUFFER data...
Page 183: Table 7-73: Sdhc Normal Interrupt Status Register
MAX32650–MAX32652 User Guide 7.5.8.1 Normal Interrupt Status Register The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not. An interrupt is generated when the Normal Interrupt Signal Enable is enabled, and at least one of the status bits is set to 1. Writing 1 to a bit of the RW1C attribute clears it.
Page 184 MAX32650–MAX32652 User Guide Normal Interrupt Status Register SDHC_INT_STAT [0x0030] Bits Name Access Reset Description buff_rd_ready RW1C Buffer Read Ready Set if the Buffer Read Enable field in the Present State register (SDHC_PRESENT.buff_rd_ready) changes from 0 to 1. 1: Ready to read buffer...
Page 185: Table 7-74: Transfer Complete And Data Timeout Error Priority And Status
MAX32650–MAX32652 User Guide Table 7-74: Transfer Complete and Data Timeout Error Priority and Status Transfer Complete Data Timeout Error Status SDHC_INT_STAT.trans_comp SDHC_ER_INT_STAT.data_to Interrupted by another event Timeout occurred during transfer N.A. Command execution complete Table 7-75: Command Complete and Command Timeout Error Priority and Status...
Page 186 CMD12, but also when Auto CMD12 is not executed due to a previous command error. current_limit R/W1C Current Limit Error Not supported on MAX32650–MAX32652 data_end_bit R/W1C Data End Bit Error Set if a 0 is detected at the end bit position of read data that uses the DAT line or the end-bit position of the CRC status.
Page 187: Table 7-77: Sdhc Normal Interrupt Status Register
MAX32650–MAX32652 User Guide Error Interrupt Status Register SDHC_ER_INT_STAT [0x0032] Bits Name Access Reset Description cmd_crc R/W1C Command CRC Error Set for the following cases: 7) If a response is returned, and the Command Timeout Error is set to 0, then this error flag is set if a CRT error is detected in the Command Response.
Page 188: Table 7-78: Sdhc Error Interrupt Status Enable Register
MAX32650–MAX32652 User Guide Normal Interrupt Status Enable Register SDHC_INT_EN [0x0034] Bits Name Access Reset Description buffer_rd Buffer Read Ready Status Enable Set to enable Buffer Read Ready status. 1: Enabled 0: Disabled buffer_wr Buffer Write Ready Status Enable Set to enable Buffer Write Ready status.
Page 189: Table 7-79: Sdhc Normal Interrupt Signal Enable Register
MAX32650–MAX32652 User Guide Error Interrupt Status Enable Register SDHC_ER_INT_EN [0x0036] Bits Name Access Reset Description auto_cmd_12 Auto CMD12 Error Status Interrupt Enable 1: Enabled 0: Disabled Reserved for Future Use Do not modify this field. data_end_bit Data End Bit Error Status Interrupt Enable...
Page 190: Table 7-80: Sdhc Error Interrupt Signal Enable Register
MAX32650–MAX32652 User Guide Normal Interrupt Signal Enable Register SDHC_INT_SIGNAL [0x0038] Bits Name Access Reset Description card_insert Card Insertion Signal Enable 1: Enabled 0: Disabled buffer_rd Buffer Read Ready Signal Enable 1: Enabled 0: Disabled buffer_wr Buffer Write Ready Signal Enable...
Page 191: Table 7-81: Sdhc Auto Cmd Error Status Register
MAX32650–MAX32652 User Guide Error Interrupt Signal Enable Register SDHC_ER_INT_SIGNAL [0x003A] Bits Name Access Reset Description current_limit Current Limit Error Signal Enable 1: Enabled 0: Disabled data_end_bit Data End Bit Error Signal Enable 1: Enabled 0: Disabled data_crc Data CRC Error Signal Enable...
Page 192: Table 7-82: Sdhc Host Control 2 Register
1: The Host Controller hardware sets the above fields using the Preset Value register settings. asynch_int Asynchronous Interrupt Enable Always reads 0. Asynchronous Interrupt Enable is not supported by the MAX32650–MAX32652. Writes to this field have no effect. 13:8 Reserved for Future Use Do not modify this field. Maxim Integrated...
Page 193: Table 7-83: Sdhc Capabilities Register 0
MAX32650–MAX32652 User Guide Host Control 2 Register SDHC_HOST_CN_2 [0x003E] Bits Name Access Reset Description sampling_clk Sampling Clock Select This field is automatically set by hardware when Execute Tuning (SDHC_HOST_CN_2. execute) is cleared. 0: The fixed clock is used to sample data 1: The tuned clock is used to sample data Note: The Card Driver cannot write 1 to this bit.
Page 194 MAX32650–MAX32652 User Guide Capabilities Register 0 SDHC_CFG_0 [0x0040] Bits Name Access Reset Description 64_bit_sys_bus 64-bit System Bus Support 0: 64-bit system bus not supported Reserved for Future Use 1_8v Voltage Support 1.8V 1: 1.8V supported 3_0v Voltage Support 3.0V 1: 3.0V supported 3_3v Voltage Support 3.3V...
Page 195: Table 7-84: Sdhc Capabilities Register 1
MAX32650–MAX32652 User Guide Table 7-84: SDHC Capabilities Register 1 Capabilities Register 1 SDHC_CFG_1 [0x0044] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 clk_multi Clock Multiplier Always reads 0x00. 0: Programmable clock generation is not supported.
Page 196: Table 7-85: Sdhc Maximum Current Capabilities Register
MAX32650–MAX32652 User Guide Table 7-85: SDHC Maximum Current Capabilities Register Maximum Current Capabilities Register SDHC_MAX_CURR_CFG [0x0048] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 1_8v Maximum Current for 1.8V 0x00: System dependent...
Page 197: Table 7-87: Sdhc Force Event Register For Error Interrupt Status
MAX32650–MAX32652 User Guide Table 7-87: SDHC Force Event Register for Error Interrupt Status Force Event Register for Error Interrupt Status SDHC_FORCE_EVENT_INT_STAT [0x0052] Bits Name Access Reset Description 15:12 stat_vendor Force Event for Vendor Specific Error Status 1: Interrupt is generated...
Page 198 MAX32650–MAX32652 User Guide ADMA Error Status Register SDHC_ADMA_ER [0x0054] Bits Name Access Reset Description len_mismatch ADMA Length Mismatch Error This error occurs in the following two cases: 1) When setting Block Count Enable, the total data length specified by the Descriptor Table is different from that specified by the Block Count and Block Length fields.
Page 199: Table 7-89: Sdhc Adma System Address Register 0
MAX32650–MAX32652 User Guide Table 7-89: SDHC ADMA System Address Register 0 SDHC_ADMA_ADDR_0 ADMA System Address Register 0 [0x0058] Bits Name Access Reset Description 31:0 addr ADMA System Address 0 Holds the byte address of the executing command for the Descriptor Table. The Host Driver must set this address, made up of <SDHC_ADMA_ADDR_1>:<SDHC_ADMA_ADDR_0>, to the start address of the...
Page 200: Table 7-92: Preset Value Register Selection Conditions
MAX32650–MAX32652 User Guide Offset Preset Value Registers Signal Voltage [0x0064] Preset Value for High Speed 3.3V [0x0066] Preset Value for SDR12 1.8V [0x0068] Preset Value for SDR25 1.8V [0x006A] Preset Value for SDR50 1.8V [0x006C] Preset Value for SDR104 1.8V...
Page 201: Table 7-94: Sdhc Slot Interrupt Status Register
Interrupt Signals Indicates the logical OR of Interrupt Signal and Wakeup Signal for the single slot. Only one slot is defined for the MAX32650–MAX32652, slot 0. Reset by POR and by software reset for all (SDHC_SW_RESET.reset_all). Table 7-95: SDHC Host Controller Version Register...
Page 202: Hyperbus/Xccela High Speed Memory Controller Interface
The HyperBus and Xccela Memory Controller (HBMC) interface is a high-speed, low-pin count interface for connecting the MAX32650–MAX32652 to one or more compatible external memory devices. The external HyperBus or Xccela Bus memory device is mapped into the MAX32650–MAX32652’s memory space enabling direct code execution, data storage or both.
Page 203: Hyperbus/Xccela Signal Descriptions
CE0# GPIO1.11 Output Each external device requires a dedicated chip select line. The MAX32650–MAX32652 initiates a bus transaction by transitioning a chip select line from a high state (deselected) to a low state (selected). When the MAX32650–MAX32652 completes the bus transaction, the HBMC drives...
Page 204: Reading And Writing To A Slave Device From Firmware
MAX32650–MAX32652 User Guide Reading and Writing to a Slave Device from Firmware Reading and writing with external memory devices is done through two memory-mapped regions of this microcontroller’s memory. Configure the memory-mapped addresses using the Memory Base Address registers, where HBMC_MBR0 configures the memory mapped region for Port0 and HBMC_MBR1 configures the memory mapped region for Port1.
Page 205: Hyperbus/Xccela Memory Transfers
MAX32650–MAX32652 User Guide HyperBus/Xccela Memory Transfers Using either a HyperBus or Xccela Bus memory requires configuration of the HBMC to communicate with the external memory device. The HBMC supports a maximum of two devices connected via the external I/O pins This HyperBus/Xccela Interface supports three memory types: •...
Page 206: External Memory Reset
MAX32650–MAX32652 User Guide Register space is used to access Device Identification (ID) and Configuration Registers (CR). These identify the characteristics of the accessed device and determine the slave-specific behavior of read and write transfers on the HyperBus interface. To write to configuration registers, first set register bit HBMC_MCR0.crt = 1 or HBMC_MCR1.crt = 1. After the configuration registers are written, set these bits back to 0 to access memory.
Page 207: Table 7-99: Hbmc Interrupt Enable Control Register
MAX32650–MAX32652 User Guide HBMC Status Register HBMC_STATUS [0x0000] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. wdecerr Write Address Error If this field is set a write address error orrcured. When set to 1 by hardware, the HBMC_INTFL.wdecerr interrupt flag is set to 1.
Page 208: Table 7-100: Hbmc Interrupt Status Flags Register
MAX32650–MAX32652 User Guide HBMC Interrupt Enable Control HBMC_INTEN [0x0004] Bits Name Access Reset Description errinte Error Interrupt Enable 0: No interrupt 1: Generate an interrupt when an error occurs Reserved for Future Use Do not modify this field. Table 7-100: HBMC Interrupt Status Flags Register...
Page 209: Table 7-102: Hbmc Memory Configuration 0 Registers
MAX32650–MAX32652 User Guide Reading and writing to the memory address space is device dependent. Refer to the slave device data sheet to determine how to use the memory space address map for that device. CS0# is the Port0 memory region chip select.
Page 210: Table 7-103: Hbmc Memory Timing Register 0
MAX32650–MAX32652 User Guide HBMC Memory Configuration Register 0 HBMC_MCR0 [0x0020] HBMC Memory Configuration Register 1 HBMC_MCR1 [0x0024] Bits Name Access Reset Description dev_type Memory Device Type 0: HyperFlash 1: Xccela PSRAM 2: HyperRAM 3: Reserved Reserved for Future Use Do not modify this field.
Page 211: Table 7-104: Latency Value Mapped To Hyperram And Xccela Psram Latency Cycles
MAX32650–MAX32652 User Guide HBMC Memory Timing Register 0 HBMC_MTR0 [0x0030] HBMC Memory Timing Register 1 HBMC_MTR1 [0x0034] Bits Name Access Reset Description latency RAM Latency Clock Cycles HyperRAM: Set this field to the external HyperRAM Read Latency Configuration Register value.
Page 212: Standard Dma Controller
MAX32650–MAX32652 User Guide Standard DMA Controller The Standard Direct Memory Access controller (DMAC) is a hardware feature that moves data blocks from peripheral to memory, memory to peripheral, and memory to memory. This hardware-based data movement reduces the processor load significantly.
Page 213: Dma Channel Arbitration And Dma Bursts
MAX32650–MAX32652 User Guide Register Description DMAn_SRC Source register DMAn_CNT Count register In addition, each channel has a set of reload registers shown in Table 8-2 that are used to chain DMA buffers when a count- to-zero (CTZ) condition occurs: Table 8-2: Channel Reload Registers...
Page 214: Dma Source And Destination Addressing
MAX32650–MAX32652 User Guide DMAn_CFG.reqsel determines which request is used to initiate a DMA burst. In the case of a memory-to-memory transfer, the channel is treated as always requesting DMA access. The DMAn_CFG.priority field determines the DMA channel priority. DMA Source and Destination Addressing...
Page 215: Data Movement From Source To Dma Fifo
MAX32650–MAX32652 User Guide Request Select Transfer Source Address SRCINC Destination Address DSTINC 0x2F SPI3 TX DMAn_SRC Programmable DMAn_DST 0x30 SPI_MSS TX DMAn_SRC Programmable DMAn_DST 0x31 USB TX1 DMAn_SRC Programmable USB IN Endpoint 1 0x32 USB TX2 DMAn_SRC Programmable USB IN Endpoint 2...
Page 216: Count-To-Zero Condition
MAX32650–MAX32652 User Guide Register/Bit Field Description Comments DMAn_CFG.dstinc Destination increment enable Increments DMAn_DST. Count-To-Zero Condition When an AHB channel burst completes, DMAC checks whether DMAn_CNT is decremented to 0. If it is, then a CTZ condition exists. At this point, there are two possible responses depending on the value of the DMAn_CFG.rlden bit: 5.
Page 217: Dma Interrupts
MAX32650–MAX32652 User Guide DMA Interrupts Enable interrupts for each channel by setting DMA_CN.chien. When an interrupt is pending, the corresponding DMA_INT.ipend = 1. The DMA_INT.ipend field is read-only, to clear the interrupt use the DMAn_ST register and write a 1 to the field that indicates the cause of the interrupt.
Page 218: Table 8-7: Standard Dma Registers, Offsets, Access And Descriptions
MAX32650–MAX32652 User Guide The DMAn_CFG.tosel field sets the time the 10-bit timer counts until generating an interrupt. The 10-bit timer resets whenever any of the following conditions occur: • The DMA request line programmed for the channel is activated. •...
Page 219: Table 8-8: Dma Control Register
MAX32650–MAX32652 User Guide 8.14 Standard DMA Register Details Table 8-8: DMA Control Register DMA_CN DMA Control Register [0x0000] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. 15:0 chien Channel Interrupt Enable Each bit in this field enables the corresponding channel interrupt.
Page 220: Table 8-11: Dman Channel Registers, Offsets, Access And Descriptions
MAX32650–MAX32652 User Guide Offset DMA Channel Access Description [0x0340] DMA12 DMA Channel 12 [0x0360] DMA13 DMA Channel 13 [0x0380] DMA14 DMA Channel 14 [0x0400] DMA15 DMA Channel 15 8.16 Standard DMA Channel Registers Each DMA channel has a set of associated Configuration Registers.
Page 221 MAX32650–MAX32652 User Guide DMA Configuration Register DMAn_CFG [0x0100] Bits Name Access Reset Description 28:24 brst Burst Size The number of bytes transferred into and out of the DMA FIFO in a single burst. 0b00000: 1 byte 0b00001: 2 bytes 0b00010: 3 bytes...
Page 222: Table 8-13: Dma Status Register
MAX32650–MAX32652 User Guide DMA Configuration Register DMAn_CFG [0x0100] Bits Name Access Reset Description 13:11 tosel Timeout Select Selects the number of pre-scaled clocks seen by the channel timer before a timeout condition is generated for this channel. 0: 3-4 1: 7-8...
Page 223: Table 8-14: Dma Source Register
MAX32650–MAX32652 User Guide DMA Status Register DMAn_ST [0x0104] Bits Name Access Reset Description bus_err R/W1C Bus Error If this bit reads 1, an AHB abort occurred and the channel was disabled by hardware. Write 1 to clear. 0: No error found...
Page 224: Table 8-15: Dma Destination Register
MAX32650–MAX32652 User Guide Table 8-15: DMA Destination Register DMA Destination Register DMAn_DST [0x010C] Bits Name Access Reset Description 31:0 Destination Device Address For peripheral transfers, the actual address field is either ignored or forced to zero because peripherals only have one location to read/write data based on the request select chosen.
Page 225: Table 8-19: Dma Count Reload Register
MAX32650–MAX32652 User Guide DMA Destination Reload Register DMAn_DST_RLD [0x0118] Bits Name Access Reset Description 30:0 dst_rld Destination Address Reload Value If DMAn_CFG.rlden = 1, then the value of this register is loaded into DMAn_DST upon a CTZ condition. Table 8-19: DMA Count Reload Register...
Page 226: Overview
MAX32650–MAX32652 User Guide CRC Engine Overview Cyclic Redundancy Checks (CRC) are commonly used for error detection. An n-bit CRC is capable of detecting the following types of errors: • Single-bit errors • Two-bit errors for block lengths less than 2 where k is the order of the longest irreducible factor of the polynomial •...
Page 227: Table 9-1: Common Crc Polynomials
MAX32650–MAX32652 User Guide CRC polynomials with good error detection properties should be irreducible (the polynomial should not be factorable). Therefore, the constant term �� or 1 should always be present, otherwise the polynomial would be factorable by ��. If the ��...
Page 228: Figure 9-1: Galois Field Crc And Lfsr Architecture
MAX32650–MAX32652 User Guide Figure 9-1: Galois Field CRC and LFSR Architecture Different polynomials generate different sequences of random data. Ideally, an n-bit polynomial generates a random �� sequence of 2 − 1 bits. Not all polynomials are maximal length. Some repeat before the theoretical maximum length of ��...
Page 229: Crc Register Details
MAX32650–MAX32652 User Guide Offset Register Name Access Description [0x0034] CRC_DATA_OUT1 CRC Data Output Register 0 (Bits 63:32) [0x0038] CRC_DATA_OUT2 CRC Data Output Register 0 (Bits 95:64) [0x003C] CRC_DATA_OUT3 CRC Data Output Register 0 (Bits 127:96) [0x0040] CRC_POLY CRC Polynomial Register...
Page 230 MAX32650–MAX32652 User Guide Crypto Control Register CRYPTO_CTRL [0x0000] Bits Name Access Reset Description flag_mode Done Flag Mode This field configures the access behavior of the CRYPTO_CTRL.dma_done field. When this field is set to 1, the CRYPTO_CTRL.dma_done field is Write 1 to Clear. When this field is 0, the CRYPTO_CTRL.dma_done field is unrestricted read/write.
Page 231: Table 9-3: Crc Control Register
MAX32650–MAX32652 User Guide Crypto Control Register CRYPTO_CTRL [0x0000] Bits Name Access Reset Description Reset Set this field to reset the CRC including the FIFOs. The CRYPTO_CTRL register is not reset. 0: Reset not active. 1: Reset the CRC Engine. Table 9-3: CRC Control Register...
Page 232: Table 9-7: Crc Data Input Registers
MAX32650–MAX32652 User Guide Table 9-7: CRC Data Input Registers CRC Data Input Register 0 CRC_DATA_IN0 [0x0020] CRC Data Input Register 1 CRC_DATA_IN1 [0x0024] CRC Data Input Register 2 CRC_DATA_IN2 [0x0028] CRC Data Input Register 3 CRC_DATA_IN3 [0x002C] Bits Name Access...
Page 233: Table 9-10: Crc Value Register
MAX32650–MAX32652 User Guide Table 9-10: CRC Value Register CRC Value Register CRC_VAL [0x0044] Bits Name Access Reset Description 31:0 CRC Value This is the state for the Galois Field. Output of the CRC calculation or the current state of the LFSR.
Page 234: Analog To Digital Converter
MAX32650–MAX32652 User Guide Analog to Digital Converter The Analog to Digital Converter (ADC) on the MAX32650–MAX32652 is a 10-bit sigma-delta ADC with a single-ended input multiplexer and an integrated reference generator. The multiplexer selects an input channel from either the external analog input signals (AIN0, AIN1, AIN2, and AIN3) or the internal power supply inputs.
Page 235: Figure 10-1: Analog To Digital Converter Block Diagram
MAX32650–MAX32652 User Guide Figure 10-1: Analog to Digital Converter Block Diagram 10.3 Clock Configuration The ADC clock, adcclk, is controlled by the GCR_PCKDIV.adcfrq register field. Configure this field a for the target ADC sample frequency. The maximum clock supported by the ADC is 8MHz. The divisor selection, GCR_PCLK_DIV.adcfrq, for the ADC depends on the peripheral clock.
Page 236: Table 10-1: Adc Clock Frequency And Adc Conversion Time (�� = 120��, ��හ
MAX32650–MAX32652 User Guide Equation 10-2: ADC Clock Frequency PCLK adcclk GCR_PCKDIV. adcfrq The GCR_PCKDIV.adcfrq register field setting must result in a value for f ≤ 8MHz as shown in Table 10-1 with the adcclk System Clock set as the 120MHz Relaxation Oscillator.
Page 237: Conversion
MAX32650–MAX32652 User Guide 10.5 Conversion After the power-up sequence is complete, the ADC is ready for data conversion. Complete the following steps to perform a data conversion. 1. Select the ADC input channel for the conversion by setting ADC_CTRL.ch_sel field. See ADC Channel Select for details.
Page 238: Table 10-2: Input And Reference Scale Support By Adc Input Channel
MAX32650–MAX32652 User Guide Table 10-2: Input and Reference Scale Support by ADC Input Channel ADC_CTRL ADC_CTRL ADC Channel input_scale ref_scale AIN4 AIN5 AIN6 AIN9 AIN10 AIN11 AIN12 Data Conversion Output Alignment The ADC outputs a total of 10-bits per conversion and stores the data in the DATA register LSB justified by default.
Page 239 MAX32650–MAX32652 User Guide Equation 10-5: ADC Data Equation for AIN4 and AIN5 �� _�� × ( 2 − 1 ) ��_�� = �� _�� Note: Refer to Table 10-2 for limitations. Equation 10-6: ADC Data Calculation AIN6 ��...
Page 240: Figure 10-2: Adc Limit Engine
MAX32650–MAX32652 User Guide Equation 10-11: ADC Data Calculation for AIN12 �� _�� × ( 2 − 1 ) ��_�� = �� _�� Note: Refer to Table 10-2 for limitations. Data Limits and Out of Range Interrupts Channel limits are implemented to minimize power consumption for power supply monitoring. The ADC includes four limit...
Page 241: Table 10-4. Adc Registers, Offsets And Descriptions
MAX32650–MAX32652 User Guide When a measurement is taken on the ADC, the limit engine determines if the channel measured matches one of the channels selected by the limit registers. If it does and the data converted is above or below the high or low limit, an interrupt flag is set resulting in an ADC interrupt if the interrupt is enabled.
Page 242: Table 10-5: Adc Control Register
MAX32650–MAX32652 User Guide 10.8 ADC Register Details Table 10-5: ADC Control Register ADC Control Register ADC_CTRL [0x0000] Bits Name Access Reset Description 31:18 Reserved for Future Use Do not modify this field. data_align ADC Data Alignment Selects the alignment of the 16-bit data conversion stored in the DATA register.
Page 243: Table 10-6: Adc Status Register
MAX32650–MAX32652 User Guide ADC Control Register ADC_CTRL [0x0000] Bits Name Access Reset Description chgpump_pwr ADC Charge Pump Setting this bit to 1 turns on the ADC charge pump required to perform ADC conversions. 0: Charge pump is powered off 1: Charge pump is powered on...
Page 244: Table 10-8: Adc Interrupt Control Register
MAX32650–MAX32652 User Guide Table 10-8: ADC Interrupt Control Register ADC Interrupt Control Register ADC_INTR [0x000C] Bits Name Access Reset Description 31:23 Reserved for Future Use Do not modify this field. pending ADC Interrupt Pending 0: No ADC interrupt is pending for an enabled interrupt condition.
Page 245 MAX32650–MAX32652 User Guide ADC Limit 0 Register ADC_LIMIT0 [0x0010] ADC Limit 1 Register ADC_LIMIT1 [0x0014] ADC Limit 2 Register ADC_LIMIT2 [0x0018] ADC Limit 3 Register ADC_LIMIT3 [0x001C] Bits Name Access Reset Description ch_hi_limit_en High Limit Monitoring Enable If set, then an ADC conversion that results in a value greater than the ch_high_limit field generates an ADC interrupt if the ADC high-limit interrupt is enabled.
Page 246: Color Lcd-Tft Controller
MAX32650–MAX32652 User Guide Color LCD-TFT Controller The Color LCD-TFT (CLCD) Controller provides a standard RGB (Red, Green, Blue) parallel interface and controls for horizontal and vertical synchronization, data enable, display enable and pixel clock for Liquid Crystal Displays (LCD) including Thin-Film-Transistor (TFT) panels with up to a 24-bit bus interface and Color STN panels with an 8-bit bus interface.
Page 247: Functional Overview
MAX32650–MAX32652 User Guide Color STN Support • 1 bpp, 2 colors • 2 bpp, 4 colors • 4 bpp, 16 colors • 8 bpp, 256 colors • RGB555 with 16 bpp, 1 unused bit • Typical Panel Resolutions  320 × 200, 320 × 240 ...
Page 248: Figure 11-1: Color Lcd Block Diagram
MAX32650–MAX32652 User Guide Figure 11-1: Color LCD Block Diagram AHB Master Interface and DMA FIFO Operation The AMBA master interface performs following functions 11.2.1.1 Frame Buffer Memory Addressing The CLCD’s AHB master interface burst copies frame data from external memory to the CLCD Frame FIFO (32 words x 32- bits) and increments the frame buffer address pointer to the next frame data address memory location.
Page 249: Table 11-1: Clcd Pins And Signal Description
The CLCD registers including the color palate registers are mapped to the AMBA APB interface enabling the application code to directly modify the CLCD configuration and color palette. 11.3 Signals and Pins The MAX32650–MAX32652 CLCD pin mapping for the 144-pin TQFP and 96-WLP. Table 11-1: CLCD Pins and Signal Description Alternate Function 144-TQFP...
Page 250: Pixel Process Engine
MAX32650–MAX32652 User Guide Perform the following steps to configure the GPIO for CLCD peripheral usage: 144-TQFP Package 1. Determine which of the GPIO port pins to use for the CLCD_CLK (P0.23 or P1.3) output pin and perform the following: Enable the alternate function for the CLCD_CLK signal output by setting either GPIO0[23] to 0 or GPIO1[3] to 0.
Page 251: Table 11-2: Clcd Data Format Little Endian Byte, Little Endian Pixel (Lblp)
MAX32650–MAX32652 User Guide Table 11-4 shows the data mapping for LBBP. The CLCD Frame Buffer registers point to the frame data to map to the display. The data should be constructed by the application code to match the format required by the display.
Page 252: Table 11-4: Clcd Data Format Little Endian Byte, Big Endian Pixel (Lbbp)
MAX32650–MAX32652 User Guide Table 11-4: CLCD Data Format Little Endian Byte, Big Endian Pixel (LBBP) DMA FIFO OUPUT BITS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 253: Table 11-6 Stn Data Output Format Per Clock Cycle
MAX32650–MAX32652 User Guide Table 11-6 STN Data Output Format per Clock Cycle Output Data Bits CLCD_CLK Period … … In STN single panel mode, output pins CLCD_R[7:0] are used for the 8-bit interface. In STN dual panel mode, CLCD_R[7:0] are used for the upper panel, and CLCD_G[7:0] are used for the lower panel.
Page 254: Table 11-8 Pclk To Pixel Clock Divide Ratios
MAX32650–MAX32652 User Guide Table 11-8 PCLK to PIXEL Clock Divide Ratios Display Type Pixels per Clock Divide Ratio 1(min) STN 8-bit color interface 2⅔ STN 4-bit color interface 1⅓ All the logic of the color LCD controller is synchronized with PCLK, except for the AMBA AHB interface, which is synchronized with HCLK.
Page 255: Table 11-9 Lcd Interface Register Offsets, Names And Descriptions
MAX32650–MAX32652 User Guide 11.9 Interrupt Operation The LCD controller provides four individually mask able interrupts: • DMA FIFO underflow: an underflow interrupt is asserted if an attempt is made to read the frame buffer FIFO when it is empty •...
Page 256: Table 11-11: Clcd Vertical Timing Register 0
MAX32650–MAX32652 User Guide CLCD Clock Register CLCD_CLK_CTRL [0x0000] Bits Name Access Reset Description clk_edge_sel Clock Edge Selection This field controls the clock edge that is used by the LCD panel to sample the data and signal lines. When set to 1, the CLCD_R[7:0], CLCD_G[7:0], and CLCD_B[7:0] data is valid on the falling edge of the CLCD_CLK.
Page 257: Table 11-12: Clcd Vertical Timing Register 1
MAX32650–MAX32652 User Guide CLCD Vertical Timing Register 0 CLCD_VTIM_0 [0x0004] Bits Name Access Reset Description 23:16 vbp_width Vertical Back Porch (VBP) Control This field sets the number of lines for the VBP from 0 lines to 255 lines. 0: 0 lines...
Page 258: Table 11-13: Clcd Horizontal Timing Register
MAX32650–MAX32652 User Guide Table 11-13: CLCD Horizontal Timing Register CLCD Horizontal Timing Register CLCD_HTIM [0x000C] Bits Name Access Reset Description 31:24 hbp_width Horizontal Back Porch (HBP) Width This field sets the number of lines for the HBP from 1 CLCD_CLK to 256 CLCD_CLKs.
Page 259 MAX32650–MAX32652 User Guide CLCD Control Register CLCD_CTRL [0x0010] Bits Name Access Reset Description lend_pol CLCD_LEND Polarity Selection This field sets the polarity of the line end signal output pin (CLCD_LEND). Setting this field to 0 sets CLCD_LEND active low and setting it to 1 results in an active high signal output.
Page 260: Table 11-15: Clcd Frame Buffer Register
MAX32650–MAX32652 User Guide CLCD Control Register CLCD_CTRL [0x0010] Bits Name Access Reset Description vci_sel Vertical Compare Interrupt (VCI) Source Select This field allows the selection of the interrupt source for Vertical Compare interrupts. 0: VCI on start of VSYNC 1: VCI on start of VBP...
Page 261: Table 11-17: Clcd Interrupt Status Register
MAX32650–MAX32652 User Guide Table 11-17: CLCD Interrupt Status Register CLCD Interrupt Status Register CLCD_INT_STAT [0x0024] Bits Name Access Reset Description 31:9 – Reserved for Future Use Do not modify this field. clcd_idle CLCD Idle Flag After the CLCD_CTRL.lcd_enable bit is set to 1 by the application, this bit is cleared by hardware to indicate the CLCD controller is sending the frame data to the display.
Page 262: Uart Frame Characters
MAX32650–MAX32652 User Guide UART The MAX32650–MAX32652 microcontroller provides three industry-standard UART ports which can communicate with external devices using standard serial communications protocols. The UARTs are full-duplex Universal Asynchronous Receiver/Transmitter (UART) serial ports. Each UART instance, UART0, UART1, and UART2, supports identical functionality and registers unless specifically noted otherwise.
Page 263: Uart Interrupts
Alternate Bit Rate Clock Source The MAX32650 includes a dedicated 7.3728MHz clock generator, which can be used for the UART bit rate clock generator if the selected System Clock does not meet the bit rate requirements of the application. In practice, the 7.3728MHz clock is ideal for use during low power mode where the Peripheral Clock is turned off for power conservation.
Page 264: Table 12-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps
MAX32650–MAX32652 User Guide Equation 12-3: Bit Rate Remainder Calculation ��_��. �� = ( �� − ��_��. �� ) × 128 Example Baud Rate Calculation: �� = 1,843,200 �� ( 1.8 �� ) �� = �� = 60 ��...
Page 265: Table 12-2: Uart Register Offsets, Names, Access And Descriptions
MAX32650–MAX32652 User Guide TX FIFO DMA Operation UARTn_DMA.txdma_lvl sets the number of entries (level) in the TX FIFO that will trigger a DMA transfer from system RAM to the TX FIFO. If the number of entries (level) in the TX FIFO falls below this value a TX DMA transfer is automatically triggered from System RAM to the TX FIFO.
Page 266: Table 12-3: Uart Control 0 Register
MAX32650–MAX32652 User Guide 12.9 UART Register Details Table 12-3: UART Control 0 Register UART Control 0 Register UARTn_CTRL0 [0x0000] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 to_cnt RX Timeout Frame Count If the RX FIFO contains data, a RX Timeout condition occurs if the time for the number of frames in this register passes without the FIFO receiving any new data.
Page 267: Table 12-4: Uart Control 1 Register
MAX32650–MAX32652 User Guide UART Control 0 Register UARTn_CTRL0 [0x0000] Bits Name Access Reset Description txflush R/W1O Transmit FIFO Flush Write 1 to flush the Transmit FIFO Cleared to 0 by hardware when flush is completed parity_lvl Parity Level Select 0: Parity is based on number of 0 bits in the character.
Page 268 MAX32650–MAX32652 User Guide UART Status Register UARTn_STAT [0x0008] Bits Name Access Reset Description rx_to RX Timeout This field is set to 1 when a receive timeout occurs. This field is set by hardware when the condition occurs and is automatically cleared when the condition is no longer valid.
Page 269: Table 12-6: Uart Interrupt Enable Register
MAX32650–MAX32652 User Guide Table 12-6: UART Interrupt Enable Register UART Interrupt Enable Register UARTn_INT_EN [0x000C] Bits Name Access Reset Description 31:10 Reserved for Future Use Do not modify this field. last_break Last Break Interrupt Enable When the UART receives a series of BREAK frames, this enables an interrupt when the last BREAK frame is received.
Page 270 MAX32650–MAX32652 User Guide UART Interrupt Flags Register UARTn_INT_FL [0x0010] Bits Name Access Reset Description last_break R/W1C Last Break Interrupt Flag When the UART receives a series of BREAK frames, this flag is set when the last BREAK frame is received. Write 1 to clear this field.
Page 271: Table 12-8: Uart Rate Integer Register
MAX32650–MAX32652 User Guide Table 12-8: UART Rate Integer Register UART Baud Rate Integer Register UARTn_BAUD0 [0x0014] Bits Name Access Reset Description 31:17 Reserved for Future Use Do not modify this field. 18:16 clkdiv Bit Rate Clock Divisor This field is used to divide the bit rate clock by the selected Clock Divider value.
Page 272: Table 12-11: Uart Dma Configuration Register
MAX32650–MAX32652 User Guide Table 12-11: UART DMA Configuration Register UART DMA Configuration Register UARTn_DMA [0x0020] Bits Name Access Reset Description 31:22 Reserved for Future Use Do not modify this field. 21:16 rxdma_lvl RX FIFO Level DMA Trigger If the RX FIFO level is greater than this value, the DMA channel transfers data from the RX FIFO into memory.
Page 273: I²C Master/Slave Features
MAX32650–MAX32652 User Guide C Master/Slave Serial Communications Peripheral The microcontroller integrates two I C peripherals, designated I2C0_ and I2C1_. The registers for each of the instances are identical with the same offset addresses for each register. For simplicity, I2Cn is used throughout this section to refer to both I C ports.
Page 274: Start And Stop Conditions
MAX32650–MAX32652 User Guide 13.3 C Transfer Protocol Operation The I C protocol operates over a two-wire bus: a clock circuit (SCL) and a data circuit (SDA). I C is a half-duplex protocol: only one device is allowed to transmit on the bus at a time. The data rate is not fixed and can dynamically operate up to 100kHz in Standard Mode and up to 400kHz in Fast Mode.
Page 275: Figure 13-1: I 2 C Write Data Transfer
MAX32650–MAX32652 User Guide A receiver can generate a NACK after a byte transfer if any of the following conditions occur: • No receiver is present on the bus with the transmitted address. In that case, no device will respond with an acknowledge signal.
Page 276: Figure 13-2: I 2 C Specification Min And Max Clock Parameters
MAX32650–MAX32652 User Guide I2C Interrupt Sources The I C Controller has a very flexible interrupt generator that generates an interrupt signal to the Interrupt Controller on any of several events. On recognizing the I C interrupt, firmware determines the cause of the interrupt by reading the I...
Page 277: Transmit And Receive Fifos
MAX32650–MAX32652 User Guide and are compliant with the clock synchronization requirements of the I C specification. Clock synchronization is automatic, and no additional programming is required. Transmit and Receive FIFOs Each I C master/slave has one 8-byte deep transmit FIFO (TX FIFO) and one 8-byte deep receive FIFO (RX FIFO) that reduces processor overhead.
Page 278: Table 13-1: I 2 C Address Byte Format
MAX32650–MAX32652 User Guide 13.11 I C Bus Timeout The Timeout register bit field I2Cn_TIMEOUT.to is used to detect if a bus error has occurred. The Timeout register configures the timeout value from the following equation: Equation 13-1: I C Timeout Maximum ��...
Page 279: Interactive Receive Mode
MAX32650–MAX32652 User Guide the slave. If the operation is a read, it is followed by a repeated START. Firmware then writes the 10-bit address again with a 1 for the R/W bit. This I C then starts receiving data from the slave device.
Page 280 MAX32650–MAX32652 User Guide After deciding on the ACK/NACK response, write a 1 to clear I2Cn_INT_FL0.irxmi to 0. This releases SCL and sends an I2Cn_CTRL0.ack value onto SDA. For both master and slave operations, SCL is released only after the necessary SCL low time requirement has been satisfied, to conform with tsu;dat timing.
Page 281 MAX32650–MAX32652 User Guide automatically cleared to 0 as soon as the master begins a RESTART condition. The reception of a STOP condition clears any pending RESTART. I2Cn_MSTR_MODE.start is automatically cleared to 0 after the master has completed a transaction and sent a STOP condition.
Page 282: Figure 13-3: I 2 C Clock Period
MAX32650–MAX32652 User Guide 13.18 SCL Clock Generation The master generates the I C clock on the SCL line. The I C peripheral clock, �� is equal to �� 2��_�� Figure 13-3: I C Clock Period I2C_CLK_HI I2C_CLK_LO I2C_CLK_HI IH_MIN...
Page 283: Table 13-2: I2C Registers
MAX32650–MAX32652 User Guide The required steps for implementing TX FIFO Preloading in an application are as follow: 1. Set I2Cn_TX_CTRL1.txrdy to 0 2. Enable TX FIFO Preloading by setting I2Cn_TXCTRL0.txpreld to 1. 3. If the TX FIFO Lockout Flag (I2Cn_INT_FL0.txloi) is set to 1, write 1 to clear the flag and enable writes to the TX FIFO.
Page 284: Table 13-3: I C Control 0 Register
MAX32650–MAX32652 User Guide Offset Register Name Access Description [0x0040] I2Cn_TIMEOUT C Timeout Register [0x0044] I2Cn_SLV_ADDR C Slave Address Register [0x0048] I2Cn_DMA C DMA Enable Register 13.22 I C Register Details Table 13-3: I C Control 0 Register C Control 0 Register...
Page 285: Table 13-4: I C Status Register
MAX32650–MAX32652 User Guide C Control 0 Register I2Cn_CTRL0 [0x0000] Bits Name Access Reset Description sdao SDA Pin Control Set the state of the SDA hardware pin (actively pull low or float). 0: Pull SDA Low 1: Release SDA Note: Only valid when I2Cn_CTRL0.swoe=1...
Page 286: Table 13-5: I C Interrupt Flag 0 Register
MAX32650–MAX32652 User Guide C Status Register I2Cn_STAT [0x0004] Bits Name Access Reset Description ckmd SCL Drive Status This field indicates if an external device is behaving as a master by actively driving the SCL line. 0: External device not driving SCL...
Page 287 MAX32650–MAX32652 User Guide C Interrupt Flag 0 Register I2Cn_INT_FL0 [0x0008] Bits Name Access Reset Description strteri R/W1C Out of Sequence START Interrupt Flag This flag is set if a START condition occurs on the I C Bus out of expected sequence.
Page 288: Table 13-6: I C Interrupt Enable 0 Register
MAX32650–MAX32652 User Guide C Interrupt Flag 0 Register I2Cn_INT_FL0 [0x0008] Bits Name Access Reset Description rxthi RX FIFO Threshold Level Interrupt Flag This field is set by hardware if the number of bytes in the Receive FIFO is greater than or equal top the Receive FIFO threshold level. This field is automatically cleared when the RX FIFO contains fewer bytes than the RX threshold setting.
Page 289 MAX32650–MAX32652 User Guide C Interrupt Enable 0 Register I2Cn_INT_EN0 [0x000C] Bits Name Access Reset Description dnrerie Slave Mode Do Not Respond Interrupt Enable Set this field to enable events in Slave Mode when the Do Not Respond condition occurs. 0: Interrupt disabled.
Page 290: Table 13-7: I 2 C Interrupt Flag 1 Register
MAX32650–MAX32652 User Guide C Interrupt Enable 0 Register I2Cn_INT_EN0 [0x000C] Bits Name Access Reset Description irxmie Interactive Receive Interrupt Enable Set this field to enable the interactive receive interrupt event. 0: Interrupt disabled. 1: Interrupt enabled. doneie Transfer Complete Interrupt Enable Set this field to enable the transfer complete interrupt event.
Page 291: Table 13-9: I C Fifo Length Register
MAX32650–MAX32652 User Guide Table 13-9: I C FIFO Length Register I2Cn_FIFO_LEN C FIFO Length Register [0x0018] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. 15:8 txlen TX FIFO Length Returns the length of the TX FIFO.
Page 292: Table 13-11: I C Receive Control 1 Register
MAX32650–MAX32652 User Guide Table 13-11: I C Receive Control 1 Register C Receive Control 1 Register I2Cn_RX_CTRL1 [0x0020] Bits Name Access Reset Description 31:12 Reserved for Future Use Do not modify this field. 11:8 rxfifo RX FIFO Byte Count Status Returns the number of bytes currently in the RX FIFO.
Page 293: Table 13-13: I C Transmit Control 1 Register
MAX32650–MAX32652 User Guide C Transmit Control Register 0 I2Cn_TX_CTRL0 [0x0024] Bits Name Access Reset Description txpreld TX FIFO Preload Mode Enable 0: Normal operation. An address match in Slave Mode, or a General Call address match, will flush and lock the TX FIFO so it cannot be written and set I2Cn_INT_FL0.txloi.
Page 294: Table 13-15: I C Master Mode Control Register
MAX32650–MAX32652 User Guide Table 13-15: I C Master Mode Control Register C Master Mode Control Register I2Cn_MSTR_MODE [0x0030] Bits Name Access Reset Description 31:8 Reserved for Future Use Do not modify this field. Slave Extended Addressing 0: Send a 7-bit address to the slave...
Page 295: Table 13-18: I C Timeout Register
MAX32650–MAX32652 User Guide C Clock High Control Register I2Cn_CLK_HI [0x0038] Bits Name Access Reset Description scl_hi Clock High Time In Master Mode, this configures the SCL high time. = 1 �� × ( ��_ℎ�� + 1 ) �� ⁄ ��_��...
Page 296: Table 13-20: I C Dma Register
MAX32650–MAX32652 User Guide Table 13-20: I C DMA Register C DMA Register I2Cn_DMA [0x0048] Bits Name Access Reset Description 31:2 Reserved for Future Use Do not modify this field. rxen RX DMA Channel Enable 0: Disable RX DMA channel 1: Enable RX DMA channel...
Page 297: Pulse Train Engine
MAX32650–MAX32652 User Guide Pulse Train Engine The Pulse Train Engine includes 16 independent pulse train engines, designated PT0 to PT15. Each pulse train engine can either operate in Square Wave mode which generates a continuous 50% duty-cycle square wave, or Pulse Train mode which generates a continuous programmed bit pattern from 2- to 32-bits in length.
Page 298 MAX32650–MAX32652 User Guide pattern bit length.) PTn_RATE_LENGTH.mode =0 (PTn bit length configured for Pulse Train mode, 32-bit pattern) If in Pulse Train Mode, Set the Bit Pattern If an output is set to Pulse Train mode, then configure a custom bit pattern from 2-bits to 32-bits in length in the 32-bit register PTn_TRAIN.
Page 299: Enabling And Disabling A Pulse Train Output
MAX32650–MAX32652 User Guide Each pulse train engine can be configured to perform an Automatic Restart when it detects a Stop Event from one or two pulse trains. • If PTn_RESTART.on_pt_n_loop_exit = 1, then pulse train engine n automatically restarts when it detects a Stop Event from pulse train x, where x is the value in the 5-bit field PTn_RESTART.pt_n_select.
Page 300: Table 14-1: Pulse Train Engine Registers
MAX32650–MAX32652 User Guide Bit banding is not supported for the PTG_ENABLE, PTG_SAFE_EN, and PTG_SAFE_DIS registers and can have unpredictable results. 14.5 Pulse Train Halt and Disable Once a pulse train engine is enabled and running, it continues to run until one of the following events stops the output:...
Page 301 MAX32650–MAX32652 User Guide PT Global Enable/Disable Control PTG_ENABLE [0x0000] Bits Name Access Reset Description enable_pt15 Enable/Disable Control for PT15 1: Enable Pulse Train 0: Disable Pulse Train Note: Manually disabling an active pulse train immediately halts the PT output and does not generate a Stop Event.
Page 302: Table 14-3: Pulse Train Engine Resync Register
MAX32650–MAX32652 User Guide PT Global Enable/Disable Control PTG_ENABLE [0x0000] Bits Name Access Reset Description enable_pt6 Enable/Disable Control for PT6 1: Enable Pulse Train 0: Disable Pulse Train Note: Manually disabling an active pulse train immediately halts the PT output and does not generate a Stop Event.
Page 303 MAX32650–MAX32652 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Name Access Reset Description pt15 Resync Control for PT15 Write 1 to reset the output of the Pulse Train. For Pulse Train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 304 MAX32650–MAX32652 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Name Access Reset Description Resync Control for PT9 Write 1 to reset the output of the Pulse Train. For Pulse Train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 305: Table 14-4:Pulse Train Engine Stopped Interrupt Flag Register
MAX32650–MAX32652 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Name Access Reset Description Resync Control for PT3 Write 1 to reset the output of the Pulse Train. For Pulse Train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 306 MAX32650–MAX32652 User Guide PT Stopped Interrupt Flag Register PTG_INTFL [0x0008] Bits Name Access Reset Description pt14 R/W1C PT14 Stopped Status Flag This bit is set to 1 by hardware when the corresponding Pulse Train is in Pulse Train Mode and the loop counter reaches 0. In Square Wave mode, this field is not used.
Page 307: Table 14-5: Pulse Train Engine Interrupt Enable Register
MAX32650–MAX32652 User Guide PT Stopped Interrupt Flag Register PTG_INTFL [0x0008] Bits Name Access Reset Description R/W1C PT5 Stopped Status Flag This bit is set to 1 by hardware when the corresponding Pulse Train is in Pulse Train Mode and the loop counter reaches 0. In Square Wave mode, this field is not used.
Page 308 MAX32650–MAX32652 User Guide PT Interrupt Enable Register PTG_INTEN [0x000C] Bits Name Access Reset Description pt13 PT13 Interrupt Enable Write 1 to enable the interrupt for the corresponding PT when the flag is set in the PTG_INTFL register. 1: Interrupt is enabled.
Page 309: Table 14-6: Pulse Train Engine Safe Enable Register
MAX32650–MAX32652 User Guide PT Interrupt Enable Register PTG_INTEN [0x000C] Bits Name Access Reset Description PT4 Interrupt Enable Write 1 to enable the interrupt for the corresponding PT when the flag is set in the PTG_INTFL register. 1: Interrupt is enabled.
Page 310 MAX32650–MAX32652 User Guide Pulse Train Engine Safe Enable Register PTG_SAFE_EN [0x0010] Bits Name Access Reset Description safeen_pt13 Safe Enable Control for PT1 Writing a 1 sets the corresponding enable bit in the PTG_ENABLE register. 1: Enable corresponding Pulse Train 0: No effect...
Page 311: Table 14-7: Pulse Train Engine Safe Disable Register
MAX32650–MAX32652 User Guide Pulse Train Engine Safe Enable Register PTG_SAFE_EN [0x0010] Bits Name Access Reset Description safeen_pt2 Safe Enable Control for PT2 Writing a 1 sets the corresponding enable bit in the PTG_ENABLE register. 1: Enable corresponding Pulse Train 0: No effect...
Page 312 MAX32650–MAX32652 User Guide Pulse Train Engine Safe Disable Register PTG_SAFE_DIS [0x0014] Bits Name Access Reset Description safedis_pt10 Safe Disable Control for PT10 Writing a 1 clears the corresponding enable bit in the PTG_ENABLE register. 1: Disable corresponding Pulse Train 0: No effect...
Page 313: Table 14-8: Pulse Train Engine Configuration Register
MAX32650–MAX32652 User Guide Table 14-8: Pulse Train Engine Configuration Register Pulse Train Configuration Register PTn_RATE_LENGTH [0x0020] Bits Name Access Reset Description 31:27 mode 0b00001 Square Wave or Pulse Train Output Mode Sets either Pulse Train mode with length, or Square Wave mode.
Page 314: Table 14-11: Pulse Train N Automatic Restart Configuration Register
MAX32650–MAX32652 User Guide Pulse Train Loop Configuration PTn_LOOP [0x0028] Bits Name Access Reset Description 15:0 count Pulse Train Loop Countdown Sets the number of times a pulse train pattern is repeated until it automatically stops. Reading this field returns the number of loops remaining.
Page 315 MAX32650–MAX32652 User Guide Pulse Train Automatic Restart Configuration PTn_RESTART [0x002C] Bits Name Access Reset Description pt_n_select Select PTn Write the Pulse Train number representing PTn. This engine must be in Pulse Train mode. 0: PT0 1: PT1 2: PT2 …...
Page 316: Timers
MAX32650–MAX32652 User Guide Timers The MAX32650–MAX32652 contains six 32-bit, reloadable timers. Each timer provides multiple operating modes: • One-Shot: Timer counts up to terminal value then halts. • Continuous: Timer counts up to terminal value then repeats. • Counter: Timer counts input edges received on timer input pin.
Page 317: Timer Pin Functionality
MAX32650–MAX32652 User Guide Equation 15-1: Timer Peripheral Clock Equation �� _�� Application firmware writes to the timer registers and external events on timer pins are asynchronous events to the slower timer clock frequency. Events are latched on the next rising edge of the timer clock. Since it is not possible to observe the timer clock directly, input events may have a delay of up to 0.5 ×...
Page 318: Figure 15-1: One-Shot Mode Diagram
MAX32650–MAX32652 User Guide 15.4 One-Shot Mode (000b) In One-shot mode the timer peripheral increments TMRn_CNT until it matches TMRn_CMP and then stops incrementing and disables the timer. The timer can optionally output a pulse on the timer pin at the end of the timer period. In this mode, the timer must be re-enabled to start another one-shot mode event.
Page 319: One-Shot Mode Configuration
MAX32650–MAX32652 User Guide One-Shot Mode Configuration Configure the timer for One-Shot mode by doing the following: 1. Set TMRn_CN.ten = 0 to disable the timer. 2. Set TMRn_CN.tmode to 000b to select One-shot mode. 3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
Page 320: Figure 15-2: Continuous Mode Diagram
MAX32650–MAX32652 User Guide 15.5 Continuous Mode (001b) In Continuous mode, the timer peripheral increments TMRn_CNT until it matches TMRn_CMP, resets TMRn_CNT 0x0000 0001, and continues incrementing. The timer peripheral can optionally toggle the state of the timer pin at the end of the timer period.
Page 321: Continuous Mode Configuration
MAX32650–MAX32652 User Guide Continuous Mode Configuration Configure the timer for Continuous mode by performing the steps following: 1. Set TMRn_CN.ten = 0 to disable the timer. 2. Set TMRn_CN.tmode to 001b to select Continuous mode. 3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency, f CNT_CLK 4.
Page 322: Figure 15-3: Counter Mode Diagram
MAX32650–MAX32652 User Guide 15.6 Counter Mode (010b) In Counter mode, the timer peripheral increments TMRn_CNT when a transition occurs on the timer pin. When TMRn_CNT = TMRn_CMP, the interrupt bit is set and the TMRn_CNT register is set to 0x0000 0001 and continues incrementing.
Page 323: Counter Mode Configuration
MAX32650–MAX32652 User Guide Counter Mode Configuration Configure the timer for Counter mode by doing the following: 1. Set TMRn_CN.ten = 0 to disable the timer. 2. Set TMRn_CN.tmode to 010b to select Counter mode. 3. Configure the timer pin: Configure the pin as a timer input and configure the electrical characteristics as needed.
Page 324: Pwm Mode (011B)
MAX32650–MAX32652 User Guide 15.7 PWM Mode (011b) In PWM mode, the timer sends a Pulse-Width Modulated (PWM) output using the timer’s output signal. The timer first counts up to the match value stored in the TMRn_PWM register. At the end of the cycle where the...
Page 325 MAX32650–MAX32652 User Guide If TMRn_CN.tpol is 0, the ratio of the PWM output high time to the total period is calculated using Equation 15-7, below. Equation 15-7: Timer PWM Output High Time Ratio with Polarity 0 ( ��_�� – ��_�� ) ��...
Page 326: Figure 15-4: Capture Mode Diagram
MAX32650–MAX32652 User Guide 15.8 Capture Mode (100b) Capture mode is most often used to measure the time between events. The timer increments from an initial value until an edge transition occurs on the timer pin. This triggers the ‘capture’ event which copies...
Page 327: Capture Mode Configuration
MAX32650–MAX32652 User Guide The timer period event occurs on the timer clock TMRn_CNT = TMRn_CMP. The timer peripheral automatically performs the following actions when an end of timer period event occurs: 1. The value in TMRn_CNT is reset to 0x0000 00001. The timer remains enabled and continues incrementing.
Page 328: Figure 15-5: Counter Mode Diagram
MAX32650–MAX32652 User Guide 15.9 Compare Mode (101b) In Compare mode the timer peripheral increments continually, allowing the timer to be a programmable 32-bit programmable period timer. The end of timer period event occurs when the timer value matches the compare value, but the timer continues to increment until the count reaches 0xFFFF FFFF.
Page 329: Compare Mode Configuration
MAX32650–MAX32652 User Guide Compare Mode Configuration Configure the timer for Compare mode by doing the following: 1. Set TMRn_CN.ten = 0 to disable the timer. 2. Set TMRn_CN.tmode to 011b to select Compare mode. 3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
Page 330: Figure 15-6: Gated Mode Diagram
MAX32650–MAX32652 User Guide 15.10 Gated Mode (110b) Gated mode is similar to Continuous Mode, except that TMRn_CNT only increments when the timer pin is in its active state. Figure 15-6: Gated Mode Diagram TMR_CN.TPL = 0 TIMER PIN (INPUT) TMR_CN.TPL = 1 TIMER CLOCK TMR_CN.TEN...
Page 331: Capture/Compare Mode (111B)
MAX32650–MAX32652 User Guide 15.11 Capture/Compare Mode (111b) In Capture/Compare mode, the timer starts counting after the first external timer input transition occurs. The transition, a rising edge or falling edge on the timer’s input signal, is set using the TMRn_CN.tpol bit.
Page 332: Table 15-1: Timer Register Offset, Names, Access And Descriptions
Register names for a specific instance are defined by appending the instance number to the peripheral name. For example, the Timer Count Register for Timer 0 is TMR0_CNT while the Timer Count Register for Timer 1 is TMR1_CNT. The MAX32650–MAX32652 include six timer instances, defined as TMR0, TMR1, TMR2, TMR3, TMR4 and TMR5.
Page 333: Table 15-5: Timer Interrupt Registers
MAX32650–MAX32652 User Guide Table 15-5: Timer Interrupt Registers Timer Interrupt Register TMRn_INT [0x000C] Bits Name Access Reset Description 31:1 Reserved for Future Use Do not modify this field. Timer Interrupt If set, this field indicates a timer interrupt condition occurred.
Page 334 MAX32650–MAX32652 User Guide Timer Control Register TMRn_CN [0x0010] Bits Name Access Reset Description pres Timer Prescaler Select Sets the timer’s prescaler value. The prescaler divides the PCLK input to the timer and = PCLK ( Hz ) ⁄ sets the timer’s count clock, .The timer’s...
Page 335: Table 15-7: Timer Non-Overlapping Compare Registers
MAX32650–MAX32652 User Guide Timer Control Register TMRn_CN [0x0010] Bits Name Access Reset Description tmode Timer Mode Select Sets the timer’s operating mode. tmode Timer Mode 0b000 One-Shot 0b001 Continuous 0b010 Counter 0b011 PWM 0b100 Capture 0b101 Compare 0b110 Gated 0b111 Capture/Compare...
Page 336: Figure 16-1: Watchdog Timer Block Diagram
MAX32650–MAX32652 User Guide Watchdog Timer (WDT) The watchdog timer protects against corrupt or unreliable software, power faults, and other system-level problems, which may place the microcontroller into an improper operating state. When the application is executing properly, application software periodically resets the watchdog counter. If the watchdog timer interrupt is enabled and the software does not reset the counter within the interrupt time period WDTn_CTRL.int_period), the watchdog timer generates a watchdog timer...
Page 337: Table 16-1: Watchdog Timer Interrupt Period
MAX32650–MAX32652 User Guide 16.1 Features • Sixteen programmable time periods for the watchdog interrupt  through 2 PCLK cycles • Sixteen programmable time periods for the watchdog reset  through 2 PCLK cycles • The watchdog timer counter is reset on all forms of reset 16.2...
Page 338: Enabling The Watchdog Timer
MAX32650–MAX32652 User Guide WDTn_CTRL INT_PERIOD int_period (seconds) 0.018 0.035 0.070 0.140 0.280 0.560 1.12 2.24 4.47 8.95 17.9 Disabled 16.4 Enabling the Watchdog Timer The watchdog timers are free running and require a protected sequence of writes to enable the watchdog timers to prevent an unintended reset during the enable process.
Page 339: Table 16-2: Watchdog Timer Register Offsets, Names And Descriptions
MAX32650–MAX32652 User Guide 16.7 Detection of a Watchdog Reset Event During system start-up, system software should check the WDTn_CTRL.rst_flag to determine if the reset was the result of a watchdog reset. Application software is responsible for taking appropriate actions if a watchdog reset occurred.
Page 340: Table 16-4: Watchdog Timer Reset Register
MAX32650–MAX32652 User Guide Watchdog Timer Control Register WDTn_CTRL [0x0000] Bits Name Access Reset Description rst_period Reset Period Sets the number of PCLK cycles until a system reset occurs if the watchdog timer is not reset. 0xF: 2 × �� ...
Page 341 MAX32650–MAX32652 User Guide Watchdog Timer Reset Register WDTn_RST [0x0004] Register Field Bits Access Reset Description Reset Register Writing the watchdog counter reset sequence to this register resets the watchdog counter. The following is the required reset sequence to reset the wdt_rst watchdog and prevent a watchdog timer interrupt or watchdog system reset.
Page 342: Table 17-1: Owm Pin To Alternate Function Mapping
MAX32650–MAX32652 User Guide 1-Wire Master The MAX32650–MAX32652 provides a 1-Wire® master (OWM) that you can use to communicate with one or more external, 1-Wire slave devices using a single-signal, combined clock, data protocol. The OWM is contained in the OWM module. The OWM module handles the lower-level details (including timing and drive modes) required by the 1-Wire protocol, allowing the CPU to communicate over the 1-Wire bus at a logical data level.
Page 343: Pin Configuration
MAX32650–MAX32652 User Guide Pin Configuration Perform the following steps to configure the GPIO for OWM peripheral usage: 1. Enable the alternate function mode for pins P1.30 and P1.31 by setting GPIO1_EN[30:31] to 0. 2. Set alternate function 1 (AF1) by setting GPIO1_AF_SEL[30:31] to 0.
Page 344: Figure 17-1: 1-Wire Signal Interface
1-Wire specification - standard speed, overdrive speed, and hyperdrive speed. However, only standard speed and overdrive speed are supported by the OWM peripheral in the MAX32650–MAX32652. The OWM begins each communication sequence by sending a reset pulse as shown in Figure 17-2.
Page 345: Figure 17-2: 1-Wire Reset Pulse
MAX32650–MAX32652 User Guide Figure 17-2: 1-Wire Reset Pulse In general, the 1-Wire line must idle in a high state when communication is not taking place. It is possible for the master to pause communication in between time slots. There is no overall ’timeout’ period that causes a slave to revert to the reset state if the master takes too long between one time slot and the next time slot.
Page 346: Figure 17-3: 1-Wire Write Time Slot
MAX32650–MAX32652 User Guide Figure 17-3: 1-Wire Write Time Slot From the slave’s perspective, the initial falling edge of the time slot triggers the start of an internal timer, and when the proper amount of time has passed, the slave samples the 1-Wire line that is driven by the master. This sampling point is in between the end of the minimum-width low pulse and the end of the time slot.
Page 347: Figure 17-5: 1-Wire Rom Id Fields
MAX32650–MAX32652 User Guide 17.6 Standard Speed and Overdrive Speed By default, all 1-Wire communications following reset begin at the lowest rate of speed (that is, standard speed). For 1-Wire devices that support it, it is possible for the OWM to increase the rate of communication from standard speed to overdrive speed by sending the appropriate command.
Page 348: Table 17-3: 1-Wire Slave Device Rom Id Field
MAX32650–MAX32652 User Guide Table 17-3: 1-Wire Slave Device ROM ID Field Field Bit Number Description Family code 0 ... 7 This 8-bit value is used to identify the type of a 1-Wire slave device. This 48-bit value is factory-programmed to give each 1-Wire slave device (within a given family code Unique ID 8 ...
Page 349: Match Rom And Overdrive Match Rom Commands
MAX32650–MAX32652 User Guide Match ROM and Overdrive Match ROM Commands The Match ROM command is used by the OWM to select one and only one slave 1-Wire device when the ROM ID of the device has already been determined. When transmitting this command, the master sends the command byte (that is, 55h for standard speed and 69h for overdrive speed) and then sends the entire 64-bit ROM ID for the device selected, least significant bit first.
Page 350: Resume Communication Command
MAX32650–MAX32652 User Guide After the four-bit processing stage is complete, the return value loaded into OWM_DATA.tx_rx consists of eight bits. The low nibble (bits 0 through 3) contains the four discrepancy flags: one for each ID bit processed. If the discrepancy bit is set to 1, it means that either two slaves with differing ID bits in that position both responded (the two bits read were both zero), or that no slaves responded (the two bits read were both 1).
Page 351: Resetting The Owm
MAX32650–MAX32652 User Guide Resetting the OWM The first step in any 1-Wire communication sequence is to reset the 1-Wire bus. To direct the OWM module to complete a 1-Wire reset, write OWM_CTRL_STAT.start_ow_reset to 1. This generates a reset pulse and checks for a replying presence pulse from any connected slave devices.
Page 352: Table 17-4: Owm Register Offsets, Names, Access And Descriptions
MAX32650–MAX32652 User Guide To read a single bit value from the 1-Wire Bus, complete the following steps: 1. Set OWM_CFG.single_bit_mode to 1. This setting causes the OWM to transmit/receive a single bit of data at a time instead of the default 8 bits.
Page 353: Table 17-5: Owm Configuration Register
MAX32650–MAX32652 User Guide 17.10 OWM Register Details Table 17-5: OWM Configuration Register OWM Configuration Register OWM_CFG [0x0000] Bits Name Access Reset Description 31:8 Reserved for Future Use Do not modify this field. int_pullup_enable Internal Pullup Enable Set this field to enable the internal pullup resistor.
Page 354: Table 17-6: Owm Clock Divisor Register
MAX32650–MAX32652 User Guide OWM Configuration Register OWM_CFG [0x0000] Bits Name Access Reset Description long_line_mode Long Line Mode Enable Selects alternate timings for 1-Wire communication. The recommended setting depends on the length of the wire. For lines less than 40 meters, 0 should be used.
Page 355: Table 17-8: Owm Data Register
MAX32650–MAX32652 User Guide OWM Control/Status Register OWM_CTRL_STAT [0x0008] Bits Name Access Reset Description bit_bang_oe OWM Bit Bang Output When bit bang mode is enabled (OWM_CFG.bit_bang_en = 1), this bit sets the state of the OWM_IO pin. Setting this bit to 1, drives the OWM_IO pin low.
Page 356: Table 17-10: Owm Interrupt Enable Register
MAX32650–MAX32652 User Guide OWM Interrupt Flags Register OWM_INTFL [0x0010] Bits Name Access Reset Description tx_data_empty R/W1C TX Empty The OWM hardware automatically sets this interrupt flag when the data transmit is complete. Write 1 to clear this flag. 0: Either no data was sent or the data in the OWM_DATA.tx_rx field has not completed transmission.
Page 357: Usbhs 2.0 Hi-Speed Host Interface With Phy
MAX32650–MAX32652 User Guide USBHS 2.0 Hi-Speed Host Interface with PHY The microcontroller includes one Universal Serial Bus (USB) Host communications peripheral with a USB physical interface (PHY). The USB Host is USB 2.0 Hi-Speed (USBHS) compliant, capable of transfers at 480Mbits/sec. It supports Host mode with 12 USB buffers called Endpoints.
Page 358: Usbhs Bus Signals
MAX32650–MAX32652 User Guide Supported interrupts include: • Interrupts for each IN endpoint from Endpoint 0 to Endpoint 11 • Interrupts for each OUT endpoint from Endpoint 1 to Endpoint 11 • Start of Frame (SOF) • RESET bus state •...
Page 359: Table 18-1: Usb Bus States Indicated By The Differential Pair (D+, D-)
MAX32650–MAX32652 User Guide Table 18-1: USB Bus States indicated by the differential pair (D+, D-) Bus State Condition Notes Differential 1 Host or Device is driving the bus Differential 0 Host or Device is driving the bus Single Ended Zero (SE0)
Page 360: Usbhs Reset
MAX32650–MAX32652 User Guide Each USBHS Data Endpoint supports the following features: • Single or double buffered • Programmable and flexible interrupts • Ability to send a STALL packet to the Host to indicate an error with the data • Ability to automatically send an ACK packet to the Host to acknowledge a successful data transfer •...
Page 361: Table 18-2: Usb Bulk In Endpoints Options
MAX32650–MAX32652 User Guide Endpoint 0 Error Handling The USBHS can detect and generate interrupts for control transfers errors. It sends a STALL packet on the bus and generates an interrupt if the incorrect amount of data is transferred over the bus. This can happen under the following conditions: 1.
Page 362: Bulk Out Endpoints
MAX32650–MAX32652 User Guide Bulk OUT Endpoints A Bulk OUT endpoint is used to transfer non-periodic data from the Host to the function controller. Five optional features are available for use with a Bulk OUT endpoint. Bulk OUT Endpoint Option Description...
Page 363: Table 18-3: Usb Isochronous In Endpoint Options
MAX32650–MAX32652 User Guide 18.9 Isochronous Endpoints Isochronous IN Endpoints An Isochronous IN endpoint is used to transfer time-sensitive but loss-tolerant data from a USB Device to a USB Host. Five optional features are available for use with an Isochronous IN endpoint as shown in Table 18-3, below.
Page 364: Table 18-4: Usb Isochronous Out Endpoint Options
MAX32650–MAX32652 User Guide Table 18-4: USB Isochronous OUT Endpoint Options Isochronous OUT Endpoint Option Description Double Packet Buffering When the value written to the USBHS_OUTMAXP register is less than or equal to half the size of the FIFO allocated to the endpoint, and double packet buffering is allowed (USBHS_OUTCSRU.dpktbufdis = 0), double packet buffering is enabled.
Page 365: Table 18-6: Usbhs Device Address Register
MAX32650–MAX32652 User Guide Offset Register Name Access Description [0x000C] USBHS_FRAME USBHS Frame Number [0x000E] USBHS_INDEX USBHS Endpoint and Status Register Index Select [0x000F] USBHS_TESTMODE USBHS Test Mode Register [0x0010] USBHS_INMAXP USBHS IN Endpoints Maximum Packet Size [0x0012] USBHS_CSR0 USBHS EP0 Control Status Register...
Page 366: Table 18-7: Usbhs Power Management Register
MAX32650–MAX32652 User Guide USBHS Device Address Register USBHS_FADDR [0x0000] Bits Name Access Reset Description faddr USBHS Device Address This is the USB Device address specified by the external USB Host during the enumeration process. It must be written with the address value contained in the SET_ADDRESS Device request when received during a Control Transaction.
Page 367: Table 18-8: Usbhs In Endpoints Interrupt Flags Register
MAX32650–MAX32652 User Guide Table 18-8: USBHS IN Endpoints Interrupt Flags Register USBHS IN Endpoints Interrupt Flags USBHS_INTRINFL [0x0002] Bits Name Access Reset Description 16:12 Reserved for Future Use Do not modify this field. ep11_in IN EP11 Interrupt Status Flag 0: IN Endpoint 11 not active.
Page 368: Table 18-9: Usbhs Out Endpoints Interrupt Flags Register
MAX32650–MAX32652 User Guide Table 18-9: USBHS OUT Endpoints Interrupt Flags Register USBHS OUT Endpoints Interrupt Flags USBHS_INTROUTFL [0x0004] Bits Name Access Reset Description 16:12 Reserved for Future Use Do not modify this field. ep11_out OUT EP11 Interrupt Status Flag 0: OUT Endpoint 11 interrupt not active.
Page 369: Table 18-10: Usbhs In Endpoints Interrupt Enable Register
MAX32650–MAX32652 User Guide Table 18-10: USBHS IN Endpoints Interrupt Enable Register USBHS IN Endpoints Interrupt Enable USBHS_INTRINEN [0x0006] Bits Name Access Reset Description 16:12 Reserved for Future Use Do not modify this field. ep11_in IN EP11 Interrupt Enable Set to 1 to enable the interrupt for IN Endpoint 11.
Page 370: Table 18-11: Usbhs Out Endpoints Interrupt Enable Register
MAX32650–MAX32652 User Guide USBHS IN Endpoints Interrupt Enable USBHS_INTRINEN [0x0006] Bits Name Access Reset Description EP0 Interrupt Enable Set to 1 to enable the the interrupt IN Endpoint 0. 0: Interrupt disabled. 1: Interrupt enabled. Table 18-11: USBHS OUT Endpoints Interrupt Enable Register...
Page 371: Table 18-12: Usbhs Signaling Interrupt Status Flag Register
MAX32650–MAX32652 User Guide USBHS OUT Endpoints Interrupt Enable USBHS_INTROUTEN [0x0008] Bits Name Access Reset Description ep3_out OUT EP3 Interrupt Enable Set to 1 to enable the interrupt for OUT Endpoint 3. 0: Interrupt disabled. 1: Interrupt enabled. ep2_out OUT EP2 Interrupt Enable Set to 1 to enable the interrupt for OUT Endpoint 2.
Page 372: Table 18-14: Usbhs Frame Number Register
MAX32650–MAX32652 User Guide USBHS Signaling Interrupt Enable USBHS_INTSIGEN [0x000B] Bits Name Access Reset Description suspend Suspend Mode Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Table 18-14: USBHS Frame Number Register USBHS_FRAME USBHS Frame Number [0x000C] Bits Name...
Page 373: Table 18-17: Usb Memory Mapped Register Access For Endpoints 1 To 11
MAX32650–MAX32652 User Guide USBHS Test Mode Register USBHS_TESTMODE [0x000F] Bits Name Access Reset Description test_packet Test Packet Mode To enter this test mode, firmware must write the standard 53-byte test packet to the Endpoint 0 FIFO, then set USBHS_INCSRL.inpktrdy = 1, then set this bit. The DATA0 PID is automatically added to the head of the packet and the CRC to the end of the packet.
Page 374: Table 18-18: Usbhs In Endpoint Maximum Packet Size Register
MAX32650–MAX32652 User Guide USBHS IN Endpoint Maximum Packet Size Registers Endpoint 1 to 11 have a memory mapped version of this register selected using the USBHS_INDEX register. Table 18-18: USBHS IN Endpoint Maximum Packet Size Register USBHS IN Endpoint Maximum Packet Size...
Page 375: Table 18-20: Usbhs Endpoint 0 Control Status Register
MAX32650–MAX32652 User Guide USBHS IN Endpoint Lower Control and Status USBHS_INCSRL [0x0012] Bits Name Access Reset Description sendstall Send STALL Handshake 1: Respond to an IN token with a STALL handshake. 0: Terminate STALL handshake Note: Ignored for Isochronous transfers.
Page 376: Table 18-21: Usbhs In Endpoint Upper Control Register
MAX32650–MAX32652 User Guide USBHS Endpoint 0 Control Status USBHS_CSR0 [0x0012] Bits Name Access Reset Description setupend Read Setup End Status Automatically set when a Control Transaction ends before the dataend bit has been set by firmware. An interrupt is generated when this bit is set.
Page 377: Table 18-22: Usbhs Out Endpoint Maximum Packet Size Register
MAX32650–MAX32652 User Guide USBHS IN Endpoint Upper Control USBHS_INCSRU [0x0013] Bits Name Access Reset Description dmareqenab DMA Request Enable 0: Disable DMA for this IN endpoint 1: Enable DMA for this IN endpoint frcdatatog Force IN Data-Toggle 0: Toggle data-toggle only when an ACK is received...
Page 378: Table 18-23: Usbhs Out Endpoint Lower Control Status Register
MAX32650–MAX32652 User Guide Table 18-23: USBHS OUT Endpoint Lower Control Status Register USBHS OUT Endpoint Lower Control Status USBHS_OUTCSRL [0x0016] Bits Name Access Reset Description clrdatatog R/W1O Clear IN Endpoint Data Toggle 1: Clear the OUT endpoint data-toggle to 0.
Page 379: Table 18-24: Usbhs Out Endpoint Upper Control Status Register
MAX32650–MAX32652 User Guide Table 18-24: USBHS OUT Endpoint Upper Control Status Register USBHS OUT Endpoint Upper Control Status Register USBHS_OUTCSRU [0x0017] Bits Name Access Reset Description autoclear Auto Clear outpktrdy 0: USBHS_OUTCSRL.outpktrdy must be cleared by firmware 1: USBHS_OUTCSRL.outpktrdy is automatically cleared when data that is of the...
Page 380: Table 18-25: Usbhs Endpoint Out Fifo Byte Count Register
MAX32650–MAX32652 User Guide Table 18-25: USBHS Endpoint OUT FIFO Byte Count Register USBHS Endpoint OUT FIFO Byte Count USBHS_OUTCOUNT [0x0018] Bits Name Access Reset Description 15:13 Reserved for Future Use Do not modify this field. 12:0 outcount Read Number of Data Bytes in OUT FIFO Returns the number of data bytes in the packet that are read next in the OUT FIFO.
Page 381: Table 18-27: Usbhs Fifo For Endpoint N Register
MAX32650–MAX32652 User Guide Table 18-27: USBHS FIFO for Endpoint n Register USBHS FIFO for Endpoint 0 USBHS_FIFO0 [0x0020] USBHS FIFO for Endpoint 1 USBHS_FIFO1 [0x0024] USBHS FIFO for Endpoint 2 USBHS_FIFO2 [0x0028] USBHS FIFO for Endpoint 3 USBHS_FIFO3 [0x002C] USBHS FIFO for Endpoint 4...
Page 382: Table 18-29: Usbhs Ram Info Register
MAX32650–MAX32652 User Guide Table 18-29: USBHS RAM Info Register USBHS RAM Info USBHS_RAMINFO [0x0079] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. rambits Number of RAM Address Bits The width of the RAM address bus in this USBHS module. The width is 12 bits.
Page 383: Table 18-32: Usbhs Hi-Speed Chirp Timeout Register
MAX32650–MAX32652 User Guide Table 18-32: USBHS Hi-Speed Chirp Timeout Register USBHS Hi-Speed Chirp Timeout USBHS_CTUCH [0x0080] Bits Name Access Reset Description 15:0 c_t_uch 0x203A HS Chirp Timeout Clock Cycles This configures the chirp timeout used by this Device to negotiate a HS connection with a FS Host.
Page 384: Figure 19-1: Spi Modes Of Operation
MAX32650–MAX32652 User Guide Quad Serial Peripheral Interface (SPI3) The Quad Serial Peripheral Interface (SPI3) is a highly configurable, synchronous communications peripheral that interfaces to SPI devices as either a Master or Slave. The Quad SPI port is designated as SPI3.
Page 385: Spi Signals
MAX32650–MAX32652 User Guide SPI Signals • SS = Slave Select with programmable polarity  SPI3 supports up to 4 Slave Select lines (SPI3_SS[0:3]) • SCLK = Serial Clock configurable as an output for master mode and an input for slave mode •...
Page 386: Spi3 Fifos
MAX32650–MAX32652 User Guide Set SPI3_CTRL0.start=1 to begin a Master Mode transmission. Do not modify the SPI timing registers while a SPI transaction is in progress. Modifying any SPI timing register while a SPI transfer is in progress will result in an invalid SPI communication transaction.
Page 387: Figure 19-2: Spi Mode 0, Four-Wire Communication
MAX32650–MAX32652 User Guide • RX FIFO Threshold • TX FIFO Threshold 19.3 Timing Diagrams The following waveform diagrams show SPI communications in each of the four SPI modes. SPI Mode 0 Figure 19-2: SPI Mode 0, Four-Wire Communication cpol = 0...
Page 388: Figure 19-5: Spi Mode 1, Three-Wire Communication
MAX32650–MAX32652 User Guide Figure 19-5: SPI Mode 1, Three-Wire Communication cpol = 0 Three-Wire SPI cpha = 1 SDIO INACT SCLK ACT2 ACT1 ACT1 ACT2 Bit 15 Bit 14 Bit 1 Bit 0 Bit 15 Bit 14 Bit 1 Bit 0...
Page 389: Figure 19-8: Spi Mode 3, Four-Wire Communication
MAX32650–MAX32652 User Guide SPI Mode 3 Figure 19-8: SPI Mode 3, Four-Wire Communication cpol = 1 Four-Wire SPI cpha = 1 MOSI / MISO SCLK INACT ACT2 ACT1 ACT1 ACT2 MOSI Bit 15 Bit 14 Bit 1 Bit 0 Bit 15...
Page 390: Table 19-2: Spi3 Fifo Data Registers
MAX32650–MAX32652 User Guide 19.5 Quad SPI Master Register Details Table 19-2: SPI3 FIFO Data Registers SPI3_DATA SPI3 FIFO Data Register [0x0000] Bits Name Access Reset Description 31:0 data SPI FIFO Data Register Reads dequeue data off the receive FIFO. Writes queue data onto the transmit FIFO.
Page 391: Table 19-4: Spi3 Transmit Packet Size Register
MAX32650–MAX32652 User Guide SPI3 Control 0 Register SPI3_CTRL0 [0x0004] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. master SPI Master Mode Enable This field selects between slave mode and master mode operation for the SPI port.
Page 392: Table 19-6: Spi3 Slave Select Timing Register
MAX32650–MAX32652 User Guide SPI3 Control 2 Register SPI3_CTRL2 [0x000C] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. 13:12 data_width 0b00 SPI Data Width 0: 1-data pin (Single Mode) 1: 2-data pins (Dual Mode) 2: 4-data pins (Quad Mode)
Page 393: Table 19-7: Spi3 Master Clock Configuration Registers
MAX32650–MAX32652 User Guide SPI3 Slave Select Timing Register SPI3_SS_TIME [0x0010] Bits Name Access Reset Description Slave Select Delay to First SCLK Set the number of system clock cycles the Slave Select is held active prior to the first SCLK edge.
Page 394 MAX32650–MAX32652 User Guide SPI3 DMA Control Register SPI3_DMA [0x001C] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. 29:24 rx_fifo_cnt Number of Bytes in the RX FIFO Read returns the number of bytes currently in the RX FIFO...
Page 395: Table 19-9: Spi3 Interrupt Status Flags Registers
MAX32650–MAX32652 User Guide Table 19-9: SPI3 Interrupt Status Flags Registers SPI3 Interrupt Status Flags Register SPI3_INT_FL [0x0020] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. rx_und RX FIFO Underrun Flag Set when a read is attempted from an empty RX FIFO.
Page 396 MAX32650–MAX32652 User Guide SPI3 Interrupt Enable Register SPI3_INT_EN [0x0024] Bits Name Access Reset Description rx_und RX FIFO Underrun Interrupt Enable 0: Interrupt is disabled 1: Interrupt is enabled rx_ovr RX FIFO Overrun Interrupt Enable 0: Interrupt is disabled 1: Interrupt is enabled...
Page 397: Table 19-11: Spi3 Wakeup Status Flags Registers
MAX32650–MAX32652 User Guide Table 19-11: SPI3 Wakeup Status Flags Registers SPI3 Wakeup Flags Register SPI3_WAKE_FL [0x0028] Bits Name Access Reset Description 31:4 Reserved for Future Use Do not modify this field. rx_full R/W1C Wake on RX FIFO Full Flag 0: Wake condition has not occurred.
Page 398 MAX32650–MAX32652 User Guide SPI3 Status Register SPI3_STAT [0x0030] Bits Name Access Reset Description busy SPI Active Status 0: SPI is not active. In Master Mode, cleared when the last character is set. In Slave Mode, cleared when SS is deasserted.
Page 399: Figure 20-1. Spimss Block Diagram
MAX32650–MAX32652 User Guide SPIMSS for I 20.1 Overview The SPIMSS peripheral provides independent serial communication support for I S (Inter-IC Sound) for 16-bit mono or stereo audio transfer to or from an external I S audio codec. Features • S mode ...
Page 400: Figure 20-2. Spi Single-Master, Single-Slave
S master, the SCLK and SSEL signals are outputs. When operating as the I S slave, the SCLK and SSEL signals are inputs. This SSEL signal is referred to as word select signal (WS) in the I S protocol. Normally the WS signal transitions one Maxim Integrated Page 400 of 411...
Page 401: Table 20-1. Clock Phase And Polarity Operation
16 bits (as set by the SPIMSSn_MOD.numbits field), the transmit character must be left justified in the SPIMSSn Data Register. A received character of less than 16 bits will be right justified (last bit received will be in bit position 0). For Maxim Integrated Page 401 of 411...
Page 402: Mute
The receive channel will read the data from the left channel (SSEL = 0) and ignore data in the right channel. This allows DMA buffers for mono mode to be one-half the size of DMA buffers for stereo mode. Maxim Integrated Page 402 of 411...
Page 403: Figure 20-5: I S Mode Right Justify Mode
A transmit overrun error indicates a write to the FIFO was attempted when the internal transmit FIFO was full in either master or slave mode. An overrun condition sets the SPIMSSn_INT_FL.tovr bit to 1. Writing a 1 to SPIMSSn_INT_FL.tovr clears this error flag. Maxim Integrated Page 403 of 411...
Page 404: Mode Fault (Multi-Master Collision)
When the SPIMSS is disabled an SPIMSS interrupt can be generated using the SPIMSS Bit Rate Generator timeout. Enable the SPIMSS Bit Rate Generator by setting SPIMSSn_CTRL.birq to 1 to use the SPIMSS BRG as a timer. Maxim Integrated Page 404 of 411...
Page 405: Table 20-2: Spimssn Register Offsets, Access And Descriptions
[0x0004] SPIMSSn_CTRL SPIMSS Control Register [0x0008] SPIMSSn_INT_FL SPIMSS Interrupt Flag Register [0x000C] SPIMSSn_MOD SPIMSS Mode Register [0x0014] SPIMSSn_BRG SPIMSS Bit Rate Register [0x0018] SPIMSSn_DMA SPIMSS DMA Register [0x001C] SPIMSSn_I2S_CTRL SPIMSS I S Control Register Maxim Integrated Page 405 of 411...
Page 406: Table 20-3. Spimss Data Register
0: Wired OR configuration disabled. 1: Wired OR configuration enabled. mmen SPI Master Mode Enable Set this field to enable Master Mode for SPI. 0: SPI set to slave mode operation 1: SPI set to master mode operation Maxim Integrated Page 406 of 411...
Page 407: Table 20-5: Spimss Interrupt Flag Register
1: A FIFO underrun has occurred txst Transmit Status This field reads 1 if a SPIMSS data transmission is currently in progress. 0: No data transmission currently in progress. 1: Data transmission currently in progress Maxim Integrated Page 407 of 411...
Page 408: Table 20-6: Spimss Mode Register
SPIMSSn_MOD.ssel_mode = 1, writing this field drives the pin to the value written. If the slave select pin is set to an input SPIMSSn_MOD.ssel_mode = 0, reading this field returns the level of the slave select pin. Maxim Integrated Page 408 of 411...
Page 409: Table 20-7: Spimss Bit Rate Generator Register
7: Request Receive DMA when RX FIFO contains 8 entries tx_dma_en Transmit DMA Enable Disabling clears any active request to the DMA controller. 0: Disable TX DMA requests 1: Enable TX DMA requests 14:12 Reserved for Future Use Do not modify this field. Maxim Integrated Page 409 of 411...
Page 410: Table 20-9: Spimss I 2 S Control Register
S Mute Transmit 0: Normal transmit. 1: Transmit data is replaced with 0 i2s_en S Mode Enable Set to enable I S mode. 0: I S mode is disabled. 1: I S mode enabled. Maxim Integrated Page 410 of 411...
Page 411: Trademarks
9/18 Initial release ©2018 by Maxim Integrated Products, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.

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Maxim Integrated MAX32650 User Manual

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Memory, Register Mapping, and Access

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