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Maxim Integrated MAX31782 User Manual

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Revision 0; 8/11
MAX31782 User's Guide
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.

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Summary of Contents for Maxim Integrated MAX31782

  • Page 1 Revision 0; 8/11 MAX31782 User’s Guide Functional Diagrams Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc.

  • Page 2: Table Of Contents

    MAX31782 User’s Guide TABLE OF CONTENTS SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2: Architecture .

  • Page 3: Section 1: Overview

    The MAX31782 system management microcontroller provides a complete solution for the monitoring and controlling of complex system physical health characteristics . The MAX31782 is based on the high-performance 16-bit family of MAXQM reduced instruction set computing (RISC) microcontrollers . The MAX31782 provides generous amounts of flash program memory and SRAM data memory .
  • Page 4 • Included ROM routines that allow bootloading and in-application programming flash memory • In-system debugging This document is provided as a supplement to the MAX31782 IC data sheet . This user’s guide provides the information necessary to develop applications using the MAX31782 . All electrical and timing specifications, pin descriptions, pack- age information, and ordering information can be found in the MAX31782 IC data sheet .
  • Page 5 MAX31782 User’s Guide SECTION 2: ARCHITECTURE This section contains the following information: 2 .1 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2 .2 Register Space .

  • Page 6: Section 2: Architecture

    MAX31782 User’s Guide SECTION 2: ARCHITECTURE The MAX31782 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with flash memory . It is structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture . Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data . The highly efficient core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching .

  • Page 7: Register Space

    The architecture of the MAX31782 is transport-triggered . This means that writing to or reading from certain register locations also causes side effects to occur . These side effects form the basis of the MAX31782’s higher level op codes, such as ADDC, OR, and JUMP . While these op codes are actually implemented as MOVE instructions between cer- tain register locations, the encoding is handled by the assembler and need not be a concern to the programmer .

  • Page 8: Memory Types

    • 16-level stack memory for storage of program return addresses and general-purpose use The memory on the MAX31782 is organized according to a Harvard architecture . This means that there are separate bus- ses for both program and data memory . Stack memory is also separate and is accessed through a dedicated register set .

  • Page 9: Sram Memory

    MAX31782 User’s Guide 2.3.2SRAMMemory The MAX31782 contains 1KWords (1K x 16) of SRAM memory . The SRAM memory address begins at address 0000h and is contiguous through word address 03FFh . The contents of the SRAM are indeterminate after power-on reset, but are maintained during stop mode and non-POR resets .

  • Page 10: Program Memory Access

    Data memory mapping and access control are handled by the memory management unit (MMU) . Read/write access to data memory can be in word or in byte mode . The MAX31782 provides three pointers that can be used for indirect accessing of data memory .

  • Page 11: Utility Rom

    MAX31782 User’s Guide PROGRAM SPACE FFFFh A3FFh 1K x 16 SRAM A000h 8FFFh 4K x 16 UTILITY ROM 8000h 7FFFh 16K x 16 FLASH (PAGE 1) 4000h 3FFFh 16K x 16 FLASH (PAGE 0) 0000h Figure 2-2. Program Memory Mapping MaximIntegrated 2-7 Revision 0;...

  • Page 12: Frame Pointer

    The frame pointer (BP[OFFS]) is formed by the 16-bit unsigned addition of the 16-bit frame pointer base register (BP) and the 8-bit frame pointer offset register (OFFS) . The method the MAX31782 uses to access data using the frame pointer is similar to the data pointers . When increments or decrements are used, only the value of OFFS is incremented or decremented .

  • Page 13: Memory Map When Executing From Flash Memory

    MAX31782 User’s Guide 2.4.4.1MemoryMapWhenExecutingfromFlashMemory When executing from the flash memory: • Read and write operations of SRAM memory are executed normally . • The utility ROM can be read as data, starting at 8000h of the data space . The utility ROM cannot be written .

  • Page 14: Memory Map When Executing From Utility Rom

    MAX31782 User’s Guide 2.4.4.2MemoryMapWhenExecutingfromUtilityROM When executing from the utility ROM: • Read and write operations of SRAM memory are executed normally . • Reading of flash memory is executed normally . Writing to flash memory requires the use of the utility ROM routines .

  • Page 15: Memory Map When Executing From Sram

    MAX31782 User’s Guide 2.4.4.3MemoryMapWhenExecutingfromSRAM When executing from the SRAM: The utility ROM can be read as data, starting at 8000h of the data space . The utility ROM cannot be written . Reading of flash memory is executed normally . Writing to flash memory requires the use of the utility ROM routines .

  • Page 16: Data Alignment

    0000h . The RST pin is an output as well as an input . If a reset condition is generated by one of the MAX31782’s internal reset sources (brownout, watchdog timer, or internal reset), an output reset pulse is generated on the RST pin while the MAX31782 remains in reset .

  • Page 17: Watchdog Timer Reset

    During normal operation, the MAX31782 is placed into external reset when the RST pin is held at logic 0 for at least four clock cycles . Once the MAX31782 enters reset mode, it remains in reset as long as the RST pin is held at logic 0 . After the RST pin returns to logic 1, the processor exits reset within 12 clock cycles .

  • Page 18: Clock Generation

    . There is a delay of approximately 1000 clock cycles (t ) between SU:MOSC when the oscillator starts and when clocking of the MAX31782 begins . This delay ensures that the clock is stable prior to beginning normal operation . 2.8PowerModes The MAX31782 has two modes of operation .

  • Page 19: Section 3: System Register Descriptions

    MAX31782 User’s Guide SECTION 3: SYSTEM REGISTER DESCRIPTIONS This section contains the following information: 3 .1 System Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3 .1 .1 Accumulator Pointer Register (AP, 8h[0h]) .
  • Page 20 SECTION 3: SYSTEM REGISTER DESCRIPTIONS Most MAX31782 functions are controlled by sets of registers . These registers provide a working space for memory oper- ations as well as configuring and addressing peripheral registers on the device . Registers are divided into two major types: system registers and peripheral registers .
  • Page 21 MAX31782 User’s Guide Table3-2.SystemRegisterBitFunctions REGISTER — — — — AP (4 bits) — — — MOD2 MOD1 MOD0 — GPF1 GPF0 — — — — — — — — — CDA0 — — — CKCN — — — STOP —...

  • Page 22: System Register Bit Descriptions

    MAX31782 User’s Guide 3.1SystemRegisterBitDescriptions 3.1.1AccumulatorPointerRegister(AP,8h[0h]) Initialization: This register is cleared to 00h on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION Active Accumulator Select . These bits select which of the 16 accumulator registers are used for arithmetic and logical operations .

  • Page 23: Processor Status Flags Register (Psf, 8H[4H])

    MAX31782 User’s Guide 3.1.3ProcessorStatusFlagsRegister(PSF,8h[4h]) Initialization: This register is cleared to 80h on all forms of reset . Access: Bit 7 (Z), bit 6 (S), and bit 2 (OV) are read-only . Bits 4 and 3 (GPF1, GPF0), bit 1 (C), and bit 0 (E) are unre- stricted read/write .

  • Page 24: Interrupt Mask Register (Imr, 8H[6H])

    MAX31782 User’s Guide 3.1.5InterruptMaskRegister(IMR,8h[6h]) Initialization: This register is cleared to 00h on all forms of reset . Access: Unrestricted read/write access . The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module . The eighth bit, IMS, serves as a mask for any system module interrupt sources .

  • Page 25: Interrupt Identification Register (Iir, 8H[Bh])

    MAX31782 User’s Guide 3.1.7InterruptIdentificationRegister(IIR,8h[Bh]) Initialization: This register is cleared to 00h on all forms of reset . Access: Read-only . The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module . The eighth bit, IIS, indicates a pending system interrupt, such as from the watchdog timer .

  • Page 26: Watchdog Control Register (Wdcn, 8H[Fh])

    MAX31782 User’s Guide 3.1.9WatchdogControlRegister(WDCN,8h[Fh]) Initialization: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions . Access: Unrestricted direct read/write access . FUNCTION Reset Watchdog Timer . Setting this bit to 1 resets the watchdog timer count . If watchdog interrupt and/or reset WDCN .0...

  • Page 27: Accumulator N Register (A[N], 9H[Nh])

    MAX31782 User’s Guide 3.1.10AccumulatornRegister(A[n],9h[nh]) Initialization: This register is cleared to 0000h on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION This register acts as the accumulator for all ALU arithmetic and logical operations when selected by the A[n] .[15:0]...

  • Page 28: Stack Pointer Register (Sp, Dh[1H])

    MAX31782 User’s Guide 3.1.13StackPointerRegister(SP,Dh[1h]) Initialization: This register is cleared to 000Fh on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION These four bits indicate the current top of the hardware stack, from 0h to Fh . This pointer is incremented SP .[3:0]...

  • Page 29: Data Pointer Control Register (Dpc, Eh[4H])

    MAX31782 User’s Guide 3.1.18DataPointerControlRegister(DPC,Eh[4h]) Initialization: This register is cleared to 001Ch on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION Source Data Pointer Select Bits 1:0 . These bits select one of the three data pointers as the active source point- er for the load operation .

  • Page 30: Frame Pointer Base Register (Bp, Eh[7H])

    MAX31782 User’s Guide 3.1.21FramePointerBaseRegister(BP,Eh[7h]) Initialization: This register is cleared to 0000h on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION This register serves as the base pointer for the frame pointer (FP) . The frame pointer is formed by unsigned addi- BP .[15:0]...

  • Page 31: Data Pointer 1 Register (Dp[1], Fh[7H])

    MAX31782 User’s Guide 3.1.27DataPointer1Register(DP[1],Fh[7h]) Initialization: This register is cleared to 0000h on all forms of reset . Access: Unrestricted direct read/write access . FUNCTION This register is used as a pointer to access data memory . DP[1] can be automatically incremented or dec- DP[1] .[15:0]...
  • Page 32 MAX31782 User’s Guide SECTION 4: PERIPHERAL REGISTER MODULES The MAX31782 has six peripheral register modules, Modules 0 through 5 . This section describes the MAX31782’s peripheral registers . Table 4-1 shows the MAX31782 peripheral register map . Table 4-2 explains peripheral register bit functions .
  • Page 33 MAX31782 User’s Guide MaximIntegrated 4-2 Revision 0; 8/11...
  • Page 34 MAX31782 User’s Guide MaximIntegrated 4-3 Revision 0; 8/11...
  • Page 35 MAX31782 User’s Guide MaximIntegrated   4-4 Revision 0; 8/11...

  • Page 36: Section 5: Interrupts

    MAX31782 User’s Guide SECTION 5: INTERRUPTS This section contains the following information: 5 .1 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 5 .2 Module Interrupt Identification Registers .

  • Page 37: Servicing Interrupts

    . The MAX31782 provides two ways to determine which block inside a module caused an interrupt to occur . Each module has a module interrupt identification register (MIIR) that indicates which of the module’s interrupt sources has a pend- ing interrupt .
  • Page 38 EDGE TRIGGER TACHCN1.TEXF LOCAL ENABLE TACHCN1.TACHIE NOTE: ONLY A FEW OF THE MAX31782 MODULES AND INTERRUPT SOURCES ARE SHOWN IN THIS INTERRUPT HIERARCHY FIGURE. REFER TO THE CORRESPONDING SECTIONS OF THIS USER’S GUIDE FOR MORE DETAILED INFORMATION ABOUT ALL THE POSSIBLE INTERRUPTS.
  • Page 39 MAX31782 User’s Guide Table5-1.InterruptSourcesandControlBits MODULE INTERRUPT MODULE INTERRUPT INTERRUPT INTERRUPTFLAG LOCALENABLEBIT IDENTIFICATION ENABLE IDENTIFICATION Timer B: External Trigger TB0CN .EXFB TB0CN .ETB MIIR0 .TB0 IIR .II0 IMR .IM0 Timer B: Overflow TB0CN .TFB C Master START Interrupt I2CST_M .I2CSRI I2CIE_M .I2CSRIE C Master Transmit Complete Interrupt I2CST_M .I2CTXI...
  • Page 40 The MIIR registers are implemented to indicate which particular function within a peripheral module has caused the interrupt . The MAX31782 has six peripheral modules, M0 to M5 . An MIIR register is implemented in each peripheral module . The MIIR registers are 16-bit read-only registers and all of them default to 0000h on system reset .

  • Page 41: Peripheral Module 2 Interrupt Identification Register (Miir2, M2[03H])

    I C START signal only when the CPU is operating in stop mode . As the CPU clock is not running in stop mode, this is an asynchronous interrupt . This interrupt causes the MAX31782 I2CS_WU to automatically transition from stop mode to CPU mode . The wake-up interrupt shares the same enable bits as the slave I C START interrupt I2CSRI .

  • Page 42: Peripheral Module 5 Interrupt Identification Register (Miir5, M5[18H])

    . Interrupt operation in the MAX31782 CPU is essentially a state machine generated long CALL instruction . When the interrupt handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of actions: 1) The next instruction fetch from program memory is cancelled .

  • Page 43: Interrupt Prioritization By Software

    MAX31782 User’s Guide 5.3.2InterruptPrioritizationbySoftware All interrupt sources of the MAX31782 naturally have the same priority . However, when CPU operation vectors to the programmed interrupt vector address, the order in which potential interrupt sources are interrogated is left entirely up to the user, as this often depends upon the system design and application requirements .

  • Page 44: Section 6: Analog-To-Digital Converter (Adc)

    MAX31782 User’s Guide SECTION 6: ANALOG-TO-DIGITAL CONVERTER (ADC) This section contains the following information: 6 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 6 .1 .1 Conversion Modes .

  • Page 45: Detailed Description

    . The internal channel is used exclusively to measure the die temperature . 6.1DetailedDescription 6.1.1ConversionModes The ADC in the MAX31782 can operate in three modes, which are selected using the EXTEMP and ADCH bits in the configuration register: 1) Voltage Conversion Mode...

  • Page 46: Conversion Sequencing

    MAX31782 User’s Guide 6.1.2ConversionSequencing The MAX31782 ADC performs a user-defined sequence of up to eight conversions . Each conversion in a sequence is set up using one of the eight ADC configuration registers . The configuration registers are accessed by writing to the ADDATA register when ADST .ADCFG = 1 .
  • Page 47 MAX31782 User’s Guide Table6-1.ExtendedAcquisitionTimeinTermsofADCClocks ADCCLOCKDIVIDER ADCCLOCKDIVIDER ADCCLOCKDIVIDER ADCCLOCKDIVIDER ADACQ[3:0] =16 =32 =64 =128 STARTUP SAMPLE 1 HOLD AND CONVERT SAMPLE 1 SAMPLE 2 HOLD AND CONVERT SAMPLE 2 ADACQ 19 20 1 2 3 4 5 6 7 8 9...

  • Page 48: Adc Data Reading

    6.1.5ADCInterrupts The MAX31782 provides an interrupt flag (ADST .ADDAI) that is set when conversions are complete . This flag generates an interrupt if enabled by setting the ADCN .ADDAIE interrupt enable bit . The condition that causes the ADDAI flag to be set can be selected using the ADCN .ADDAINV[1:0] bits .
  • Page 49 MAX31782 User’s Guide 6.2ADCRegisterDescriptions The ADC is controlled by ADC SFR registers . Four of the registers, ADST, ADADDR, ADCN, and ADDATA, are used for setup, control, and reading from the ADC . There are five other registers, ETS, ADCG1, ADCG5, ADVOFF, and TOEX, which are used to adjust the gains and offsets applied to ADC results .

  • Page 50: Adc Status Register (Adst)

    MAX31782 User’s Guide 6.2.2ADCStatusRegister(ADST) Register Address: M2[06h] Name — — — — ADDAT3 ADDAT2 ADDAT1 ADDAT0 — ADCONV ADDAI ADCFG ADIDX3 ADIDX2 ADIDX1 ADIDX0 Reset Access NAME DESCRIPTION 15:12 — Reserved . The user should not write to these bits .

  • Page 51: Adc Data And Configuration Register (Addata)

    MAX31782 User’s Guide 6.2.4ADCDataandConfigurationRegister(ADDATA) Register Address: M2[09h] The ADDATA register is used to set up the ADC sequence configurations and also to read the results of the ADC con- versions . If the ADST .ADCFG bit is set to 1, writing to ADDATA writes to one of the configuration registers . If ADST .
  • Page 52 MAX31782 User’s Guide ADC Differential Mode Select . In voltage mode, this bit selects the ADC conversion mode . When this bit is set to 1, the ADC conversion is in differential mode . When this bit is cleared to 0, the ADC conversion is performed in single-ended mode .

  • Page 53: External Temperature Slope Control Register (Ets)

    The ETS register changes the slope of external temperature measurements to compensate for changes in diode ideality factor . The MAX31782 is factory calibrated to work with a diode-connected 2N3904 NPN transistor with an ideality factor of 1 .004 .

  • Page 54: Adc External Temperature Offset Register (Toex)

    MAX31782 User’s Guide 6.2.6ADCExternalTemperatureOffsetRegister(TOEX) Register Address: M1[1Ah] Name Reset Access s = special, initial value is dependent on trim settings The TOEX register contains the temperature offset for the external temperature measurements . The default value of this register is -273 (Kelvin to Celsius) plus any offset that was calibrated out at the factory . This offset is applied to the raw data from the ADC prior to the value being stored into the data buffer .

  • Page 55: Adc Code Examples

    MAX31782 User’s Guide 6.3ADCCodeExamples 6.3.1OneSequenceofFourTemperatureandVoltageConversions ADCN_bit.IREFEN = 1; //enable the internal reference ADCN_bit.ADCONT = 0; //run a single conversion sequence ADST_bit.ADCFG = 1; //set ADDATA as ADCFG ADST_bit.ADIDX = 0; //ADIDX = 0, set to ADCFG[0] ADDATA = 0x08; //ADCFG[0]: Differential voltage CH0, 1.225V FS, Right Aligned ADDATA = 0x41; //ADCFG[1]: Single ended voltage CH1, 5.5V FS, Right Aligned ADDATA = 0x85; //ADCFG[2]: External temperature CH5, right aligned ADDATA = 0x86; //ADCFG[3]: Internal temperature, CH6, right aligned ADADDR_bit.ADSTART = 0; //start sequence with ADCFG[0] ADADDR_bit.ADEND = 3; //end sequence with ADCFG[3] ADST_bit.ADCONV = 1; //start the conversions while(ADST_bit.ADCONV) //wait for conversions to complete ADST_bit.ADCFG = 0; //set ADDATA to data buffer ADST_bit.ADIDX = 0; //set ADDATA to data buffer[0] ch0_volt = ADDATA; //read and store ch0 voltage to variable ch1_volt = ADDATA; //read and store ch1 voltage to variable ch5_temp = ADDATA; //read and store ch5 temperature to variable int_temp = ADDATA;...

  • Page 56: Continuous Conversion Of 16 Samples

    MAX31782 User’s Guide 6.3.2ContinuousConversionof16Samples ADCN_bit.IREFEN = 1; //enable the internal reference ADCN_bit.ADDAINV = 3; //set the interrupt flag after 16 conversions ADCN_bit.ADCONT = 1; //run continuous conversions ADST_bit.ADCFG = 1; //set ADDATA as ADCFG ADST_bit.ADIDX = 0; //ADIDX = 0, set to ADCFG[0] ADDATA = 0x08; //ADCFG[0]: Differential voltage, ch0, 1.225V FS, Right Aligned ADADDR = 0x0000; //ADSTART=0, ADEND=0, sequence is only ADCFG[0] ADST_bit.ADDAI = 0; //clear the interrupt flag ADST_bit.ADCONV = 1; //start the conversion while(!ADST_bit.ADDAI) //wait for 16 conversions to complete ADST_bit.ADCONV = 0; //stop the converter ADST_bit.ADDAI = 0; //clear the interrupt flag ADST_bit.ADCFG = 0; //set ADDATA to data buffer ADST_bit.ADIDX = 0; //set ADDATA to data buffer[0] for(i=0; i<16; i++) ADC[i] = ADDATA; //read all 16 conversions MaximIntegrated 6-13 Revision 0; 8/11...

  • Page 57: Section 7: I C-Compatible Slave Interface

    MAX31782 User’s Guide SECTION 7: I C-COMPATIBLE SLAVE INTERFACE This section contains the following information: 7 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 7 .1 .1 Default Operation .
  • Page 58 C-COMPATIBLE SLAVE INTERFACE The MAX31782 provides an I C-compatible slave controller that allows the MAX31782 to communicate with a host device . This controller can also operate as an SMBus slave . Also designed into the I C slave controller is the ability to bootload the MAX31782 with new user flash memory .

  • Page 59: Slave Address

    MAX31782 . The MAX31782 retains control of the SDA line so data can be transmit to the host . • Data Receive: The slave address matched and the R/W bit was a 0 . The host wants to write data to the MAX31782 .

  • Page 60: Transmitting Data

    Following the 8th data (least significant bit) being shifted to SDA, the SDA line is released by the MAX31782 slave controller . This allows the host to signal an ACK or NACK during the 9th clock cycle . The MAX31782 I C slave control- ler samples the acknowledge bit following the rising 9th SCL rising edge .

  • Page 61: Receiving Data

    I2CBUSY being cleared, which indicates that all the bits in I2CBUF_S have been shifted onto SDA . The detection of a NACK indicates that the host does not want to receive any additional data . The MAX31782 I C slave controller releases control of SDA following the reception of the NACK bit .

  • Page 62: Clock Stretching

    . This allows software time to inspect data that was received before responding with an appropriate acknowledge bit . Most applications that use the MAX31782’s I C slave controller need to use clock stretching . Generally the application...

  • Page 63: Section 8: I

    C interfaces, the slave (SDA and SCL) and master (MSDA and MSCL) . These are two totally separate blocks within the MAX31782 . However, both of the blocks are identical . Because of this, it is possible to operate the slave as a master and also operate the master as a slave .
  • Page 64 MAX31782 User’s Guide 7.2I CSlaveControllerRegisterDescriptions The following registers are used to control the I C slave interface, which uses the SDA and SCL pins . These registers control the I C slave interface if it is operating as either a slave or master . The bit descriptions detail how to use these registers when operating in slave mode .

  • Page 65: I 2 C Slave Status Register (I2Cst_S)

    MAX31782 User’s Guide 7.2.2I CSlaveStatusRegister(I2CST�S) Address: M2[01h] Name I2CBUS I2CBUSY — — I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI — I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI Reset Access *Set by hardware only. NAME DESCRIPTION C Slave Bus Busy . This bit is set to 1 when a START/repeated START condition is detected and cleared I2CBUS to 0 when the STOP condition is detected .

  • Page 66: I 2 C Slave Interrupt Enable Register (I2Cie_S)

    MAX31782 User’s Guide 7.2.3I CSlaveInterruptEnableRegister(I2CIE�S) Address: M2[02h] Name — — — — I2CSPIE — I2CROIE I2CGCIE I2CNACKIE — I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE Reset Access NAME DESCRIPTION 15:12 — Reserved . The user should not write to these bits .

  • Page 67: I 2 C Slave Address Register (I2Csla_S)

    MAX31782 User’s Guide 7.2.4I CSlaveAddressRegister(I2CSLA�S) Address: M2[0Fh] Name — — — — — — — — — Reset Access NAME DESCRIPTION 15:7 — Reserved . The user should not write to these bits . These address bits contain the address of the I C slave interface .
  • Page 68 MAX31782 User’s Guide 7.2.6SMBusModeSelectionRegister(SMBUS) Address: M3[04h] Name — — — — — — — — — — — — RESET_S RESET_M SMB_MOD_S SMB_MOD_M Reset Access This register contains bits that are used for both the I C slave interface (SDA and SCL) and the I C master interface (MSDA and MSCL) .
  • Page 69 MAX31782 User’s Guide SECTION 8: I C-COMPATIBLE MASTER INTERFACE This section contains the following information: 8 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 8 .1 .1 Description of Master I...

  • Page 70: Section 8: I

    8.1.3I CClockGeneration In an I C system, the master is responsible for generating the SCL signal . The MAX31782 I C master controller provides complete control over the clock rate and duty cycle . The I C master controller generates SCL from the system clock .

  • Page 71: Timeout

    MAX31782 User’s Guide there is a rise time that is determined by the capacitive loading and pullup resistance on the SCL line . When the control- ler senses the SCL line has reached a high logic level, the count for SCL High Time begins . The same is true for a falling edge .

  • Page 72: Generating A Start

    MAX31782 User’s Guide 8.1.5GeneratingaSTART To initiate a data transfer, the I C master controller must first issue a START command . The master I C controller’s flow when attempting to issue a START command is shown in Figure 8-3 . A START command is generated by setting the I2CSTART bit to 1 .

  • Page 73: Generating A Stop

    MAX31782 User’s Guide C controller starts its timeout timer if enabled (I2CTO_M ≠ 0) . If the timer When the I2CSTART bit is set to a 1, the I expires before the START can be generated, t h e I C timeout interrupt flag (I2CTOI) will be set and an interrupt generated if enabled .

  • Page 74: Transmitting Data

    • Data Receive: The I2CMODE (R/W) bit was set to a 1, indicating that the master will be receiving data from a slave . The MAX31782 releases control of SDA to allow a slave device to output data . The MAX31782 master I C controller automatically begins clocking bytes of data from the slave .

  • Page 75: Receiving Data

    MAX31782 User’s Guide Following the 8th bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the MAX31782 master controller . This allows the slave to signal an ACK or NACK during the 9th clock cycle . The MAX31782 I C master controller samples the acknowledge bit following the 9th SCL rising edge .

  • Page 76: Resetting The I

    C interfaces, the master (MSDA and MSCL) and slave (MAX31782 SDA and SCL pins) . These are two totally separate blocks within the MAX31782 . However, both of the blocks are identical . Because of this, it is possible to operate the master as a slave and also operate the slave as a master .

  • Page 77: I 2 C Master Controller Register Descriptions

    MAX31782 User’s Guide 8.2I CMasterControllerRegisterDescriptions Following are the registers that are used to control the I C master interface, which is the MSDA and MSCL pins . These registers are used to control the I C master interface if it is operating as either a master or slave . The bit descriptions below detail how to use these registers when operating in master mode .

  • Page 78: I 2 C Master Status Register (I2Cst_M)

    MAX31782 User’s Guide 8.2.2I CMasterStatusRegister(I2CST�M) Address: M1[01h] Name I2CBUS I2CBUSY — — I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI — I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI Reset Access *Set by hardware only. NAME DESCRIPTION C Master Bus Busy . This bit is set to 1 when a START/repeated START condition is detected and I2CBUS cleared to 0 when the STOP condition is detected .

  • Page 79: I 2 C Master Interrupt Enable Register (I2Cie_M)

    MAX31782 User’s Guide 8.2.3I CMasterInterruptEnableRegister(I2CIE�M) Address: M1[02h] Name — — — — I2CSPIE — I2CROIE I2CGCIE I2CNACKIE — I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE Reset Access NAME DESCRIPTION 15:12 — Reserved . The user should not write to these bits .

  • Page 80: I 2 C Master Clock Control Register (I2Cck_M)

    MAX31782 User’s Guide 8.2.5I CMasterClockControlRegister(I2CCK�M) Address: M1[0Dh] Name I2CCKH7 I2CCKH6 I2CCKH5 I2CCKH4 I2CCKH3 I2CCKH2 I2CCKH1 I2CCKH0 I2CCKL7 I2CCKL6 I2CCKL5 I2CCKL4 I2CCKL3 I2CCKL2 I2CCKL1 I2CCKL0 Reset Access NAME DESCRIPTION These bits define the high period of the clock . This period is defined by the number of system clocks .

  • Page 81: Smbus Mode Selection Register (Smbus)

    MAX31782 User’s Guide 8.2.8SMBusModeSelectionRegister(SMBUS) Address: M3[04h] — — — — — — — — — — — Name — RESET_S RESET_M SMB_MOD_S SMB_MOD_M Reset Access This register contains bits that are used for both the I C slave interface (SDA and SCL) and the I C master interface (MSDA and MSCL) .

  • Page 82: Section 9: Pwm Outputs

    MAX31782 User’s Guide SECTION 9: PWM OUTPUTS This section contains the following information: 9 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9 .1 .1 PWM Pin Mapping and GPIO Muliplexing .
  • Page 83 SECTION 9: PWM OUTPUTS The MAX31782 provides six independent PWM output pins that can be used for power-supply margining or fan speed control . When the PWM output functionality of a pin is disabled, that pin can be used as a general-purpose input/output (GPIO) .
  • Page 84 The PWM can provide up to 16-bit resolution of the frequency or duty cycle . A timed setting or clearing of the PWM .n pin can also be generated without the need for the MAX31782 to time the event or use GPIO . This is accomplished by set- ting the compare register (PWMCn) to a value greater than the reload register (PWMRn) .
  • Page 85 MAX31782 User’s Guide 9.1.3NormalPWMOutputOperation When operating in PWM output mode and configured for up count (DCEN = 0), the value in PWMVn is incremented until it reaches the reload value, PWMRn . At this point, PWMVn reloads with 0000h, the TFB flag is set (which can generate an interrupt if enabled), and counting continues .
  • Page 86 MAX31782 User’s Guide 9.1.4Up/DownCountPWMOutputOperation The PWM can also operate in an up/down count configuration by setting DCEN = 1 . The value in PWMVn counts upward until it reaches the value in the reload register (PWMRn) . On the next cycle the count reverses direction and starts count- ing down .
  • Page 87 MAX31782 User’s Guide 9.2PWMOutputRegisterDescriptions The following peripheral registers are used to control the PWM outputs of the MAX31782 . Each of the six independent PWM outputs has four associated registers . Since there are six independent PWM outputs, the registers are described in a batch manner .
  • Page 88 MAX31782 User’s Guide 9.2.2PWMValueRegister(PWMVn) The PWM value register, PWMVn, holds the 16-bit value of the PWM’s counter . Enabling or disabling the PWM with the PWMEN bit does not reset the PWMVn register . The PWMVn register must be cleared by software . This register is cleared to 0000h on all forms of reset and has unrestricted read/write access .

  • Page 89: Section 10: Fan Tachometer

    MAX31782 User’s Guide SECTION 10: FAN TACHOMETER This section contains the following information: 10 .1 Fan Tachometer Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10 .2 Timer/Fan Tachometer Register Descriptions .
  • Page 90 SECTION 10: FAN TACHOMETER The MAX31782 provides six independent fan tachometers that can be used to monitor the speed of six fans indepen- dently . When the fan tachometer functionality of a pin is disabled, that pin can be used as a general-purpose input/ output (GPIO) .
  • Page 91 Fan Frequency = Tachometer Clock/TACHR = 250kHz/1000h = 61Hz, which equals 3660 RPM 10.2Timer/FanTachometerRegisterDescriptions The following peripheral registers are used to control the fan tachometer of the MAX31782 . Each of the six indepen- dent tachometers has three associated registers . Because there are six independent tachometers, the registers are described in a batch manner .
  • Page 92 MAX31782 User’s Guide 10.2.1TachometerControlRegister(TACHCNn) The tachometer control register, TACHCNn, is used to set up and start the tachometer, and is also where tachometer interrupt flags are located . It should be noted that the user should not modify the reserved bits in the TACHCNn regis- ters .
  • Page 93 When the tachometer’s pin functionality is disabled (TEXEN = 0), that pin can be used as a GPIO . The tachometer pins are mapped to GPIO port P2[5:0] . Table 10-2 shows the mapping of the MAX31782 tachometer pins . Refer to SECTION 11: General-Purpose Input/Output (GPIO) Pins for information on using the tachometer pins as GPIO .
  • Page 94 MAX31782 User’s Guide 10.4TachometerCodeExample The following pseudocode shows how to set up tachometer 0 . This example does not generate any interrupts, but instead the captured tachometer value can be periodically polled by software . Tachometer setup: TACHCN0_bit.TPS = 3; //tachometer clock is sysclk / 64 or 62.5kHz TACHCN0_bit.TRPS = 1;...

  • Page 95: Section 11: General-Purpose Input/Output (Gpio) Pins

    MAX31782 User’s Guide SECTION 11: GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS This section contains the following information: 11 .1 GPIO Port 1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 11 .1 .1 GPIO Direction Register Port 1 (PD1) .
  • Page 96 SECTION 11: GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS The MAX31782 provides general-purpose input/output (GPIO) functionality on 21 pins . In addition to the GPIO function- ality, each of these pins is multiplexed with at least one other function, which is classified as either a special function or alternate function .
  • Page 97 MAX31782 User’s Guide Table11-1.GPIOPinsandMultiplexedFunctions PORT ALTERNATE ALTERNATE SPECIAL RESET NAME SPECIALFUNCTIONENABLE INDEX FUNCTION(S) FUNCTIONENABLE FUNCTION STATE PWM .0 P1 .0 — — PWM .0 PWMCN0 .PWMCR or PWMCS = 1 GPIO PWM .1 P1 .1 — — PWM .1 PWMCN1 .PWMCR or PWMCS = 1 GPIO PWM .2...

  • Page 98: Gpio Port 1 Register Descriptions

    MAX31782 User’s Guide 11.1GPIOPort1RegisterDescriptions Port 1 provides six GPIO pins that are multiplexed with PWM functionality . The PWM function is enabled when either the PWMCNn .PWMCR or PWMCS bits are a 1, where n = 0 to 5 . If both of these bits are a 0, the pin operates as a GPIO .

  • Page 99: Gpio Port 2 Register Descriptions

    MAX31782 User’s Guide 11.2GPIOPort2RegisterDescriptions Port 2 provides eight GPIO pins that are multiplexed with the tachometers and master I C port . This port does not provide GPIO interrupts . The tachometer function is an alternate function . This means that the GPIO functions are fully supported, even when the pin is operating as a tachometer .

  • Page 100: Gpio Port 6 Register Descriptions

    MAX31782 User’s Guide 11.3GPIOPort6RegisterDescriptions Port 6 provides seven GPIO pins that are multiplexed with the test access port (TAP), Timer B, and slave I C port . See Table 11-1 for more details about the multiplexed functions and how to enable or disable these functions .

  • Page 101: Gpio Input Register For Port 6 (Pi6)

    MAX31782 User’s Guide 11.3.3GPIOInputRegisterforPort6(PI6) Name PI6_7 PI6_6 — PI6_4 PI6_3 PI6_2 PI6_1 PI6_0 Reset Access PI6 is an 8-bit register that contains the data that is applied to the GPIO pins . The PI6 input register contains valid input data even when the pin is not operating as a GPIO . The reset value for this register is dependent on the logical states applied to the pins .

  • Page 102: Gpio Code Example

    MAX31782 User’s Guide 11.4GPIOCodeExample //set pin 6.4 as a high output PD6 |= 0x10; //set direction PD6.4 to 1 for an output PO6 |= 0x10; //set the output PO6.4 high //set pin 6.4 as a high-impedance input PD6 &= ~0x10; //set direction PD6.4 to 0 for input PO6 &= ~0x10; //set PO6.4 low to disable weak pullup //enable the pin 6.4 weak pullup PD6 &= ~0x10; //set direction PD6.4 to 0 for input PO6 |= 0x10; //set PO6.4 high to enable weak pullup MaximIntegrated  11-8 Revision 0; 8/11...

  • Page 103: Section 12: Timer B Module

    MAX31782 User’s Guide SECTION 12: TIMER B MODULE This section contains the following information: 12 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 12 .1 .1 Auto-Reload Mode .

  • Page 104: Detailed Description

    SECTION 12: TIMER B MODULE The MAX31782 provides one Timer B module that can be configured to provide different timer, counter, clock, or PWM functions . The Timer B uses the TBB and TBA pins, which are also used for JTAG and GPIO operation .

  • Page 105: Auto-Reload Mode

    MAX31782 User’s Guide 12.1.1Auto-ReloadMode The 16-bit auto-reload mode of Timer B is established by clearing the CP/RLB bit to 0 . In this mode, the timer performs a simple 16-bit timer or counter function that is reset to 0000h when a match between the Timer B count value register (TB0V) and the Timer B capture/reload register (TB0R) occurs .

  • Page 106: Up/Down Count With Auto-Reload

    MAX31782 User’s Guide 12.1.2Up/DownCountwithAuto-Reload The 16-Bit up/down count auto-reload mode is enabled by clearing the capture/reload bit (CP/RLB) to 0 and setting the down count enable bit (DCEN) to 1 . This mode is illustrated in Figure 12-2 . When DCEN is set to 1 the Timer B either counts up or down, depending upon the state of the TBB pin .

  • Page 107: Capture Mode

    MAX31782 User’s Guide 12.1.3CaptureMode The Timer B 16-bit capture mode is configured by setting the CP/RLB bit to 1 . A block diagram of this mode is shown Figure 12-3 . In capture mode, the Timer B can be clocked either by a prescaled version of the system clock or fall- ing edges of the TBA pin .

  • Page 108: Clock Output Mode

    MAX31782 User’s Guide 12.1.4ClockOutputMode The Timer B can be configured to drive a clock output on the TBA pin as shown in Figure 12-4 . For the timer to operate in this mode, the capture/reload select bit (CP/RLB) and the counter/timer select bit (C/TB) must be cleared to 0 and the Timer B output enable bit (TBOE) must be set to 1 .

  • Page 109: Pwm Output Mode

    MAX31782 User’s Guide 12.1.5PWMOutputMode The PWM output mode is enabled when the Timer B is enabled (TRB = 1) and either the TBCS or TBCR bit is set to 1 . Table 12-3 describes how these bits determine the specific PWM operation . When operating as a PWM output, the Timer B can provide up to 16-bit resolution of the PWM frequency or duty cycle .

  • Page 110: Up Count Pwm Output Mode

    MAX31782 User’s Guide 12.1.5.1UpCountPWMOutputMode When operating in PWM output mode and configured for up count (DCEN = 0), the value in TB0V is incremented until it reaches the reload value, TB0R . At this point, TB0V is reloaded with 0000h, the TFB flag is set (which can generate an interrupt if enabled), and counting continues .

  • Page 111: Up/Down Count Pwm Output Mode

    MAX31782 User’s Guide 12.1.5.2Up/DownCountPWMOutputMode The Timer B can also operate in an up/down count configuration when in PWM output mode by setting DCEN = 1 . The timer counts upward until it reaches the value in the reload register (TB0R) . On the next cycle, it reverses the count direction and starts counting down .

  • Page 112: Timer B Register Descriptions

    MAX31782 User’s Guide 12.2TimerBRegisterDescriptions The following peripheral registers are used to control the Timer B timer and counter functions . Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal) .

  • Page 113: Timer B Value Register (Tb0V)

    MAX31782 User’s Guide NAME DESCRIPTION Timer B Output Enable . Setting this bit to 1 enables the clock output function on the TBA pin if C/TB TBOE = 0 . Clearing this bit to 0 allows the TBA pin to function as either a standard GPIO pin or a counter input for the Timer B .

  • Page 114: Timer B Code Examples

    MAX31782 User’s Guide 12.3TimerBCodeExamples 12.3.1Auto-ReloadMode Creating a 10ms interrupt (10ms at 4MHz = 40,000 clock cycles): TB0R = 40000; //set the Reload Register TB0V = 0x0000; //clear the Value Register TB0CN_bit.CPnRLB = 0; //clear for auto reload TB0CN_bit.ETB = 1; //enable the interrupt TB0CN_bit.TRB = 1; //enable the Timer B operation 12.3.2ClockOutputMode Creating a 100kHz clock on the TBA pin: TB0CN_bit.CPnRLB = 0; //clear for reload TB0CN_bit.TBPS = 1; //prescaler: divide sysclk/4 for 1MHz Timer B Clock TB0R = 4;...

  • Page 115: Section 13: Supply Voltage Monitor

    Note that the SVTH[3:0] bits can only be modified when SVMEN = 0 . Writing to these bits is ignored if SVMEN = 1 . SVM thresholds of 2 .3V and 2 .5V have no actual use because the MAX31782 enters brownout at 2 .5V .

  • Page 116: Section 14: Hardware Multiplier

    MAX31782 User’s Guide SECTION 14: HARDWARE MULTIPLIER This section contains the following information: 14 .1 Hardware Multiplier Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2 14 .2 Hardware Multiplier Controls .

  • Page 117: Hardware Multiplier Organization

    MAX31782 User’s Guide SECTION 14: Hardware Multiplier The hardware multiplier module can be used by the MAX31782 to support high-speed multiplications . The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width .

  • Page 118: Hardware Multiplier Controls

    MAX31782 User’s Guide 14.2HardwareMultiplierControls The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS, MSUB, MMAC, and SQU . The number of operands that must be loaded to trigger the specified operation is dictated by the OPCS bit setting, except when the square function is enabled (SQU = 1) .

  • Page 119: Accessing The Multiplier

    MAX31782 User’s Guide most significant bit of the MC register occurs . For a signed two’s-complement multiply-accumulate/subtract operations, the OF bit is set when the carry-out/borrow-in from the most significant magnitude position of the MC register is differ- ent from the carryout/ borrow-in of the sign position of the MC register .

  • Page 120: Hardware Multiplier Peripheral Registers

    MAX31782 User’s Guide 14.5HardwareMultiplierPeripheralRegisters The hardware multiplier registers are detailed in the following sections . Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal) .

  • Page 121: Multiplier Control Register (Mcnt)

    MAX31782 User’s Guide 14.5.1MultiplierControlRegister(MCNT) Name OPCS MSUB MMAC Reset Access NAME DESCRIPTION OverflowFlag . This bit is set to logic 1 when an overflow occurred for the last operation . This bit can be set for accumulation/subtraction operations or unsigned multiply-negate attempts . This bit is automatically cleared to 0 following a reset, starting a multiplier operation, or setting of the CLD bit to 0 .
  • Page 122 MAX31782 User’s Guide 14.5.2MultiplierOperandARegister(MA) Name MA .15 MA .14 MA .13 MA .12 MA .11 MA .10 MA .9 MA .8 MA .7 MA .6 MA .5 MA .4 MA .3 MA .2 MA .1 MA .0 Reset Access MultiplierOperandARegister.This operand A register is used by the application code to load 16-bit values for mul- tiplier operations .
  • Page 123 MAX31782 User’s Guide 14.5.7MultiplierReadRegister1(MC1R) Name MC1R .15 MC1R .14 MC1R .13 MC1R .12 MC1R .11 MC1R .10 MC1R .9 MC1R .8 MC1R .7 MC1R .6 MC1R .5 MC1R .4 MC1R .3 MC1R .2 MC1R .1 MC1R .0 Reset Access MultiplierReadRegister1:The MC1R register represents bytes 3 and 2 from the result of the last operation when MCW = 1 or the last operation was a multiply or multiply-negate .
  • Page 124 MAX31782 User’s Guide ;Signed Multiply-Accumulate 16-bit x 16-bit ; MC2:0=0000_0100_0001h move MCNT, #02h ; SUS=0 (signed) move MA, #F001h move MB, #1001h ; MC1R:MC0R= FF00_0003h ; MC2:0=0000_0000_0002h ;Unsigned Multiply-Subtract 16-bit x 16-bit ; MC2:0=0000_0100_0001h move MCNT, #07h ; MMAC=1, MSUB=1, SUS=1 (unsigned) move MA, #0FFFh move MB, #1001h ; MC1R:MC0R=FF00_0003h ; MC2:0=0000_0000_0002h ;Signed Multiply-Subtract 16-bit x 16-bit ; MC2:0=0000_0100_0001h move MCNT, #06h ; MMAC=1, MSUB=1, SUS=0 (signed) move MA, #F001h move MB, #1001h ; MC1R:MC0R= 02FF_FFFFh ; MC2:0=0000_0200_0000h ;Signed Multiply Negate 16-bit x 16-bit move MCNT, #24h ; CLD=1, MSUB=1, SUS=0 (signed) move MA, #F001h ; MC2:0=0000_0000_0000h...

  • Page 125: Section 15: Watchdog Timer

    MAX31782 User’s Guide SECTION 15: WATCHDOG TIMER This section contains the following information: 15 .1 Watchdog Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-3 15 .1 .2 Watchdog Timer Interrupt Operation .
  • Page 126 MAX31782 User’s Guide SECTION 15: WATCHDOG TIMER The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system supervisor . As shown in Figure 15-1, the timer is driven by the main system clock and is supplied to a series of dividers .
  • Page 127 RWT bit or clear the EWT bit . This can occur at any time during the watchdog timer interval or the addi- tional 512 system clock cycles after WDIF is set . At the end of the 512 system clock cycles the MAX31782 is reset .
  • Page 128 Enable Watchdog Timer Reset . If this bit is set to 1 when the watchdog timer elapses, the watchdog resets the MAX31782 512 system clock cycles later unless action is taken to disable the reset event . Clearing this bit to 0 prevents a watchdog reset from occurring but does not stop the watchdog timer or prevent watch- dog interrupts from occurring if EWDI = 1 .

  • Page 129: Section 16: Test Access Port (Tap)

    MAX31782 User’s Guide SECTION 16: TEST ACCESS PORT (TAP) This section contains the following information: 16 .1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3 16 .2 TAP State Control .

  • Page 130: Tap Controller

    The MAX31782 incorporates a test access port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface . The TAP can be used by the MAX31782 to support in-system programming and/ or in-circuit debug . The TAP is compatible with the JTAG IEEE standard 1149 and is formed by four interface signals...
  • Page 131 MAX31782 User’s Guide 16.1TAPController The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signals . Based on its state transition, the controller provides the clock and control sequence for TAP operation . The performance of the TAP is dependent on the TCK clock frequency .

  • Page 132: Tap State Control

    MAX31782 User’s Guide 16.2TAPStateControl The TAP provides an independent serial channel to communicate synchronously with the host system . The TAP state control is achieved through host manipulation of the test mode select (TMS) and test clock (TCK) signals . The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states .

  • Page 133: Dr-Scan Sequence

    The Bypass (IR[2:0] = 011b, 101b, or 111b) instruction is also mandated by the JTAG standard . The Bypass instruction is fully implemented by the MAX31782 to provide a minimum length serial data path between the TDI and the TDO pins .

  • Page 134: Communication Via Tap

    . In-circuit debug or in-system programming commands and data can be exchanged between the host and the MAX31782 by operating in the data register portion of the state sequence (i .e ., DR-Scan) . The TAP retains the private instruction that was loaded into IR[2:0] until a new instruction is shifted in, or until the TAP controller returns to the Test-Logic-Reset state .
  • Page 135 MAX31782 User’s Guide CONTROL STATE SHIFT DON'T CARE OR UNDEFINED DON'T CARE OR UNDEFINED REGISTER PARALLEL OLD DATA NEW DATA OUTPUT INSTRUCTION DON'T CARE OR UNDEFINED DATA REGISTER REGISTER ENABLE Figure 16-4. TAP Controller Debug Mode DR-Scan Example MaximIntegrated 16-7...

  • Page 136: Section 17: In-Circuit Debug Mode

    MAX31782 User’s Guide SECTION 17: IN-CIRCUIT DEBUG MODE This section contains the following information: 17 .1 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3 17 .1 .1 Breakpoint Registers .
  • Page 137 TDO output during DR-Scan sequences . All background and debug mode communication (commands, data input/ output, and status) occurs via this serial channel . Each 10-bit exchange of data between the host and the MAX31782 internal hardware is composed of two status bits and a single byte of command or data . The 10-bit word is always...

  • Page 138: Background Mode Operation

    JTAG in-system programming also requires use of the 10-bit debug shift register and, if enabled (JTAG_SPE = 1, PSS[1:0] = 0), takes precedence over background mode communication . When operating in background mode, the status bits are always cleared to 00b (non-debug), which indicates that the MAX31782 is ready to receive background mode commands .
  • Page 139 MAX31782 User’s Guide Table17-2.BackgroundModeCommands(continued) OPCODE COMMAND OPERATION ReaddatafromtheICDA. The contents of the ICDA register are loaded into the debug shift reg- 0000–0011 Read ICDA ister through the ICDB register for host read . This command requires two follow-on transfer cycles with the least significant byte first .

  • Page 140: Breakpoint Registers

    MAX31782 User’s Guide 17.1.1BreakpointRegisters The MAX31782 incorporates six breakpoint registers (BP0–BP5) that are configurable by the host for establishing different types of breakpoint mechanisms . The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable as program memory address breakpoints . When enabled, the debug engine forces a break when a match between the breakpoint register and the program memory execution address occurs .
  • Page 141 MAX31782 User’s Guide 17.1.1.4Breakpoint3Register(BP3) Name BP3 .15 BP3 .14 BP3 .13 BP3 .12 BP3 .11 BP3 .10 BP3 .9 BP3 .8 BP3 .7 BP3 .6 BP3 .5 BP3 .4 BP3 .3 BP3 .2 BP3 .1 BP3 .0 Reset Access s = special The breakpoint 3 register is accessible only via background mode read/write commands .

  • Page 142: Using Breakpoints

    . When a breakpoint match occurs, the debug engine forces a break and the MAX31782 enters Debug Mode . If a break- point match occurs on an instruction that activates the PFX register, the break is held off until the prefixed operation completes .

  • Page 143: Debug Mode Commands

    1 . The ROD bit is reset by the debug engine when it recognizes the done condition . Table 17-3 shows the debug mode commands supported by the MAX31782 . Note that background mode com- mands are supported inside debug mode, however, the documentation of these commands can be found in the 17.1 Background Mode Operation...
  • Page 144 MAX31782 . Writing to the IP register alters the address that execution resumes from when the debugging engine exits .

  • Page 145: Read Register Map Command Host-Rom Interaction

    MAX31782 User’s Guide Table17-3.DebugModeCommands(continued) OPCODE COMMAND OPERATION Unlockthepasswordlock.This command requires 32 follow-on transfer cycles each containing a byte value to be compared with the program memory password for the purpose of clearing the PWL Unlock pass- bit and granting access to protected debug and loader functions . When this command is received, 0010–1000...

  • Page 146: Single Step Operation (Trace)

    MAX31782 User’s Guide Table17-4.OutputfromReadRegisterMapCommand WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER ---- ---- PWMC0 PWMC2 MCNT A[3] I2CST_M I2CST_S PWMR0 PWMR2 A[4] ---- I2CIE_M I2CIE_S PWMC1 PWMC3 A[5] MIIR0 MIIR2 PWMR1 PWMR3 A6[]...

  • Page 147: Return

    MAX31782 User’s Guide Note that the trace operation uses a return address from the stack as a legitimate address for program fetching . The host must maintain consistency of program flow during the debug process . The Instruction Pointer is automatically incremented after each trace operation, thus a new return address is pushed onto the stack before returning the control to the debug engine .
  • Page 148 17.3In-CircuitDebugPeripheralRegisters The following peripheral registers are used to control the in-circuit debug mode of the MAX31782 . Addresses of regis- ters are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal) .

  • Page 149: In-Circuit Debug Control Register (Icdc, M2[1Ah])

    MAX31782 User’s Guide 17.3.3In-CircuitDebugControlRegister(ICDC,M2[1Ah]) Name REGE CMD3 CMD2 CMD1 CMD0 Reset Access r = read, s = special NAME DESCRIPTION Debug Mode Enable (DME) . When this bit is cleared to 0, background mode commands may be executed, but breakpoints are disabled . When this bit is set to 1, breakpoints are enabled while background mode commands still may be entered .

  • Page 150: In-Circuit Debug Flag Register (Icdf, M2[1Bh])

    MAX31782 User’s Guide 17.3.4In-CircuitDebugFlagRegister(ICDF,M2[1Bh]) Name PSS1 PSS0 JTAG_SPE Reset Access r = read, s = special NAME DESCRIPTION Reserved Reserved . Do not write to these bits . Programming Source Select Bits [1:0] . These bits are used to select a programming interface during...
  • Page 151 MAX31782 User’s Guide 17.3.6In-CircuitDebugAddressRegister(ICDA,M2[1Dh]) Name ICDA .15 ICDA .14 ICDA .13 ICDA .12 ICDA .11 ICDA .10 ICDA .9 ICDA .8 ICDA .7 ICDA .6 ICDA .5 ICDA .4 ICDA .3 ICDA .2 ICDA .1 ICDA .0 Reset Access This register is used by the debug engine to store addresses so that ROM code can view that information . This register is also used by the debug engine as a mask register to mask out don’t care bits in the ICDD register when BP5 is used...

  • Page 152: Section 18: In-System Programming

    MAX31782 User’s Guide SECTION 18: IN-SYSTEM PROGRAMMING This section contains the following information: 18 .1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3 18 .1 .1 Password Protection .
  • Page 153 MAX31782 User’s Guide LIST OF FIGURES Figure 18-1 . Entering Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3 Figure 18-2 .

  • Page 154: Detailed Description

    18.1DetailedDescription Following every reset, device ROM code is executed that determines if the MAX31782 should enter into a bootloader mode . First, the ICDF register, which is not cleared by a reset, is read to see if the system programming enable (SPE) bit is set .

  • Page 155: Password Protection

    18.1.1 Password Protection for more details about the password . If there is not a valid password, the MAX31782 ROM code assumes that the program memory is blank and the device has never been programmed . The ROM code sets the I2C_SPE bit and the PSS[1:0] bits to 01 and then enters I C bootloader operation .

  • Page 156: Entering I

    C bootloader, the host must first write slave address 34h with data F0h and then issue a STOP command . When the STOP command is received, the I C _SPE bit is set . The MAX31782 must then be reset . This can be done using either the RST pin or by using the I C self-reset .

  • Page 157: I 2 C System Programming Buffer Register (I2C_Spb)

    . When I2C_SPE = 1, the I C bootstrap loader is activated to perform a bootstrap loader function . Also, if the MAX31782 does not contain a valid password, this bit is set during reset, followed by entry into the I C bootstrap loader .

  • Page 158: C Bootloader Protocol

    C communication takes place on the default I C slave address 36h . When writ- ing data to the MAX31782, slave address 36h (R/W bit = 0) is used . To read data from the MAX31782 I C bootloader, slave address 37h (R/W bit = 1) is used . The I C bootloader does not return the status bits that are available from the JTAG bootloader .

  • Page 159: Bootloader Commands

    18.3BootloaderCommands Commands for the MAX31782 loader are grouped into families . All bootloader commands begin with a single command byte . The upper 4 bits of this command byte define the command family (from 0 to 15), while the lower 4 bits define the specific command within that family .

  • Page 160: Command 02H-Master Erase

    MAX31782 User’s Guide 18.3.3Command02h—MasterErase Byte1 Byte2 Byte3 Byte4 Command Return DummyRX Input Output This command erases (sets to FFFFh) all words in the program flash memory and writes all words in the data SRAM to zero . This command is not password protected . After this command completes, the password lock bit is automati- cally cleared, allowing access to all bootloader commands .

  • Page 161: Command 05H-Get Supported Commands

    . If bit 0 is set to 1, it indicates that Family 0 is supported . If bit 1 is set to 1, it indicates that Family 1 is supported . The value returned by the MAX31782 is 403Fh, indicating that command families 0, 1, 2, 3, 4, 5 and E are supported .

  • Page 162: Command 08H-Get Loader Version

    00h . Memory locations in flash that have been previously loaded must be erased (Master Erase or Page Erase command) before they can be loaded with a new value . The MAX31782 uses a little-endian memory architecture where the least significant byte of each word is loaded first .

  • Page 163: Command 11H-Load Data

    This command writes (Length) bytes of data into the data SRAM starting at byte address (AddressH:AddressL) . The MAX31782 uses a little-endian memory architecture where the least significant byte of each word is loaded first . For example, if you load bytes (11h, 22h, 33h, 44h) starting at address 0000h, the first two words of memory space are written to 2211h, 4433h .

  • Page 164: Command 30H-Crc Code

    MAX31782 User’s Guide 18.3.16Command30h—CRCCode Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte9 Byte10 Byte11 Data Data Data Data Data Dummy Command DataIn DataIn Return Input AddrL AddrH LengthL LengthH Output CRCL CRCH This command returns the CRC-16 value (CRCH:CRCL) of the (LengthH:LengthL) bytes of program flash starting at (AddrH:AddrL) .

  • Page 165: Command 50H-Load And Verify Code

    This command erases (programs to FFFFh) all words in a 256 word (512 byte) page of the program flash memory . The MAX31782 has 128 pages of flash . The input PageNum indicates which page to erase . For example, PageNum = 1 would erase byte addresses 000h through 1FFh and PageNum = 2 would erase byte addresses 200h through 3FFh .

  • Page 166: Section 19: Programming

    MAX31782 User’s Guide SECTION 19: PROGRAMMING This section contains the following information: 19 .1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2 19 .2 Prefixing Operations .
  • Page 167 SECTION 19: PROGRAMMING The following section provides a programming overview of the MAX31782 . For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide .
  • Page 168 . 19.3ReadingandWritingRegisters All functions in the MAX31782 are accessed through registers, either directly or indirectly . This section discusses load- ing registers with immediate values and transferring values between registers of the same size and different sizes .
  • Page 169 MAX31782 User’s Guide 19.3.4MovingValuesBetweenRegistersofDifferentSizes Before covering some transfer scenarios that might arise, a special register must be introduced that will be used in many of these cases . The 16-bit General Register (GR) is expressly provided for performing byte singulation of 16-bit words .
  • Page 170 MAX31782 User’s Guide High(16-bitdestination)←8-bitsource To modify only the high byte of a given 16-bit destination, the 16-bit register should be moved into the GR register such that the low byte can be singulated and the high byte can be written exclusively . Additional cycles are required if the destination index is greater than 0Fh or if the source index is greater than 0Fh .
  • Page 171 19.5UsingtheArithmeticandLogicUnit The MAX31782 provides a 16-bit ALU, which allows operations to be performed between the active accumulator and any other register . The MAX31782 provides 16 accumulator registers, of which any one may be selected as the active accumulator .
  • Page 172 MAX31782 User’s Guide • MOVE Acc, src (Copy data from source to active accumulator) • MOVE dst, Acc (Copy data from active accumulator to destination) • MOVE Acc, Acc (Recirculation of active accumulator contents) • XCHN (Exchange nibbles within each byte of active accumulator) •...
  • Page 173 MAX31782 User’s Guide For this example, assume that all 16 accumulator registers are initially set to zero . move AP, #02h ; select A[2] as active accumulator move APC, #02h ; auto-increment AP[1:0] modulo 4 A[0] A[1] A[2] A[3] 0000 0000 0000 0000 add #01h 0000 0000 0001 0000 add #02h...
  • Page 174 MAX31782 User’s Guide 19.5.5ALUBitOperationsUsingOnlytheActiveAccumulator The following operations operate on single bits of the current active accumulator in conjunction with the Carry flag . Any of these operations may use an Acc bit from 0 to 15 . move C, Acc.0 ; copy bit 0 of accumulator to Carry move Acc.5, C...
  • Page 175 MAX31782 User’s Guide 19.6.3EqualsFlag The Equals flag (PSF .0) is a static flag set by the CMP instruction . When the source given to the CMP instruction is equal to the active accumulator, the Equals flag is set to 1 . When the source is different from the active accumulator, the Equals flag is cleared to 0 .
  • Page 176 • SUBB src (Subtract source and Carry from active accumulator) 19.7ControllingProgramFlow The MAX31782 provides several options to control program flow and branching . Jumps may be unconditional, con- ditional, relative, or absolute . Subroutine calls store the return address on the hardware stack for later return . Built-in counters and address registers are provided to control looping operations .
  • Page 177 MAX31782 User’s Guide 19.7.3ConditionalJumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S) . Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command .
  • Page 178 MAX31782 User’s Guide 19.7.5LoopingOperations Looping over a section of code can be performed by using the conditional jump instructions . However, there is built-in functionality, in the form of the ‘DJNZ LC[n], src’ instruction, to support faster, more compact looping code with separate loop counters .
  • Page 179 19.8HandlingInterrupts Handling interrupts in the MAX31782 is a three-part process . First, the location of the interrupt handling routine must be set by writing the address to the 16-bit Interrupt Vector (IV) register . This register defaults to 0000h on reset, but this will usually not be the desired location since this will often be the location of reset/power-up code .
  • Page 180 19.8.1ConditionalReturnfromInterrupt Similar to the conditional returns, the MAX31782 also supports a set of conditional return from interrupt operations . Based upon the value of one of the status flags, the CPU can conditionally pop the stack, clear the INS bit to 0, and begin execution at the address popped from the stack .
  • Page 181 The @SP-- mnemonic can be used by the MAX31782 so that stack values may be used directly by ALU operations (e .g . ADD src, XOR src, etc .) without requiring that the value be first popped into an intermediate register or accumulator .
  • Page 182 MAX31782 User’s Guide Either of the data pointers may be post-incremented or post-decremented following any read or may be pre-increment- ed or predecremented before any write access by using the following syntax . move A[0], @DP[0]++ ; increment DP[0] after read move @++DP[0], A[1] ; increment DP[0] before write move A[5], @DP[1]-- ; decrement DP[1] after read...
  • Page 183 MAX31782 User’s Guide Once the pointer selection has been made, it remains in effect until: • The source data pointer select bits are changed via the explicit or implicit methods described above (i .e ., another data pointer is selected for use) .

  • Page 184: Section 20: Instruction Set Summary

    MAX31782 User’s Guide SECTION 20: INSTRUCTION SET SUMMARY Table20-1.InstructionSetSummary 16-BITINSTRUCTION STATUSBITS APINC/ MNEMONIC DESCRIPTION NOTES WORD AFFECTED AND src f001 1010 ssss ssss S, Z Acc ← Acc AND src OR src f010 1010 ssss ssss S, Z Acc ← Acc OR src XOR src Acc ← Acc XOR src...
  • Page 185 MAX31782 User’s Guide Table20-1.InstructionSetSummary(continued) 16-BITINSTRUCTION STATUSBITS APINC/ MNEMONIC DESCRIPTION NOTES WORD AFFECTED {L/S}JUMP src f000 1100 ssss ssss IP ← IP + src or src {L/S}JUMP C, src f010 1100 ssss ssss If C=1, IP ← (IP + src) or src {L/S}JUMP NC, src If C=0, IP ← (IP + src) or src...
  • Page 186 MAX31782 User’s Guide ADD/ADDCsrc Add/AddwithCarry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator . The ADDC instruction additionally includes the Carry (C) Status Flag in the sum- mation . For the complete list of src specifiers, reference the MOVE instruction .
  • Page 187 MAX31782 User’s Guide ANDsrc LogicalAND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data . For the complete list of src specifiers, reference the MOVE instruction . Because the source field is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources .
  • Page 188 MAX31782 User’s Guide {L/S}CALLsrc {Long/Short}CalltoSubroutine Description: Performs a call to the subroutine destination specified by src . The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words) . The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address .
  • Page 189 MAX31782 User’s Guide CMPsrc CompareAccumulator Description: Compare for equality between the active accumulator and the least significant byte of the speci- fied src . Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources .
  • Page 190 MAX31782 User’s Guide CPLC ComplementCarryFlag Description: Logically complements the Carry (C) Flag . StatusFlags: C ← ~C Operation: Encoding: 1101 1010 0010 1010 Example(s): ; C = 0 CPL C ; C ← 1 {L/S}DJNZLC[n],src DecrementCounter,{Long/Short}JumpNotZero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) reg- ister .
  • Page 191 MAX31782 User’s Guide {L/S}JUMPsrc Unconditional{Long/Short}Jump Description: Performs an unconditional jump as determined by the src specifier . The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words) . The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address . The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP .
  • Page 192 MAX31782 User’s Guide {L/S}JUMPC/{L/S}JUMPNC,src, Conditional {Long/Short} Jump on Status Flag L/S}JUMPZ/{L/S}JUMPNZ,src, {{L/S}JUMPE/{L/S}JUMPNE,src, {L/S}JUMPS,src Performs conditional branching based upon the state of a specific processor status flag . JUMP C Description: results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear . JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear .
  • Page 193 MAX31782 User’s Guide Z=0: IP ← IP + src (relative) -or- src (absolute) JUMPNZ Z=1: IP ← IP + 1 Operation: Encoding: f101 1100 ssss ssss Example(s): JUMP NZ, label1 ; Z=1, branch taken E=1: IP ← IP + src (relative) -or- src (absolute) JUMPE E=0: IP ←...
  • Page 194 MAX31782 User’s Guide MOVEdst,src MoveData Description: Moves data from a specified source (src) to a specified destination (dst) . A list of defined source, destination spec- ifiers is given in the table below . Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section .
  • Page 195 MAX31782 User’s Guide MOVEdst,src(continued) MoveData Table20-3.DestinationSpecifierCodes dstBitEncoding WIDTH(16OR8) DESCRIPTION (ddddddd) Null (Virtual) Destination . Intended as a bit bucket to assist soft- 111 0110 8/16 ware with pointer increments/decrements . nnnn Selects One of First 8 Registers in Module NNN; where...
  • Page 196 MAX31782 User’s Guide ; A[0] ← A[3] Example(s): MOVE A[0], A[3] ; DP[0] ← #0110h (PFX[0] register used) MOVE DP[0], #110h ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h MOVE DP[0], #80h ; DP[0] ← #0080h (PFX[0] register not needed)
  • Page 197 MAX31782 User’s Guide MOVEC,Acc.<b> MoveAccumulatorBittoCarryFlag Description: Replaces the Carry (C) status flag with the specified active accumulator bit . StatusFlags: C ← Acc .<b> Operation: Encoding: 1110 1010 bbbb 1010 Example(s): ; Acc = 01C0h, C=0 MOVE C, Acc .8 ;...
  • Page 198 MAX31782 User’s Guide MOVEC,#1 SetCarryFlag Description: Sets the Carry (C) processor status flag . C ← 1 StatusFlag: C ← 1 Operation: Encoding: 1101 1010 0001 1010 Example(s): ; C = 0 MOVE C, #1 ; C ← 1 MOVEdst.<b>,#0...
  • Page 199 MAX31782 User’s Guide NEG NegateAccumulator Description: Performs a negation (two’s complement) of the active accumulator and returns the result back to the active accumulator . StatusFlags: S, Z Acc ← ~Acc + 1 Operation: Encoding: 1000 1010 1001 1010 Example(s): ;...
  • Page 200 MAX31782 User’s Guide ORAcc.<b> LogicalORCarryFlagwithAccumulatorBit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumula- tor (Acc .<b>) and returns the result to the Carry . StatusFlags: C ← C OR Acc .<b>...
  • Page 201 MAX31782 User’s Guide POPIdst PopWordfromtheStackEnableInterrupts Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP) . Additionally, POPI returns the interrupt logic to a state in which it can acknowledge additional interrupts .
  • Page 202 MAX31782 User’s Guide RET ReturnfromSubroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP) . The decremented SP is saved as the new stack pointer (SP) . StatusFlags: None IP ←...
  • Page 203 MAX31782 User’s Guide RETNC C=0: IP ← @SP-- Operation: C=1: IP ← IP +1 Encoding: 1110 1100 0000 1101 Example(s): RET NC ; C=1, return (RET) does not occur RETZ Z=1: IP ← @SP-- Operation: Z=0: IP ← IP + 1...
  • Page 204 MAX31782 User’s Guide RETI ReturnfromInterrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP) . Additionally, RETI returns the interrupt logic to a state in which it can acknowl- edge additional interrupts .
  • Page 205 MAX31782 User’s Guide RETIZ Z=1: IP ← @SP-- Operation: INS ← 0 Z=0: IP ← IP + 1 Encoding: 1001 1100 1000 1101 Example(s): RETI Z ; Z=0, return from interrupt (RETI) does not occur RETINZ Z=0: IP ← @SP-- Operation: INS ←...
  • Page 206 MAX31782 User’s Guide RL/RLC RotateLeftAccumulator CarryFlag(Ex/In)clusive Description: Rotates the active accumulator left by a single bit position . The RL instruction circulates the msb of the accumula- tor (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift .
  • Page 207 MAX31782 User’s Guide RR/RRC RotateRightAccumulator CarryFlag(Ex/In)clusive Description: Rotates the active accumulator right by a single bit position . The RR instruction circulates the lsb of the accumula- tor (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift .
  • Page 208 MAX31782 User’s Guide SLA/SLA2/SLA4 ShiftAccumulatorLeftArithmetically One,Two,orFourTimes Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4 . For each shift iter- ation, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag . For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur .
  • Page 209 MAX31782 User’s Guide SR/SRA/SRA2/SRA4 ShiftAccumulatorRight/ShiftAccumulatorRightArithmetically One,Two,orFourTimes Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times, respectively, for the SRA2, SRA4 instructions . The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instruc- tions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation .
  • Page 210 MAX31782 User’s Guide SRA2Operation: Active Accumulator (Acc) 0 Carry Flag Acc .[13:0] ← Acc .[15:2] Acc .[15:14] ← Acc .15 C ← Acc .1 Encoding: 1000 1010 1110 1010 Example(s): ; Acc = 0003h, C=0, Z=0 SRA2 ; Acc = 0000h, C=1, Z=1...
  • Page 211 MAX31782 User’s Guide SUB/SUBBsrc Subtract/SubtractwithBorrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumula- tor . The SUBB additionally subtracts the borrow (Carry Flag), which may have resulted from previous subtraction . For the complete list of src specifiers, reference the MOVE instruction .
  • Page 212 MAX31782 User’s Guide XCH ExchangeAccumulatorBytes Description: Exchanges the upper and lower bytes of the active accumulator . StatusFlags: Acc .[15:8] ← Acc .[7:0] Operation: Acc .[7:0] ← Acc .[15:8] Encoding: 1000 1010 1000 1010 Example(s): ; Acc = 2345h XCHN ;...
  • Page 213 MAX31782 User’s Guide XORsrc LogicalXOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data . For the complete list of src specifiers, reference the MOVE instruction . Because the source is lim- ited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources .
  • Page 214 MAX31782 User’s Guide SECTION 21: UTILITY ROM This section contains the following information: 21 .1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2 21 .2 In-Application Programming Functions .
  • Page 215 SECTION 21: UTILITY ROM 21.1Overview The MAX31782 utility ROM includes routines that provide the following functions to application software: • In-application programming routines for flash memory (program, erase, mass erase) • Single word/byte copy and buffer copy routines for lookup tables in flash •...
  • Page 216 MAX31782 User’s Guide 21.2In-ApplicationProgrammingFunctions 21.2.1UROM�flashWrite Function UROM_flashWrite Summary Programs a single word of flash memory A[0]: Word address in program flash memory to write . Inputs A[1]: Value to write to flash memory . Outputs Carry: Set on error and cleared on success...

  • Page 217: Section 21: Utility Rom

    MAX31782 User’s Guide 21.3DataTransferFunctions The MAX31782 cannot access data from the same memory segment that is currently being used for instructions . For example, when instructions are executing from FLASH, data in FLASH cannot be accessed . The following utility ROM functions can be used to transfer data from one memory segment to another .
  • Page 218 MAX31782 User’s Guide 21.3.1UROM�moveDP0 Function UROM_moveDP0 Summary Reads the byte/word value pointed to by DP[0] . Inputs DP[0]: Address to read from data space (include 8000h offset if reading from flash) . Outputs GR: Data byte/word read . Destroys None Notes: •...
  • Page 219 MAX31782 User’s Guide 21.3.4UROM�moveDP1 Function UROM_moveDP1 Summary Reads the byte/word value pointed to by DP[1] . Inputs DP[1]: Address to read from data space (include 8000h offset if reading from flash) . Outputs GR: Data byte/word read . None Destroys Notes: •...
  • Page 220 MAX31782 User’s Guide 21.3.7UROM�moveBP Function UROM_moveBP Summary Reads the byte/word value pointed to by BP[OFFS] . Inputs BP[OFFS]: Address to read from data space (include 8000h offset if reading from flash) . Outputs GR: Data byte/word read Destroys None .
  • Page 221 MAX31782 User’s Guide 21.3.10UROM�copyBuffer Function UROM_copyBuffer Summary LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS] . DP[0]: Starting address to copy from . Inputs BP[OFFS]: Starting address to copy to . LC[0]: Number of bytes/words to copy . OFFS is incremented by LC[0] .
  • Page 222 MAX31782 User’s Guide 21.4UtilityROMExamples 21.4.1ReadingConstantWordDatafromFlash UROM_moveDP0inc equ 08494h move DPC, #1Ch ; Set all pointers to word mode ; P oint to address of data as viewed in the Utility ROM move DP[0], #(table + 8000h) memory map lcall #UROM_moveDP0inc move A[0], GR ; A[0] = 1111h lcall #UROM_moveDP0inc move A[1], GR ; A[1] = 2222h lcall #UROM_moveDP0inc move A[2], GR ; A[0] = 3333h lcall #UROM_moveDP0inc move A[3], GR ; A[1] = 4444h sjump $ org 0100h table: dw 1111h, 2222h, 3333h, 4444h 21.4.2ReadingConstantByteDatafromFlash(Indirect FunctionCall)

  • Page 223: Revision History

    Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2011 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. Revision 0; 8/11...

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