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Maxim Integrated MAX32600 User Manual

Maxim Integrated MAX32600 User Manual

Wellness measurement microcontroller

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MAX32600

User's Guide

April 2015

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Page 1 MAX32600 User’s Guide April 2015...
Page 2: Table Of Contents
MAX32600 User’s Guide Contents Contents Contents Main Page Legal Disclaimer ..............
Page 3 MAX32600 User’s Guide Contents Contents 2.4.5 Cryptographic Internal Oscillator ............
Page 4 MAX32600 User’s Guide Contents Contents 2.8.1 Trust Protection Unit (TPU) ............
Page 5 MAX32600 User’s Guide Contents Contents 3.4.2 Core AHB Interface - D-Code ............
Page 6 MAX32600 User’s Guide Contents Contents 4.1.9 Low-Dropout Regulators (LDO) ............
Page 7 MAX32600 User’s Guide Contents Contents 4.4.1.11 IOMAN_SPI1_REQ ............119 4.4.1.12 IOMAN_SPI1_ACK...
Page 8 MAX32600 User’s Guide Contents Contents Pin Conﬁgurations, Packages, and Special Function Multiplexing Pin Layout ............... . . 165 Pin Function Mapping .
Page 9 MAX32600 User’s Guide Contents Contents 6.3.3 PMU Op Code: WAIT (0x02) ............198 6.3.4...
Page 10 MAX32600 User’s Guide Contents Contents 7.1.6.1 Peripheral Clock Frequency Selection ..........227 7.1.7...
Page 11 MAX32600 User’s Guide Contents Contents 7.3.2.1 Compact Layout Conﬁguration ........... . . 284 7.3.2.2...
Page 12 MAX32600 User’s Guide Contents Contents 8.2.1.1 ..............350 8.2.1.2...
Page 13 MAX32600 User’s Guide Contents Contents 8.4.3.2 Individual DAC Conﬁguration Settings ..........454 8.4.3.3...
Page 14 MAX32600 User’s Guide Contents Contents 8.5.7.1 Design Current ............. 487 8.5.7.2...
Page 15 MAX32600 User’s Guide Contents Contents 10.1.1.4 48MHz Internal 24MHz Trimmed Relaxation Oscillator ........500 10.1.1.5 Cryptographic Internal Oscillator...
Page 16 MAX32600 User’s Guide Contents Contents 10.3.3 RTC Interrupts ..............564 10.3.4 RTC Conﬁguration...
Page 17 MAX32600 User’s Guide Contents Contents 11.2 Modular Arithmetic Accelerator (MAA) ............617 11.2.1 Registers (MAA)
Page 18 MAX32600 User’s Guide Contents Contents 12.6.1.5 CRC_DATA_VALUE32 ............634 13 LCD Controller 13.1 LCD Overview...
Page 19 MAX32600 User’s Guide Contents Contents 14.1.1.4 FLC_INTR ............. . . 655 14.1.1.5 FLC_FDATA...
Page 20: Main Page
Document Disclaimer ©2015 by Maxim Integrated, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTAT ION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
Page 21 MAX32600 User’s Guide Main Page 1.2 Revision Information Version Section Changes 6.4.1.3 PMUn_LOOP: Corrected descriptions for counter_0 and counter_1 ﬁelds. 8.2.1 Graphic and label corrections to Figures 8.1, 8.2, 8.3, and 8.4. 8.2.2.1.4 AFE_CTRL2: Corrected ﬁeld and value descriptions for dacout_en0, dacout_en1, dacout_en2, and dacout_en3.
Page 22: Introduction
24MHz. Application code on the MAX32600 runs from an onboard program ﬂash memory (64 KB to 256 KB), with 16 KB to 32 KB SRAM available for general application use. A 2 KB instruction cache improves execution throughput, and a transparent code scrambling interface is used to protect customer intellectual property residing in the program ﬂash memory.
Page 23 MAX32600 User’s Guide Introduction 2.1 Overview Figure 2.1: Block Diagram Rev.1.3 April 2015 Maxim Integrated Page 5...
Page 24: Core And Architecture
• Power saving sleep mode(s) 2.2.1 Core Parameters When the Cortex-M3 core is instantiated in a design, values must be selected for conﬁgurable parameters in the core. For the MAX32600 design, core parameters have been selected as shown below. Parameter...
Page 25 MAX32600 User’s Guide Introduction 2.2 Core and Architecture Parameter Value Description RESET_ALL_REGS Registers are set to a known reset state. JTAG_PRESENT JTAG Debug Access Port is included on this design. CLKGATE_PRESENT Architectural gates are included to minimize dynamic power dissipation.
Page 26: Generic Memory Map
MAX32600 User’s Guide Introduction 2.2 Core and Architecture 2.2.2 Generic Memory Map Figure 2.2: Memory Map Rev.1.3 April 2015 Maxim Integrated Page 8...
Page 27: Ahb Buses
2.2 Core and Architecture 2.2.3 AHB Buses The standard ARM Advanced High Performance Bus (AHB-Lite version) is used for several different system bus masters on the MAX32600. All buses are 32-bits in width. • I-Code: Performs instruction fetches from internal code memory regions. On the MAX32600, accesses to internal program ﬂash memory (for instruction decoding purposes) are cached to improve execution throughput.
Page 28: Arm Debug
CPU is running, and pause, trace, or reset the CPU. Because the debug engine is coupled to the CPU only for clocking and reset purposes, if the debug engine pauses the CPU it is important to note that other peripherals and functions on the MAX32600 are not paused and continue to operate normally.
Page 29: Onboard Core Voltage Regulator
2.3.4 Onboard VUSB Voltage Regulator and Automatic Power Switching The MAX32600 includes a second onboard digital supply voltage regulator which is used when a powered USB bus has been connected to the device. This regulator takes the 5V (typical) supply from V and regulates it down to a nominal 3.3V output.
Page 30: Clock Inputs
Time Clock module. An external clock source may also be used by the MAX32600 in place of a 32kHz crystal. For this conﬁguration, the external clock source (which must meet the electrical/timing requirements given in the datasheet) is connected to the part on the 32KIN pin.
Page 31: Cryptographic Internal Oscillator
MAX32600 to execute any application code. The MAX32600 supports multiple size options for the ﬂash memory within the maximum possible space of 256 KB. The actual size of the memory is controlled by a trim option loaded from the ﬂash information block. When a size smaller than the maximum one is being used, the ﬂash controller will respond to attempts to access out-of-range addresses within the 256 KB range by setting an interrupt ﬂag and returning a ﬁxed "invalid access"...
Page 32: Internal Data Sram
2.5.3 Internal Data SRAM The internal data SRAM on the MAX32600 ranges from 16 KB to 32 KB in size and has a 32-bit internal width. It is mapped into the SRAM bit-banding access region beginning at address 0x2000_0000, and so it can be read/written either a full 32-bit word at a time, or a single bit at a time using the bit-band alias region (beginning at 0x2200_0000).
Page 33: Flash Information Block
However, this mapping of the ﬂash information block (and direct read/write access to its contents) is only intended for testing and trimming purposes during the factory production test sequence. Once production test of the MAX32600 has completed (or at least the last stage where trim operations are performed has been completed), a lock option setting will be set in the information block to prevent future modiﬁcations to the trim and option settings (except for those which are explicitly...
Page 34: Analog Peripherals
2.6.1 16-Bit ADC with PGA The MAX32600 includes a 16-bit analog-to-digital converter (ADC) with a 16-channel analog input multiplexer, to allow selection of input from one of 16 input lines (single-ended mode) or two of eight input pairs (differential mode). The differential mode supports fully differential signal inputs.
Page 35: 8-Bit Voltage Output Dacs
The SPST switches support input voltages from ground to V AVDD 2.6.7 Temperature Sensor The device includes an internal temperature sensor which can be read using the ADC. The MAX32600 also supports a mode for an external temperature sensor. 2.7 Digital Peripherals 2.7.1 GPIO Pins w/Interrupt and Wakeup Capability The device includes up to eight GPIO ports with eight pins per port for a total of 64 GPIO pins.
Page 36: 32-Bit Timer/Counters
2.7.3 Watchdog Timers The MAX32600 includes two independent watchdog timers (WDT) with window support. The watchdog timers run independently from each other and the processor and have multiple clock source options for ensuring system stability. The watchdog uses a 32-bit timer with prescaler to generate the watchdog reset. When enabled, the watchdog timers must be fed/reset prior to timeout or within a speciﬁed window of time if window mode is enabled.
Page 37: 32-Bit Real Time Clock With Time Of Day Alarm
MAX32600 User’s Guide Introduction 2.7 Digital Peripherals The ﬁrst watchdog instance (WDT0) can be conﬁgured to trigger a system reset (reset of digital core) when it generates a watchdog reset. The second watchdog instance (WDT1) can be conﬁgured to generate a system reboot (equivalent to digital POR event) when it generates a watchdog reset.
Page 38: Usb 2.0 Device Slave With Integrated Transceiver
2.7.8 LCD Controller The MAX32600 incorporates an LCD controller with a boost regulator that interfaces to common low-voltage displays in the standard 12mm x 12mm package. By incorporating the LCD controller into the microcontroller, the design requires only an LCD glass rather than a considerably more expensive LCD module. Every character in an LCD glass is composed of one or more segments, each of which is activated by selecting the appropriate segment and common signal.
Page 39: Security Features
2.8.1 Trust Protection Unit (TPU) The MAX32600 includes several cryptographic and security peripherals which are grouped together to form the Trust Protection Unit, or TPU. The TPU architecture includes cryptographic peripherals (such as the AES engine or the Micro MAA) as well as security features (such as the dynamic tamper sensor) which help to form a secure cryptographic boundary for protecting critical user information within the device.
Page 40: Modular Arithmetic Accelerator (Maa)
MAX32600 User’s Guide Introduction 2.8 Security Features storage using an AES master key, then once a tamper response occurs and this master key has been deleted, the sensitive information will not be recoverable by an attacker at that point; even if the ciphertext version of the information can be recovered in some way, the key that was used to encrypt that data no longer exists.
Page 41: Memory, Register Mapping, And Access
MAX32600 User’s Guide Memory, Register Mapping, and Access 3 Memory, Register Mapping, and Access 3.1 Memory, Register Mapping, and Access Overview The ARM Cortex-M3 architecture deﬁnes a standard memory space for uniﬁed code and data access. This memory space is addressed in units of single bytes but is most typically accessed in 32-bit (4-byte) units.
Page 42: Standard Memory Regions
This is arranged so that data fetches avoid interfering with instruction execution. On the MAX32600, the code space memory area contains the main program ﬂash memory, which holds the majority of the instruction code that will be executed on the device.
Page 43: Peripheral Space
(non-ARM-core) bus masters such as the PMU AHB bus master will not trigger a bit-banding operation and will instead result in an AHB bus error. The SRAM area on the MAX32600 can be used to contain executable code. Code stored in the SRAM is accessed directly for execution (using the system bus) and is not cached or code scrambled.
Page 44: External Ram Space
3.3 Device Memory Instances This section details physical memory instances on the MAX32600 (including main program ﬂash and SRAM instances) that are accessible as standalone memory regions using either the AHB or APB bus matrix. Memory areas which are only accessible via FIFO interfaces, or memory areas consisting of only a few registers for a particular peripheral, are not covered here.
Page 45: Main Program Flash Memory
3.3.7 TPU Memory Secure Key Storage Area The MAX32600 contains a specialized 128-bit memory that is designed to preserve a critical key (such as an AES key) even when the device is in the lowest power-saving state. As long as the RTC power supply is still available, this key will be retained, even if the AES block and the main SRAM are shut down completely.
Page 46: Ahb Bus Matrix And Ahb Bus Interfaces
MAX32600 User’s Guide Memory, Register Mapping, and Access 3.4 AHB Bus Matrix and AHB Bus Interfaces The Secure Key Storage Area consists of four V -backed 32-bit registers: TPU_TSR_SKS0, TPU_TSR_SKS1, TPU_TSR_SKS2, and TPU_TSR_SKS3. 3.4 AHB Bus Matrix and AHB Bus Interfaces This section details memory accessibility on the AHB bus matrix and the organization of AHB master and slave instances.
Page 47: System Conﬁguration And Management
(powered by battery or super cap) ensures that this domain is always on during battery change or other loss-of-power events on the main V supply. When a wakeup event is detected, the MAX32600 exits the low power mode (LP0: STOP or LP1: STANDBY) and always enters LP3: RUN where ﬁrmware takes over control of the system and power states.
Page 48 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Note Power mode transition restrictions dictate measurement sequences. Further transitioning information is found in the power mode sections below. The following is a typical measurement sequence: LP0/LP1 LP0/LP1 Figure 4.1: Power State Diagram...
Page 49: Low Power Modes (Lp0: Stop And Lp1: Standby)
LP0: STOP is the lowest power mode supported by the MAX32600: using as little as 850nA in normal operation and as little as 1.25uA with the RTC active. The core system registers and SRAM do not retain state and, upon exit from LP0: STOP, the system starts as if from a core reset. The sections of the MAX32600 that maintain state during LP0: STOP are: •...
Page 50: Entering Lp0: Stop Or Lp1: Standby
4.1.2.3 Entering LP0: STOP or LP1: STANDBY The following illustrates the procedure to change the MAX32600 operating state to either LP0: STOP or LP1: STANDBY. The examples used set up a GPIO wakeup on P0.0 that wakes up on an active high. Although P0.0 is used here, any available port.pin can be conﬁgured in this manner for a GPIO wakeup event.
Page 51: Wakeup Events From Lp0: Stop And Lp1: Standby
Certain wakeup events can be masked out by writing to the PWRSEQ_MSK_FLAGS register. After Wakeup Events After the MAX32600 experiences a wakeup event from LP0: STOP or LP1: STANDBY, proceed with the following actions: LP0 Wakeup • Read PWRSEQ_FLAGS register to determine the source of the wakeup event Rev.1.3 April 2015...
Page 52: Low Power Modes (Lp2: Pmu And Lp3: Run)
MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • If the wakeup event was a GPIO event, do one of the following to clear the GPIO WUD: 1. If desired action is to clear all GPIO WUD latches: •...
Page 53: Low Power Mode 2 (Lp2: Peripheral Management Unit)
During this state, the ARM Cortex-M3 has relinquished control to the PMU. The ARM Cortex-M3 is in sleep mode, resulting in power reduction and noise minimization. To further reduce power consumption and noise, only the required clocks and data buses are active during LP2: PMU. Typically, the MAX32600 draws 1.2mA of current (24MHz clock) with a single channel of the PMU active.
Page 54 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Figure 4.2: Power and Clock Gating Options Rev.1.3 April 2015 Maxim Integrated Page 36...
Page 55: Power Domains
4.1.5 Power Domains The MAX32600 has multiple power domains that are controlled by the power management block. This includes the Power Sequencer, Power Manager, Trickle Charger, 1.8V LDO, 3.3V USB LDO, and Real Time Clock (RTC). The conﬁguration registers for the Power Manager are within the battery backed V domain.
Page 56: Power Manager
4.1.7.1 Power Mode Transitioning to Low Power Modes To take full advantage of the low power modes of operation in the MAX32600, application ﬁrmware will need to spend as much time as possible in either LP0: STOP and LP1: STANDBY modes. Prior to entering these modes, it is extremely important to set up the wakeup interrupts and supply voltage monitor conﬁguration. To...
Page 57: Svm Periodic Monitoring
The 8kHz Oscillator is a low-power internal oscillator with a nominal frequency of 8kHz that allows periodic supply voltage monitoring during Low Power Modes (LP0: STOP and LP1: STANDBY). 4.1.7.4 First Boot Power Up ﬂag will be set to indicate the MAX32600 is powering up from a ﬁrst boot condition. The When initial power is applied, the PWRSEQ_FLAGS.pwr_ﬁrst_boot pwr_ ﬁrst_boot register must be set to 0 by ﬁrmware prior to attempting to enter either...
Page 58: Brownout Detector
700mV drop and, if detected, sends the NMI to the ARM. The amount of time the supply must be below the detection level is conﬁgurable on the MAX32600 and can be set by ﬁrmware as shown in the following table. This setting indicates the minimum window of detection that the Brownout Detector will see as a brownout.
Page 59: Low-Dropout Regulators (Ldo)
Charger will charge the super capacitor from the main V supply. Note When using a super capacitor, the MAX32600 cannot go into LP1 until the the super capacitor has been been sufﬁciently charged. Poll the V Warning Level (user conﬁgurable) to set the appropriate level. 4.1.9 Low-Dropout Regulators (LDO) 4.1.9.1 1.8V LDO...
Page 60: Reset Pins
4.1.10 Reset Pins The MAX32600 contains two active low reset pins, RSTN and SRTSN. RSTN serves as the main chip reset input. Asserting the pin low will reset all registers on the chip except RTC related circuits and wakeup conﬁguration. This allows a restart of all chip functions (analog and digital) while still maintaining the Real Time Clock.
Page 61: Registers (Pwrman)
MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Pin Name Description DAC / op amp power input (3V nominal). Connect to V directly or via a ﬁlter network. DDA3DAC DDA3 Reference power input (3V nominal). Connect to V directly or via a ﬁlter network.
Page 62 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Address Register Word Len Description 0x40090838 PWRMAN_DIE_TYPE Die Type ID Register 0x4009083C PWRMAN_BASE_PART_NUM Base Part Number 0x40090840 PWRMAN_MASK_ID0 Mask ID Register 0 0x40090844 PWRMAN_MASK_ID1 Mask ID Register 1...
Page 63 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 1:AFE is powered on globally; individual AFE controls may be used to power sub-features of AFE on and off as needed. PWRMAN_PWR_RST_CTRL.io_active Field Bits Default Access...
Page 64 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Initiates a system reset when set to 1. This bit is self-clearing. PWRMAN_PWR_RST_CTRL.arm_lockup_reset Field Bits Default Access Description arm_lockup_reset ARM Lockup Reset If this bit is set to 1, a system reset will be automatically triggered when the ARM core asserts its lockup state output signal.
Page 65 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description watchdog_timeout special Reset Caused By - Watchdog Reset PWRMAN_PWR_RST_CTRL.fw_command_arm Field Bits Default Access Description fw_command_arm special Reset Caused By - Firmware Commanded Reset (ARM Core) PWRMAN_PWR_RST_CTRL.arm_lockup...
Page 66 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes 1: Enables dynamic clock gating for pwrman functions. 4.1.12.1.2 PWRMAN_INTFL PWRMAN_INTFL.v1_8_warning Field Bits Default Access Description v1_8_warning 1.8V Warning Monitor Int Flag Write 1 to clear. Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.
Page 67 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description v3_3_reset 3.3V Reset Monitor Int Flag Write 1 to clear. Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.
Page 68 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_INTEN.rtc_warning Field Bits Default Access Description rtc_warning RTC Warning Monitor Int Enable 0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event. PWRMAN_INTEN.v3_3_reset Field Bits Default Access...
Page 69 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_SVM_EVENTS.v3_3_warning Field Bits Default Access Description v3_3_warning 3.3V Warning Monitor Event Input Current state of the associated SVM event input. PWRMAN_SVM_EVENTS.rtc_warning Field Bits Default Access Description rtc_warning RTC Warning Monitor Event Input Current state of the associated SVM event input.
Page 70 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes 4.1.12.1.5 PWRMAN_WUD_CTRL PWRMAN_WUD_CTRL.pad_select Field Bits Default Access Description pad_select 000000b Wake-Up Pad Select Selects which pad to modify WUD/Weak latch states. Pads are numbered from 0-63, where 0-7 corresponds to P0.0-P0.7, 8-15 corresponds to P1.0-P1.7, and so on.
Page 71 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes 4.1.12.1.6 PWRMAN_WUD_PULSE0 Default Access Description WUD Pulse To Mode Bit 0 Writing to this register issues a pulse to the selected WUD pad mode[0] for one clock.
Page 72 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description gpio0 Wake-Up Detect Status for P0.0 gpio1 Wake-Up Detect Status for P0.1 gpio2 Wake-Up Detect Status for P0.2 gpio3 Wake-Up Detect Status for P0.3 gpio4 Wake-Up Detect Status for P0.4...
Page 73 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description gpio11 Wake-Up Detect Status for P1.3 gpio12 Wake-Up Detect Status for P1.4 gpio13 Wake-Up Detect Status for P1.5 gpio14 Wake-Up Detect Status for P1.6 gpio15 Wake-Up Detect Status for P1.7...
Page 74 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description gpio22 Wake-Up Detect Status for P2.6 gpio23 Wake-Up Detect Status for P2.7 Displays wakeup detection status of the 8 listed GPIO pads, •...
Page 75 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Displays wakeup detection status of the 8 listed GPIO pads, • bit 0: Px.0 • bit 1: Px.1 • bit 2: Px.2 • bit 3: Px.3 • bit 4: Px.4 •...
Page 76 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • bit 1: Px.1 • bit 2: Px.2 • bit 3: Px.3 • bit 4: Px.4 • bit 5: Px.5 • bit 6: Px.6 • bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.
Page 77 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • bit 4: Px.4 • bit 5: Px.5 • bit 6: Px.6 • bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected. Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.
Page 78 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected. Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.
Page 79 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Default Access Description Die Type ID Register Read-only. Always returns 4D513637h to identify as ’MQ67’. 4.1.12.1.11 PWRMAN_BASE_PART_NUM PWRMAN_BASE_PART_NUM.base_part_number Field Bits Default Access Description base_part_number 15:0 Base Part Number Always returns 3260h (base part number).
Page 80 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_MASK_ID0.mask_id Field Bits Default Access Description mask_id 31:4 Mask ID[27:0] Mask identiﬁcation information - low 28 bits. 4.1.12.1.13 PWRMAN_MASK_ID1 PWRMAN_MASK_ID1.mask_id Field Bits Default Access Description mask_id 30:0 Mask ID[58:28] Mask identiﬁcation information - high 31 bits.
Page 81 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.uart1 Field Bits Default Access Description uart1 Reset UART1 • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state.
Page 82 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_PERIPHERAL_RESET.timer2 Field Bits Default Access Description timer2 Reset Timer2 • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.timer3...
Page 83 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description Reset USB • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.adc Field Bits...
Page 84 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.dac2 Field Bits Default Access Description dac2 Reset 8-Bit DAC 0 •...
Page 85 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_PERIPHERAL_RESET.lcd Field Bits Default Access Description Reset LCD • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.gpio Field...
Page 86 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description spi0 Reset SPI 0 • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.spi1...
Page 87 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.i2cm1 Field Bits Default Access Description i2cm1 Reset I2C Master 1 •...
Page 88: Registers (Pwrseq)
MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRMAN_PERIPHERAL_RESET.tpu Field Bits Default Access Description Reset TPU • 0: Peripheral is released to run normally. • 1: Peripheral is held in a reset state. PWRMAN_PERIPHERAL_RESET.ssb Field...
Page 89 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Address Register Word Len Description 0x40090A50 PWRSEQ_FLAGS Power Sequencer Flags 0x40090A54 PWRSEQ_MSK_FLAGS Power Sequencer Flags Mask Register 4.1.13.1.1 PWRSEQ_REG0 PWRSEQ_REG0.pwr_lp1 Field Bits Default Access Description pwr_lp1 0 (PwrSeq RSTN, see note) Shutdown Power Mode Select •...
Page 90 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_sys_reboot Firmware System Reboot Request Writing a 1 to this bit triggers a system reboot. PWRSEQ_REG0.pwr_ldoen_run Field Bits Default Access Description pwr_ldoen_run 1 (PwrSeq RSTN) Enable Main 1.8V LDO Operation in...
Page 91 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_REG0.pwr_chzyen_slp Field Bits Default Access Description pwr_chzyen_slp Enable Backup 1.8V LDO Operation in Sleep Mode Chzy regulator enable during sleep (default 1) PWRSEQ_REG0.pwr_roen_run Field Bits Default Access...
Page 92 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_REG0.pwr_nren_slp Field Bits Default Access Description pwr_nren_slp 0 (RTC POR) Enable Nano Oscillator in Sleep Mode Nano oscillator enable during sleep (default 0) PWRSEQ_REG0.pwr_rtcen_run Field Bits Default...
Page 93 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_REG0.pwr_svm3en_slp Field Bits Default Access Description pwr_svm3en_slp 1 (PwrSeq RSTN) Enable VDD3 SVM operation in Sleep Mode VDD3 SVM enable during sleep mode (default 1) PWRSEQ_REG0.pwr_svm1en_run Field...
Page 94 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes VRTC SVM enable during run mode (default 0) PWRSEQ_REG0.pwr_svmrtcen_slp Field Bits Default Access Description pwr_svmrtcen_slp 0 (PwrSeq RSTN) Enable VRTC SVM operation in Sleep Mode VRTC SVM enable during sleep mode (default 0) PWRSEQ_REG0.pwr_svmvdda3en...
Page 95 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • A7h - no diode + 4kohm • A9h - diode + 250ohm • AAh - diode + 2kohm • ABh - diode + 4kohm By default, the trickle charger is disabled.
Page 96 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 0: VDDIO supply rail is powered on (default). • 1: VDDIO supply rail is powered down. PWRSEQ_REG1.pwr_man_vddio_sw Field Bits Default Access Description pwr_man_vddio_sw 0 (PwrSeq RSTN)
Page 97 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes This setting will only take effect when the Manual Override Enable for VDDIO Switch 1/2 has been set to 1. • 0: VDDIO_SW1 is set to VREG18 mode (default).
Page 98 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_REG2.pwr_w1 Field Bits Default Access Description pwr_w1 14:10 15 (PwrSeq RSTN or VDD3 rail POR) pwr_w1_o[4:0] VREG18 Warning decode. approx 30mV step size over applicable range. PWRSEQ_REG2.pwr_w1_low...
Page 99 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes 4.1.13.1.4 PWRSEQ_REG3 PWRSEQ_REG3.pwr_rosel Field Bits Default Access Description pwr_rosel 101b (PwrSeq RSTN) pwr_rosel_o[2:0] Relaxation Oscillator Stable timeout setting (in RO clocks) • 000b - Bypass • 001b - 64 clocks •...
Page 100 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 10b: 128 clocks • 11b: 256 clocks Notes • This ﬁeld is reset by any of the following conditions/events: – PwrSeq RSTN (power sequencer asynchronous reset) –...
Page 101 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_pwrﬂtrsvmselo 11b (PwrSeq RSTN) pwr_pwrﬂtrsvmselo_o[1:0] Window of time power must be valid while checking SVMs (in SVM clocks) • 00b: Bypass • 01b: 2 clocks •...
Page 102 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_svm_clk_mux 14:13 00b (PwrSeq RSTN) pwr_svm_clk_mux_o[1:0] SVM clock mux • 00b: Nano Oscillator (default) • 01b: RTC clock • 10b: Relaxation Oscillator •...
Page 103 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_REG3.pwr_bo_tc Field Bits Default Access Description pwr_bo_tc 18:17 11b (PwrSeq RSTN) Brownout Detection Time Constant 4.1.13.1.5 PWRSEQ_REG4 PWRSEQ_REG4.pwr_tm_ps_2_gpio Field Bits Default Access Description pwr_tm_ps_2_gpio 0 (PwrSeq RSTN)
Page 104 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_usb_dis_comp 0 (PwrSeq RSTN) pwr_usb_dis_comp_o Disable USB protection comparator PWRSEQ_REG4.pwr_usb_to_vdd_fast Field Bits Default Access Description pwr_usb_to_vdd_fast 0 (PwrSeq RSTN) pwr_usbToVddFast_w Switch to VDD rail as soon as VDDBOK is deasserted PWRSEQ_REG4.pwr_usb_ldo_off...
Page 105 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_trim_svm_bg 000000b (PwrSeq RSTN) pwr_trim_svm_bg_w[5:0] Power manager bandgap trim PWRSEQ_REG5.pwr_trim_reg1p8 Field Bits Default Access Description pwr_trim_reg1p8 0000b (PwrSeq RSTN) pwr_trim_reg1p8_w[3:0] 3 volt to 1.8 volt LDO trim PWRSEQ_REG5.pwr_trim_reg3p3...
Page 106 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_trim_usb_bias 000b (PwrSeq RSTN) pwr_trim_usb_bias_o[2:0] USB bias current trim PWRSEQ_REG6.pwr_trim_usb_pm_res Field Bits Default Access Description pwr_trim_usb_pm_res 0000b (PwrSeq RSTN) pwr_trim_usb_pm_ res_o[3:0] USB Data Plus slew rate trim PWRSEQ_REG6.pwr_trim_usb_dm_res...
Page 107 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_FLAGS.pwr_sys_reboot Field Bits Default Access Description pwr_sys_reboot pwr_sys_reboot_o Firmware Reset event PWRSEQ_FLAGS.pwr_prv_pwr_fail Field Bits Default Access Description pwr_prv_pwr_fail pwr_prv_pwr_fail_r Write 1 to clear power fail detect latch Power Fail event detected PWRSEQ_FLAGS.pwr_prv_boot_fail...
Page 108 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Write 1 to clear analog comparator wakeup latch Comparator wakeup event detected PWRSEQ_FLAGS.pwr_io_wakeup Field Bits Default Access Description pwr_io_wakeup pwr_iowakeup_latch_r Write 1 to clear GPIO wakeup event latch GPIO wakeup event detected PWRSEQ_FLAGS.pwr_vdd3_rst...
Page 109 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_vdd1_rst pwr_vdd1_rst_bad_r Write 1 to clear VREG18 reset compare latch VREG18 reset comparator tripped PWRSEQ_FLAGS.pwr_vdd1_low_rst Field Bits Default Access Description pwr_vdd1_low_rst pwr_vdd1_low_rst_bad_r...
Page 110 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes VRTC comparator tripped PWRSEQ_FLAGS.pwr_por3z_fail Field Bits Default Access Description pwr_por3z_fail pwr_por3z_fail_latch_r Write 1 to clear por3z_fail POR3 and POR3_lite have been tripped PWRSEQ_FLAGS.rtc_cmpr0 Field Bits Default Access...
Page 111 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Write 1 to clear; causes 4kHz transaction in RTC PWRSEQ_FLAGS.rtc_rollover Field Bits Default Access Description rtc_rollover rtc_rollover_ﬂag Write 1 to clear; causes 4kHz transaction in RTC PWRSEQ_FLAGS.pwr_brownout_det...
Page 112 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Write 1 to clear PWRSEQ_FLAGS.pwr_vdd22_rst Field Bits Default Access Description pwr_vdd22_rst pwr_vdd22_rst Write 1 to clear PWRSEQ_FLAGS.pwr_vdd195_rst Field Bits Default Access Description pwr_vdd195_rst pwr_vdd195_rst Write 1 to clear 4.1.13.1.9 PWRSEQ_MSK_FLAGS...
Page 113 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.pwr_prv_boot_fail Field Bits Default Access Description pwr_prv_boot_fail Mask for previous boot fail detect • 0: Event can be detected •...
Page 114 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_MSK_FLAGS.pwr_vdd3_rst Field Bits Default Access Description pwr_vdd3_rst Mask for VDD3 reset comparator event detect • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.pwr_vdd3_warn Field...
Page 115 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes Field Bits Default Access Description pwr_vdd1_low_rst Mask for VREG18 reset LOW compare event • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.pwr_vdd1_warn Field Bits...
Page 116 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.rtc_cmpr0 Field Bits Default Access Description rtc_cmpr0 Mask for RTC compare 0 event • 0: Event can be detected •...
Page 117 MAX32600 User’s Guide System Conﬁguration and Management 4.1 Power Ecosystem and Operating Modes PWRSEQ_MSK_FLAGS.rtc_rollover Field Bits Default Access Description rtc_rollover Mask for RTC rollover event • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.pwr_brownout_det Field Bits Default...
Page 118: Interrupt Vector Table
MAX32600 User’s Guide System Conﬁguration and Management 4.2 Interrupt Vector Table PWRSEQ_MSK_FLAGS.pwr_usb_remove_wakeup Field Bits Default Access Description pwr_usb_remove_wakeup Mask for USB power disconnected wakeup event • 0: Event can be detected • 1: Event is masked PWRSEQ_MSK_FLAGS.pwr_vdd22_rst Field Bits Default...
Page 119 MAX32600 User’s Guide System Conﬁguration and Management 4.2 Interrupt Vector Table Interrupt Number Vector Interrupt Source 0x40 UART0 0x44 UART1 0x48 C Master 0 0x4c C Slave 0x50 USB Device Controller 0x54 Peripheral Management Unit 0x58 Analog Front End 0x5c...
Page 120: Resets And Reset Sources
This section describes resets and the reset sources for the MAX32600. 4.3.1 System Reset The system reset triggers a reset of the operational states and most digital and analog blocks on the MAX32600, including the ARM Cortex-M3 CPU. Sources that can trigger a system reset include: •...
Page 121: Power-On Reset
4.3.2 Power-On Reset The Power-On Reset or POR on the MAX32600 resets all functions and blocks that are reset by a System Reset, but also resets additional blocks and registers including certain system conﬁguration registers and the ARM JTAG debugging engine on the Cortex-M3 core.
Page 122: Ioman_Spi0_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Address Register Word Len Description 0x40090C20 IOMAN_SPI0_REQ SPI0 I/O Mode Request 0x40090C24 IOMAN_SPI0_ACK SPI0 I/O Mode Acknowledge 0x40090C28 IOMAN_SPI1_REQ SPI1 I/O Mode Request 0x40090C2C IOMAN_SPI1_ACK SPI1 I/O Mode Acknowledge 0x40090C30...
Page 123 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 4.4.1.1 IOMAN_WUD_REQ0 IOMAN_WUD_REQ0.port0 Field Bits Default Access Description port0 00000000b Wakeup Detect Request Mode: P0[7:0] • 0:No effect • 1:Requests enable of wakeup detect mode on the associated GPIO pin.
Page 124 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description port3 31:24 00000000b Wakeup Detect Request Mode: P3[7:0] • 0:No effect • 1:Requests enable of wakeup detect mode on the associated GPIO pin. 4.4.1.2 IOMAN_WUD_REQ1 IOMAN_WUD_REQ1.port4...
Page 125 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) • 0:No effect • 1:Requests enable of wakeup detect mode on the associated GPIO pin. IOMAN_WUD_REQ1.port7 Field Bits Default Access Description port7 31:24 00000000b Wakeup Detect Request Mode: P7[7:0] • 0:No effect •...
Page 126 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description port2 23:16 00000000b WUD Mode Acknowledge: P2[7:0] A ’1’ value indicates that the associated pin has been enabled for wakeup detection mode. IOMAN_WUD_ACK0.port3 Field Bits...
Page 127 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description port6 23:16 00000000b WUD Mode Acknowledge: P6[7:0] A ’1’ value indicates that the associated pin has been enabled for wakeup detection mode. IOMAN_WUD_ACK1.port7 Field Bits...
Page 128 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) • 1:Requests analog input mode on the associated pin. IOMAN_ALI_REQ0.port2 Field Bits Default Access Description port2 23:16 00000000b Analog Input Mode Request: P2[7:0] • 0:No effect • 1:Requests analog input mode on the associated pin.
Page 129 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_ALI_REQ1.port5 Field Bits Default Access Description port5 15:8 00000000b Analog Input Mode Request: P5[7:0] • 0:No effect • 1:Requests analog input mode on the associated pin. IOMAN_ALI_REQ1.port6 Field Bits Default...
Page 130 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description port0 00000000b Analog In Mode Acknowledge: P0[7:0] A ’1’ value indicates that the associated pin has been enabled for analog input mode. IOMAN_ALI_ACK0.port1 Field Bits...
Page 131 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description port4 00000000b Analog In Mode Acknowledge: P4[7:0] A ’1’ value indicates that the associated pin has been enabled for analog input mode. IOMAN_ALI_ACK1.port5 Field Bits...
Page 132 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description mapping SPI0 I/O Mapping Select • 00b: Select pin mapping A for all enabled SPI pins • 01b: Select pin mapping B (if supported) • 10b: Select pin mapping C (if supported) •...
Page 133 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Requests SPI mode for SS[1]. IOMAN_SPI0_REQ.ss2_io Field Bits Default Access Description ss2_io SPI0 SS[2] I/O Request 1:Requests SPI mode for SS[2]. IOMAN_SPI0_REQ.ss3_io Field Bits Default Access Description ss3_io SPI0 SS[3] I/O Request 1:Requests SPI mode for SS[3].
Page 134 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI0_REQ.sr1_io Field Bits Default Access Description sr1_io SPI0 SR[1] I/O Request 1:Requests SPI mode for SR[1]. IOMAN_SPI0_REQ.quad_io Field Bits Default Access Description quad_io SPI0 Quad I/O Request 1:Requests SPI mode for SDIO[2] and SDIO[3].
Page 135 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI0_ACK.core_io Field Bits Default Access Description core_io SPI0 Core I/O Acknowledge 1:Acknowledges SPI0 mode selected for SCLK, SDIO[0] and SDIO[1]. IOMAN_SPI0_ACK.ss0_io Field Bits Default Access Description ss0_io SPI0 SS[0] I/O Acknowledge 1:Acknowledges SPI0 mode selected for SS[0].
Page 136 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI0_ACK.ss3_io Field Bits Default Access Description ss3_io SPI0 SS[3] I/O Acknowledge 1:Acknowledges SPI0 mode selected for SS[3]. IOMAN_SPI0_ACK.ss4_io Field Bits Default Access Description ss4_io SPI0 SS[4] I/O Acknowledge 1:Acknowledges SPI0 mode selected for SS[4].
Page 137: Ioman_Spi1_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI0_ACK.quad_io Field Bits Default Access Description quad_io SPI0 Quad I/O Acknowledge 1:Acknowledges SPI0 mode selected for SDIO[3:2]. IOMAN_SPI0_ACK.fast_mode Field Bits Default Access Description fast_mode SPI0 Fast Mode Acknowledge 4.4.1.11 IOMAN_SPI1_REQ IOMAN_SPI1_REQ.mapping...
Page 138 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Requests SPI mode for SCLK, SDIO[0] and SDIO[1]. IOMAN_SPI1_REQ.ss0_io Field Bits Default Access Description ss0_io SPI1 SS[0] I/O Request 1:Requests SPI mode for SS[0]. IOMAN_SPI1_REQ.ss1_io Field Bits Default Access Description...
Page 139 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI1_REQ.ss4_io Field Bits Default Access Description ss4_io SPI1 SS[4] I/O Request 1:Requests SPI mode for SS[4]. IOMAN_SPI1_REQ.sr0_io Field Bits Default Access Description sr0_io SPI1 SR[0] I/O Request 1:Requests SPI mode for SR[0].
Page 140: Ioman_Spi1_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI1_REQ.fast_mode Field Bits Default Access Description fast_mode SPI1 Fast Mode 1:Enables faster pad output transitions. 4.4.1.12 IOMAN_SPI1_ACK IOMAN_SPI1_ACK.mapping Field Bits Default Access Description mapping SPI1 I/O Mapping Acknowledge Mirror of I/O mapping select bits from REQ bits 1:0 IOMAN_SPI1_ACK.core_io...
Page 141 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI1_ACK.ss1_io Field Bits Default Access Description ss1_io SPI1 SS[1] I/O Acknowledge 1:Acknowledges SPI1 mode selected for SS[1]. IOMAN_SPI1_ACK.ss2_io Field Bits Default Access Description ss2_io SPI1 SS[2] I/O Acknowledge 1:Acknowledges SPI1 mode selected for SS[2].
Page 142: Ioman_Spi2_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI1_ACK.sr0_io Field Bits Default Access Description sr0_io SPI1 SR[0] I/O Acknowledge 1:Acknowledges SPI1 mode selected for SR[0]. IOMAN_SPI1_ACK.sr1_io Field Bits Default Access Description sr1_io SPI1 SR[1] I/O Acknowledge 1:Acknowledges SPI1 mode selected for SR[1].
Page 143 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description mapping SPI2 I/O Mapping Select • 00b: Select pin mapping A for all enabled SPI pins • 01b: Select pin mapping B (if supported) • 10b: Select pin mapping C (if supported) •...
Page 144 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Requests SPI mode for SS[1]. IOMAN_SPI2_REQ.ss2_io Field Bits Default Access Description ss2_io SPI2 SS[2] I/O Request 1:Requests SPI mode for SS[2]. IOMAN_SPI2_REQ.ss3_io Field Bits Default Access Description ss3_io SPI2 SS[3] I/O Request 1:Requests SPI mode for SS[3].
Page 145: Ioman_Spi2_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI2_REQ.sr1_io Field Bits Default Access Description sr1_io SPI2 SR[1] I/O Request 1:Requests SPI mode for SR[1]. IOMAN_SPI2_REQ.quad_io Field Bits Default Access Description quad_io SPI2 Quad I/O Request 1:Requests SPI mode for SDIO[2] and SDIO[3].
Page 146 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI2_ACK.core_io Field Bits Default Access Description core_io SPI2 Core I/O Acknowledge 1:Acknowledges SPI2 mode selected for SCLK, SDIO[0] and SDIO[1]. IOMAN_SPI2_ACK.ss0_io Field Bits Default Access Description ss0_io SPI2 SS[0] I/O Acknowledge 1:Acknowledges SPI2 mode selected for SS[0].
Page 147 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI2_ACK.ss3_io Field Bits Default Access Description ss3_io SPI2 SS[3] I/O Acknowledge 1:Acknowledges SPI2 mode selected for SS[3]. IOMAN_SPI2_ACK.ss4_io Field Bits Default Access Description ss4_io SPI2 SS[4] I/O Acknowledge 1:Acknowledges SPI2 mode selected for SS[4].
Page 148: Ioman_Uart0_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_SPI2_ACK.quad_io Field Bits Default Access Description quad_io SPI2 Quad I/O Acknowledge 1:Acknowledges SPI2 mode selected for SDIO[3:2]. IOMAN_SPI2_ACK.fast_mode Field Bits Default Access Description fast_mode SPI2 Fast Mode Acknowledge 4.4.1.15 IOMAN_UART0_REQ IOMAN_UART0_REQ.mapping...
Page 149: Ioman_Uart0_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Requests UART0 mode for RX and TX pins. IOMAN_UART0_REQ.cts_io Field Bits Default Access Description cts_io UART0 CTS I/O Request 1:Requests UART0 mode for CTS pin. IOMAN_UART0_REQ.rts_io Field Bits Default Access...
Page 150: Ioman_Uart1_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Acknowledges UART0 mode selected for RX and TX. IOMAN_UART0_ACK.cts_io Field Bits Default Access Description cts_io UART0 CTS I/O Acknowledge 1:Acknowledges UART0 mode selected for CTS. IOMAN_UART0_ACK.rts_io Field Bits Default Access...
Page 151: Ioman_Uart1_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_UART1_REQ.core_io Field Bits Default Access Description core_io UART1 Core I/O (RX/TX) Request 1:Requests UART1 mode for RX and TX pins. IOMAN_UART1_REQ.cts_io Field Bits Default Access Description cts_io UART1 CTS I/O Request 1:Requests UART1 mode for CTS pin.
Page 152: Ioman_I2Cm0_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_UART1_ACK.core_io Field Bits Default Access Description core_io UART1 Core I/O (RX/TX) Acknowledge 1:Acknowledges UART1 mode selected for RX and TX. IOMAN_UART1_ACK.cts_io Field Bits Default Access Description cts_io UART1 CTS I/O Acknowledge 1:Acknowledges UART1 mode selected for CTS.
Page 153: Ioman_I2Cm0_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) • 01b: Select pin mapping B (if supported) • 10b: Select pin mapping C (if supported) • 11b: Select pin mapping D (if supported) IOMAN_I2CM0_REQ.core_io Field Bits Default Access Description...
Page 154: Ioman_I2Cs0_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 4.4.1.21 IOMAN_I2CS0_REQ IOMAN_I2CS0_REQ.mapping Field Bits Default Access Description mapping I2C Slave I/O Mapping Select • 00b: Select pin mapping A for all I2C Slave pins • 01b: Select pin mapping B (if supported) •...
Page 155: Ioman_Lcd_Com_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_I2CS0_ACK.core_io Field Bits Default Access Description core_io I2C Slave I/O Acknowledge 1:Acknowledges I2C Slave mode selected for SCL/SDA 4.4.1.23 IOMAN_LCD_COM_REQ IOMAN_LCD_COM_REQ.com_io Field Bits Default Access Description com_io LCD COM I/O Request 1:Requests LCD COM mode for COM[3:0] (all four) 4.4.1.24 IOMAN_LCD_COM_ACK...
Page 156 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description 1:Requests LCD SEG mode for this GPIO. (P3.0) IOMAN_LCD_SEG_REQ0.io_req_25 Field Bits Default Access Description io_req_25 LCD SEG I/O Request for GPIO 25 1:Requests LCD SEG mode for this GPIO. (P3.1) IOMAN_LCD_SEG_REQ0.io_req_26...
Page 157 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Requests LCD SEG mode for this GPIO. (P3.4) IOMAN_LCD_SEG_REQ0.io_req_29 Field Bits Default Access Description io_req_29 LCD SEG I/O Request for GPIO 29 1:Requests LCD SEG mode for this GPIO. (P3.5) IOMAN_LCD_SEG_REQ0.io_req_30...
Page 158 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_33 Field Bits Default Access Description io_req_33 LCD SEG I/O Request for GPIO 33 1:Requests LCD SEG mode for this GPIO. (P4.1) IOMAN_LCD_SEG_REQ0.io_req_34 Field Bits Default Access Description io_req_34 LCD SEG I/O Request for GPIO 34 1:Requests LCD SEG mode for this GPIO.
Page 159 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_37 Field Bits Default Access Description io_req_37 LCD SEG I/O Request for GPIO 37 1:Requests LCD SEG mode for this GPIO. (P4.5) IOMAN_LCD_SEG_REQ0.io_req_38 Field Bits Default Access Description io_req_38 LCD SEG I/O Request for GPIO 38 1:Requests LCD SEG mode for this GPIO.
Page 160 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_41 Field Bits Default Access Description io_req_41 LCD SEG I/O Request for GPIO 41 1:Requests LCD SEG mode for this GPIO. (P5.1) IOMAN_LCD_SEG_REQ0.io_req_42 Field Bits Default Access Description io_req_42 LCD SEG I/O Request for GPIO 42 1:Requests LCD SEG mode for this GPIO.
Page 161 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_45 Field Bits Default Access Description io_req_45 LCD SEG I/O Request for GPIO 45 1:Requests LCD SEG mode for this GPIO. (P5.5) IOMAN_LCD_SEG_REQ0.io_req_46 Field Bits Default Access Description io_req_46 LCD SEG I/O Request for GPIO 46 1:Requests LCD SEG mode for this GPIO.
Page 162 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_49 Field Bits Default Access Description io_req_49 LCD SEG I/O Request for GPIO 49 1:Requests LCD SEG mode for this GPIO. (P6.1) IOMAN_LCD_SEG_REQ0.io_req_50 Field Bits Default Access Description io_req_50 LCD SEG I/O Request for GPIO 50 1:Requests LCD SEG mode for this GPIO.
Page 163: Ioman_Lcd_Seg_Req1
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ0.io_req_53 Field Bits Default Access Description io_req_53 LCD SEG I/O Request for GPIO 53 1:Requests LCD SEG mode for this GPIO. (P6.5) IOMAN_LCD_SEG_REQ0.io_req_54 Field Bits Default Access Description io_req_54 LCD SEG I/O Request for GPIO 54 1:Requests LCD SEG mode for this GPIO.
Page 164 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ1.io_req_57 Field Bits Default Access Description io_req_57 LCD SEG I/O Request for GPIO 57 1:Requests LCD SEG mode for this GPIO. (P7.1) IOMAN_LCD_SEG_REQ1.io_req_58 Field Bits Default Access Description io_req_58 LCD SEG I/O Request for GPIO 58 1:Requests LCD SEG mode for this GPIO.
Page 165: Ioman_Lcd_Seg_Ack0
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_REQ1.io_req_61 Field Bits Default Access Description io_req_61 LCD SEG I/O Request for GPIO 61 1:Requests LCD SEG mode for this GPIO. (P7.5) IOMAN_LCD_SEG_REQ1.io_req_62 Field Bits Default Access Description io_req_62 LCD SEG I/O Request for GPIO 62 1:Requests LCD SEG mode for this GPIO.
Page 166 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_25 Field Bits Default Access Description io_ack_25 LCD SEG I/O Acknowledge for GPIO 25 1:Acknowledges SEG mode selected. (P3.1) IOMAN_LCD_SEG_ACK0.io_ack_26 Field Bits Default Access Description io_ack_26 LCD SEG I/O Acknowledge for GPIO 26 1:Acknowledges SEG mode selected.
Page 167 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_29 Field Bits Default Access Description io_ack_29 LCD SEG I/O Acknowledge for GPIO 29 1:Acknowledges SEG mode selected. (P3.5) IOMAN_LCD_SEG_ACK0.io_ack_30 Field Bits Default Access Description io_ack_30 LCD SEG I/O Acknowledge for GPIO 30 1:Acknowledges SEG mode selected.
Page 168 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_33 Field Bits Default Access Description io_ack_33 LCD SEG I/O Acknowledge for GPIO 33 1:Acknowledges SEG mode selected. (P4.1) IOMAN_LCD_SEG_ACK0.io_ack_34 Field Bits Default Access Description io_ack_34 LCD SEG I/O Acknowledge for GPIO 34 1:Acknowledges SEG mode selected.
Page 169 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_37 Field Bits Default Access Description io_ack_37 LCD SEG I/O Acknowledge for GPIO 37 1:Acknowledges SEG mode selected. (P4.5) IOMAN_LCD_SEG_ACK0.io_ack_38 Field Bits Default Access Description io_ack_38 LCD SEG I/O Acknowledge for GPIO 38 1:Acknowledges SEG mode selected.
Page 170 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_41 Field Bits Default Access Description io_ack_41 LCD SEG I/O Acknowledge for GPIO 41 1:Acknowledges SEG mode selected. (P5.1) IOMAN_LCD_SEG_ACK0.io_ack_42 Field Bits Default Access Description io_ack_42 LCD SEG I/O Acknowledge for GPIO 42 1:Acknowledges SEG mode selected.
Page 171 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_45 Field Bits Default Access Description io_ack_45 LCD SEG I/O Acknowledge for GPIO 45 1:Acknowledges SEG mode selected. (P5.5) IOMAN_LCD_SEG_ACK0.io_ack_46 Field Bits Default Access Description io_ack_46 LCD SEG I/O Acknowledge for GPIO 46 1:Acknowledges SEG mode selected.
Page 172 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_49 Field Bits Default Access Description io_ack_49 LCD SEG I/O Acknowledge for GPIO 49 1:Acknowledges SEG mode selected. (P6.1) IOMAN_LCD_SEG_ACK0.io_ack_50 Field Bits Default Access Description io_ack_50 LCD SEG I/O Acknowledge for GPIO 50 1:Acknowledges SEG mode selected.
Page 173: Ioman_Lcd_Seg_Ack1
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK0.io_ack_53 Field Bits Default Access Description io_ack_53 LCD SEG I/O Acknowledge for GPIO 53 1:Acknowledges SEG mode selected. (P6.5) IOMAN_LCD_SEG_ACK0.io_ack_54 Field Bits Default Access Description io_ack_54 LCD SEG I/O Acknowledge for GPIO 54 1:Acknowledges SEG mode selected.
Page 174 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK1.io_ack_57 Field Bits Default Access Description io_ack_57 LCD SEG I/O Acknowledge for GPIO 57 1:Acknowledges SEG mode selected. (P7.1) IOMAN_LCD_SEG_ACK1.io_ack_58 Field Bits Default Access Description io_ack_58 LCD SEG I/O Acknowledge for GPIO 58 1:Acknowledges SEG mode selected.
Page 175: Ioman_Crnt_Req
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_LCD_SEG_ACK1.io_ack_61 Field Bits Default Access Description io_ack_61 LCD SEG I/O Acknowledge for GPIO 61 1:Acknowledges SEG mode selected. (P7.5) IOMAN_LCD_SEG_ACK1.io_ack_62 Field Bits Default Access Description io_ack_62 LCD SEG I/O Acknowledge for GPIO 62 1:Acknowledges SEG mode selected.
Page 176: Ioman_Crnt_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) Field Bits Default Access Description io_req_crnt3 Request for pair CRNT3 io_req_crnt4 Request for pair CRNT4 io_req_crnt5 Request for pair CRNT5 io_req_crnt6 Request for pair CRNT6 io_req_crnt7 Request for pair CRNT7 1:Requests Current Drive I/O mode for drain/source pair.
Page 177 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Acknowledges Current Drive I/O mode enabled for this pair. IOMAN_CRNT_ACK.io_ack_crnt3 Field Bits Default Access Description io_ack_crnt3 Acknowledge for pair CRNT3 1:Acknowledges Current Drive I/O mode enabled for this pair. IOMAN_CRNT_ACK.io_ack_crnt4...
Page 178: Ioman_Crnt_Mode
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_CRNT_ACK.io_ack_crnt7 Field Bits Default Access Description io_ack_crnt7 Acknowledge for pair CRNT7 1:Acknowledges Current Drive I/O mode enabled for this pair. 4.4.1.31 IOMAN_CRNT_MODE IOMAN_CRNT_MODE.[io_crnt0, io_crnt1, io_crnt2, io_crnt3, io_crnt4, io_crnt5, io_crnt6, io_crnt7]...
Page 179: Ioman_Ali_Connect0
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) • 6 = H-Bridge A w/Observe • 7 = H-Bridge B w/Observe 4.4.1.32 IOMAN_ALI_CONNECT0 Default Access Description 00000000h Analog I/O Connection Control Register 0 Selects analog connection input for ﬁrst 32 GPIO.
Page 180: Ioman_I2Cm1_Ack
MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) IOMAN_I2CM1_REQ.core_io Field Bits Default Access Description core_io I2C Master I/O Request 1:Requests I2C Master mode for SCL and SDA pins. 4.4.1.35 IOMAN_I2CM1_ACK IOMAN_I2CM1_ACK.mapping Field Bits Default Access Description mapping I2C Master I/O Mapping Acknowledge Mirror of I/O mapping select bits from REQ bits 1:0 IOMAN_I2CM1_ACK.core_io...
Page 181 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) 1:Enables I/O on PADX GPIO0 and GPIO1 IOMAN_PADX_CONTROL.padx_gpio0_out_mode Field Bits Default Access Description padx_gpio0_out_mode PADX GPIO0 Out Mode Sets output drive mode for GPIO PADX pad. • 0: High impedance •...
Page 182 MAX32600 User’s Guide System Conﬁguration and Management 4.4 Registers (IOMAN) • 0: High impedance • 1: Pullup • 2: Drive 0 • 3: Drive 1 IOMAN_PADX_CONTROL.padx_gpio1_input_state Field Bits Default Access Description padx_gpio1_input_state PADX GPIO1 Input Value Returns input value on GPIO PADX pad.
Page 183: Pin Layout
There are two logical pin layouts available on the MAX32600 which determine the location of certain multiplexed functions. The pin layout in effect is determined by the state of an internal pad in the MAX32600 package which can be bonded either to a high or low setting. The pin layout remapping is performed internal to the MAX32600 and is independent of the actual pad-to-pin/ball packaging layout that occurs as part of the device assembly process.
Page 184: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping • P4[7:0] - These pins exist on Standard layout only. • P5[7:0] - These pins exist on Standard layout only. • P6[7:0] - These pins exist on Standard layout only.
Page 185: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.1: Compact Port 0 IO Function Muxing Figure 5.2: Compact Port 1 IO Function Muxing Rev.1.3 April 2015 Maxim Integrated Page 167...
Page 186: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.3: Compact Port 2 IO Function Muxing 5.2.2 Standard Package GPIO Mapping GPIO port and pin mapping for the Standard Package (12mm x 12mm). Rev.1.3 April 2015...
Page 187: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.4: Standard Port 0 IO Function Muxing Figure 5.5: Standard Port 1 IO Function Muxing Rev.1.3 April 2015 Maxim Integrated Page 169...
Page 188: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.6: Standard Port 2 IO Function Muxing Figure 5.7: Standard Port 3 IO Function Muxing Rev.1.3 April 2015 Maxim Integrated Page 170...
Page 189: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.8: Standard Port 4 IO Function Muxing Figure 5.9: Standard Port 5 IO Function Muxing Rev.1.3 April 2015 Maxim Integrated Page 171...
Page 190: 5.2 Pin Function Mapping
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.2 Pin Function Mapping Figure 5.10: Standard Port 6 IO Function Muxing Figure 5.11: Standard Port 7 IO Function Muxing Rev.1.3 April 2015 Maxim Integrated Page 172...
Page 191: 5.3 General-Purpose I/O
5.3 General-Purpose I/O 5.3 General-Purpose I/O The MAX32600 includes 64 general-purpose I/O (GPIO) pins which can be controlled directly by ﬁrmware or indirectly by other hardware functions (such as output peripherals). GPIOs can be powered by either V or V...
Page 192: 5.3 General-Purpose I/O
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.3 General-Purpose I/O Device Pins When not overridden by a higher-priority function, the GPIO module can be used to control the I/O state of any of the 64 port pins: •...
Page 193: 5.4 Gpio Pins And Peripheral Mode Functions
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.4 GPIO Pins and Peripheral Mode Functions Detailed Description The GPIO function provides ﬁrmware with basic direct control and monitoring capabilities for digital I/O pins. The GPIO module only provides an APB slave interface, as no burst capability is required to implement this function.
Page 194: 5.4 Gpio Pins And Peripheral Mode Functions
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.4 GPIO Pins and Peripheral Mode Functions GPIO Function All eight GPIO pins in each GPIO port have access to a common set of low-level peripheral functions that can use GPIO pins as inputs or outputs: •...
Page 195: 5.4 Gpio Pins And Peripheral Mode Functions
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.4 GPIO Pins and Peripheral Mode Functions Peripheral Pin Function Function Description Direction P0.1 P1.1 P2.1 P3.1 P4.1 P5.1 P6.1 P7.1 Pulse Train 1 Pulse Train 1 Output Pulse Train 4...
Page 196: 5.4 Gpio Pins And Peripheral Mode Functions
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.4 GPIO Pins and Peripheral Mode Functions Px.3 GPIO Pins and Functions Function Support by Port (Px.3, x=0 to 7) Peripheral Pin Function Function Description Direction P0.3 P1.3 P2.3 P3.3 P4.3...
Page 197: 5.4 Gpio Pins And Peripheral Mode Functions
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.4 GPIO Pins and Peripheral Mode Functions Peripheral Pin Function Function Description Direction P0.4 P1.4 P2.4 P3.4 P4.4 P5.4 P6.4 P7.4 32-bit Timer 3 TMR3 32-bit Timer/Counter 3 Input or Out- In/Out Px.5 GPIO Pins and Functions...
Page 198: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Peripheral Pin Function Function Description Direction P0.6 P1.6 P2.6 P3.6 P4.6 P5.6 P6.6 P7.6 32-bit Timer 3 TMR3 32-bit Timer/Counter 3 Input or Out- In/Out 32-bit Timer 0...
Page 199: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Address Register Word Len Description 0x40000040 GPIO_FREE_P0 Port P0 Free for GPIO Operation Flags 0x40000044 GPIO_FREE_P1 Port P1 Free for GPIO Operation Flags 0x40000048 GPIO_FREE_P2 Port P2 Free for GPIO Operation Flags...
Page 200: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Address Register Word Len Description 0x40000140 GPIO_IN_MODE_P0 Port P0 GPIO Input Monitoring Mode 0x40000144 GPIO_IN_MODE_P1 Port P1 GPIO Input Monitoring Mode 0x40000148 GPIO_IN_MODE_P2 Port P2 GPIO Input Monitoring Mode...
Page 201: Gpio_Free_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Address Register Word Len Description 0x40000214 GPIO_INTFL_P5 Port P5 Interrupt Flags 0x40000218 GPIO_INTFL_P6 Port P6 Interrupt Flags 0x4000021C GPIO_INTFL_P7 Port P7 Interrupt Flags 0x40000240 GPIO_INTEN_P0 Port P0 Interrupt Enables...
Page 202: Gpio_Out_Mode_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) • 0: Port pin is not available for GPIO use. • 1: Port pin is available for GPIO use. Note All GPIO registers of this type (GPIO_FREE_Px) follow this same format.
Page 203: Gpio_Out_Val_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) 5.5.1.3 GPIO_OUT_VAL_Pn GPIO_OUT_VAL_Pn.[pin0, pin1, pin2, pin3, pin4, pin5, pin6, pin7] Field Bits Default Access Description pin0 Pn.0 GPIO Output Drive Value pin1 Pn.1 GPIO Output Drive Value pin2 Pn.2 GPIO Output Drive Value...
Page 204: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) • 6: 32-bit Timer 2 I/O • 7: 32-bit Timer 3 I/O GPIO_FUNC_SEL_Pn.pin1 Field Bits Default Access Description pin1 0000b Pn.1 Output Function Select • 0: Firmware control (with OUT_VAL) •...
Page 205: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) • 4: 32-bit Timer 2 I/O • 5: 32-bit Timer 3 I/O • 6: 32-bit Timer 0 I/O • 7: 32-bit Timer 1 I/O GPIO_FUNC_SEL_Pn.pin3 Field Bits...
Page 206: 5.5 Registers (Gpio
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) • 2: Pulse train 2 • 3: Pulse train 6 • 4: 32-bit Timer 0 I/O • 5: 32-bit Timer 1 I/O • 6: 32-bit Timer 2 I/O •...
Page 207: Gpio_In_Mode_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) • 0: Firmware control (with OUT_VAL) • 1: Pulse train 6 • 2: Pulse train 3 • 3: Pulse train 0 • 4: 32-bit Timer 2 I/O •...
Page 208: Gpio_In_Val_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Field Bits Default Access Description pin0 Pn.0 Input Monitoring Mode pin1 Pn.1 Input Monitoring Mode pin2 Pn.2 Input Monitoring Mode pin3 13:12 Pn.3 Input Monitoring Mode pin4 17:16 Pn.4 Input Monitoring Mode...
Page 209: Gpio_Int_Mode_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Returns current input value on this pin, as modiﬁed by the corresponding Input Monitoring Mode setting. 5.5.1.7 GPIO_INT_MODE_Pn GPIO_INT_MODE_Pn.[pin0, pin1, pin2, pin3, pin4, pin5, pin6, pin7] Field...
Page 210: Gpio_Inten_Pn
MAX32600 User’s Guide Pin Conﬁgurations, Packages, and Special Function Multiplexing 5.5 Registers (GPIO) Field Bits Default Access Description pin0 Pn.0 External Interrupt Flags pin1 Pn.1 External Interrupt Flags pin2 Pn.2 External Interrupt Flags pin3 Pn.3 External Interrupt Flags pin4 Pn.4 External Interrupt Flags pin5 Pn.5 External Interrupt Flags...
Page 211 6.1 Overview The Peripheral Management Unit (PMU) on the MAX32600 is a DMA-based linked list processing engine. The PMU can perform operations and data transfers involving memory and/or peripherals in the Advanced Peripheral Bus (APB) and Advanced High-performance Bus (AHB) peripheral memory space while the main CPU is in a sleep state.
Page 212 MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.1 Overview Figure 6.1: PMU Interface Rev.1.3 April 2015 Maxim Integrated Page 194...
Page 213: Pmu Operation
AHB/APB address space using an internal round-robin arbiter, on an op code-by-op code basis, with priority encoding. Priority ranges from channel one with the highest priority and channel six with the lowest priority. The PMU runs from a ﬁxed-source clock and is clocked at the same frequency as the main MAX32600 system clock (scaling conﬁgured by CLKMAN_CLK_CTRL_0_SYSTEM), which has a maximum frequency of 24MHz.
Page 214: Rev.1.3 April
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details 6.3 PMU Programming Details There are eight op codes available for programming the PMU engine. These op codes are: MOVE, WRITE, WAIT, JUMP, LOOP, BRANCH, POLL, and TRANSFER. Each op code has one or more operands that are speciﬁc to the op code. All op codes and operands are 32-bits wide. A description of each op code is given below.
Page 215: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details RD SIZE WR SIZE Operation Perform 8-bit reads and 8-bit writes Perform 8-bit reads and pack data into 16-bit writes Perform 8-bit reads and pack data into 32-bit writes...
Page 216: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details Figure 6.3: PMU WRITE Op Code Details • Set to 1 to generate an interrupt to the CPU upon completion of this op code. STOP • Set to 1 if this op code is to terminate op code processing after execution.
Page 217: 6.3 Pmu Programming Details
The interrupt mask ﬁeld corresponds to the following interrupt sources available to the PMU from the MAX32600. The following interrupts are generated by the Peripheral FIFOs automatically as listed below based on FIFO conﬁguration registers. These interrupts do not require the user to clear or enable the interrupt source, they are self clearing and enabled by the appropriate FIFO conﬁguration registers as shown in the table below.
Page 218: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details Interrupt Bit Source Cause DAC2 almost empty Interrupt is set when FIFO level falls below user deﬁned threshold in the DAC2_CTRL0.ﬁfo_ae_cnt register ﬁeld, interrupt self-clears when the FIFO level is above the user deﬁned threshold in DAC2_CTRL0.ﬁfo_ae_cnt.
Page 219: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details Interrupt Bit Source Cause The remaining interrupts, shown below, must be enabled thru the appropriate peripheral register and also cleared after the interrupt becomes set. PMU Interrupt Event Table...
Page 220: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details Interrupt Bit Source Enable and Clear Interrupts on Port 1 GPIO GPIO_INT_MODE_P1.pin[7:0] to enable, GPIO_INTFL_P1.pin[7:0] to clear (W1C) Interrupts on Port 2 GPIO GPIO_INT_MODE_P2.pin[7:0] to enable, GPIO_INTFL_P2.pin[7:0] to clear (W1C) Interrupts on Port 3 GPIO GPIO_INT_MODE_P3.pin[7:0] to enable, GPIO_INTFL_P3.pin[7:0] to clear (W1C)
Page 221: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details STOP • Set to 1 if this op code is to terminate op code processing after execution. • This also clears the START bit ﬁeld in the PMUn_CFG register.
Page 222: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details 6.3.6 PMU Op Code: POLL (0x05) The POLL op code will cause the PMU engine to pause, wait for the speciﬁed polling interval to occur, and then read the speciﬁed address location. Read accesses may be in either the AHB or APB memory space.
Page 223: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details • This ﬁeld determines the size of the transfer: 00 = 8-bit, 01 = 16-bit and 10 = 32-bit. • This bit, when set to 1, will require that all bits set in the data mask be set in the data read from the poll address. Otherwise, polling will complete when any of the bits in the data mask are set in the data read from the poll address.
Page 224: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details • Set to 1 if this op code is to terminate op code processing after execution. • This also clears the START bit ﬁeld in the PMUn_CFG register. RD SIZE •...
Page 225: 6.3 Pmu Programming Details
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details Figure 6.9: PMU TRANSFER Op Code Details • Set to 1 to generate an interrupt to the CPU upon completion of this op code. STOP • Set to 1 if this op code is to terminate op code processing after execution.
Page 226: Registers (Pmu)
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) RD SIZE WR SIZE Operation Perform 8-bit reads and pack data into 32-bit writes Perform 16-bit reads and unpack into 8-bit writes Perform 16-bit reads and writes Perform 16-bit reads and pack data into 32-bit writes...
Page 227 MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) Address Register Word Len Description 0x40070000 PMU0_DSCADR Starting Descriptor Address 0x40070004 PMU0_CFG Channel Conﬁguration 0x40070008 PMU0_LOOP Channel Loop Counters 0x4007000C PMU0_OP Current Descriptor DWORD 0 (OP) 0x40070010 PMU0_DSC1 Current Descriptor DWORD 1...
Page 228 MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) Address Register Word Len Description 0x40070074 PMU3_DSC2 Current Descriptor DWORD 2 0x40070078 PMU3_DSC3 Current Descriptor DWORD 3 0x4007007C PMU3_DSC4 Current Descriptor DWORD 4 0x40070080 PMU4_DSCADR Starting Descriptor Address 0x40070084 PMU4_CFG Channel Conﬁguration...
Page 229: Pmun_Cfg
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) 6.4.1.2 PMUn_CFG PMUn_CFG.enable Field Bits Default Access Description enable PMU Channel Enable • 0: Disabled/stopped (this channel only) • 1: Enabled/running (this channel only) PMUn_CFG.ll_stopped Field Bits Default Access Description...
Page 230 MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) PMUn_CFG.bus_error Field Bits Default Access Description bus_error AHB Bus Error Interrupt Flag Write 1 to clear. Set to 1 by hardware when an AHB bus error occurs during PMU operation. PMU operation will terminate on an AHB bus error condition.
Page 231 MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) • 111b: 512 PMUn_CFG.ps_sel Field Bits Default Access Description ps_sel 15:14 Time Out Interval Prescale Select This ﬁeld selects the prescale value which is used to generate the timeout counter.
Page 232: Pmun_Loop
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) CPU interrupt enable/disable for this PMU channel. • 0: No interrupts will be generated for this channel. • 1: The PMU will generate an interrupt when the Descriptor Interrupt ﬂag is set. AHB bus error or bus timeout conditions will cause a halt to PMU operation.
Page 233: Pmun_Dsc1
MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU) 6.4.1.5 PMUn_DSC1 Default Access Description 00000000h Current Descriptor DWORD 1 6.4.1.6 PMUn_DSC2 Default Access Description 00000000h Current Descriptor DWORD 2 6.4.1.7 PMUn_DSC3 Default Access Description 00000000h Current Descriptor DWORD 3 6.4.1.8 PMUn_DSC4...
Page 234: Communication Peripherals 7.1 I²C
C bus, drive the clock via the SCL pin, and generate the START and STOP signals. This enables the MAX32600 to send and receive data from a slave as required by the user’s application. In slave mode, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I C master device.
Page 235 Note Pin Layout for a detailed mapping of MAX32600 multiplexed function locations. Functional priority distinction is included in the mapping. 7.1.3.1 Compact Layout (7mm x 7mm) Conﬁguration Available SDA and SCL port and pin conﬁgurations for each of the I...
Page 236 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Figure 7.1: Compact Package Mapping Options I²C Master Conﬁgurations (Compact) I2CM0 Logic Signal Port and Pin A) P1.4 B) P2.2 D) P0.4 A) P1.5 B) P2.3 D) P0.5 Rev.1.3 April 2015 Maxim Integrated...
Page 237 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CM1 Logic Signal Port and Pin A) P1.6 B) P2.6 D) P0.6 A) P1.7 B) P2.7 D) P0.7 I²C Slave Conﬁgurations (Compact) I2CS Logic Signal Port and Pin A) P1.4 B) P2.2 D) P0.4 E) P1.6...
Page 238 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Figure 7.2: Standard Package Mapping Options Rev.1.3 April 2015 Maxim Integrated Page 220...
Page 239 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I²C Master Conﬁgurations (Standard) I2CM0 Logic Signal Port and Pin A) P2.4 B) P2.2 C) P7.4 D) P0.4 A) P2.5 B) P2.3 C) P7.5 D) P0.5 I2CM1 Logic Signal Port and Pin A) P2.6 B) P1.6...
Page 240 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Logic Signal Port and Pin A) P2.4 B) P2.2 C) P7.4 D) P0.4 E) P2.6 F) P1.6 G) P7.6 H) P0.6 A) P2.5 B) P2.3 C) P7.5 D) P0.5 E) P2.7 F) P1.7 G) P7.7...
Page 241: Protocol
MAX32600 User’s Guide Communication Peripherals 7.1 I²C Figure 7.3: I²C Master Block Diagram 7.1.5 Protocol The I C protocol communication is a two-wire serial transmission. It is a half-duplex protocol where data can be transferred at various baud rates: up to 100Kbits (100Kbps) in standard mode and up to 400Kbits (400Kbps) in fast mode.
Page 242: Rev.1.3 April
MAX32600 User’s Guide Communication Peripherals 7.1 I²C Bit Transfer Both SDA and SCL lines are bi-directional lines connected to a positive supply voltage via a current source or a pullup resistor. When the bus is free, the lines are in high state.
Page 243 MAX32600 User’s Guide Communication Peripherals 7.1 I²C 7-1 bits R/W bit Deﬁnition 0000 000 START byte 0000 001 Reserved (CBUS address) 0000 010 Reserved 0000 011 Reserved 0000 1XX Reserved 1111 1XX Reserved General Call Address The general call address is for addressing every device connected to the I C bus at the same time.
Page 244 MAX32600 User’s Guide Communication Peripherals 7.1 I²C When the R/W bit is set to 1, the hardware address of the master is written in the second byte. The General Call Address has no effect on this interface. START Byte The START byte is used to initiate communication with slow devices (i.e., one reliant on software polling). The START byte has no effect on this interface.
Page 245 MAX32600 User’s Guide Communication Peripherals 7.1 I²C i2cm_clk_scale Description 0000b CLK is Disabled 0001b (System Clock Source / 1) 0010b (System Clock Source / 2) 0011b (System Clock Source / 4) 0100b (System Clock Source / 8) 0101b (System Clock Source / 16)
Page 246: Fifo-Based I²C Master
MAX32600 User’s Guide Communication Peripherals 7.1 I²C PCLK I²C Filt CLK Divisor SCL Hi SCL Lo DUTY HOLD 0.67 1000 Note Explanation of SCL Clock Conﬁguration Common Calculations values: • PCLK = Peripheral Clock (MHz) • F C Frequency (KHz) •...
Page 247 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I²C and SMBus Compliance SMBus and I C protocols are essentially the same: an SMBus master is able to control I C devices and vice versa at the protocol level. The SMBus clock is deﬁned from 10kHz to 100kHz whereas I C can range from 0Hz to 100kHz or 0Hz to 400kHz depending on the mode.
Page 248: Module I2Cm Registers
MAX32600 User’s Guide Communication Peripherals 7.1 I²C 7.1.8 Registers (I2CM) 7.1.8.1 Module I2CM Registers Address Register Word Len Description 0x40040000 I2CM0_FS_CLK_DIV Full Speed SCL Clock Settings 0x4004000C I2CM0_TIMEOUT [TO_CNTL] Timeout and Auto-Stop Settings 0x40040010 I2CM0_CTRL [EN_CNTL] I2C Master Control Register...
Page 249 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Filter frequency = 200MHz/bits[7:0]; 1=Off I2CMn_FS_CLK_DIV.fs_scl_lo_cnt Field Bits Default Access Description fs_scl_lo_cnt 19:8 12’b0 Full Speed SCL Low Count Number of clocks to hold SCL low for clock output I2CMn_FS_CLK_DIV.fs_scl_hi_cnt Field Bits Default...
Page 250 MAX32600 User’s Guide Communication Peripherals 7.1 I²C If 1, master automatically issues a Stop when a timeout or unexpected Nack occurs. 7.1.8.1.3 I2CMn_CTRL I2CMn_CTRL.tx_ﬁfo_en Field Bits Default Access Description tx_ﬁfo_en Master Transaction FIFO Enable 0:Disabled; 1:Enabled I2CMn_CTRL.rx_ﬁfo_en Field Bits Default...
Page 251 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Write to 1 to begin a master transaction. I2CMn_TRANS.tx_in_progress Field Bits Default Access Description tx_in_progress Transaction In Progress Set to 1 by hardware when a new transaction is started; cleared when transaction ends.
Page 252 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CMn_TRANS.tx_timeout Field Bits Default Access Description tx_timeout Transaction Timed Out Set to 1 when a transaction halts due to a timeout; cleared to 0 on Start. 7.1.8.1.5 I2CMn_INTFL I2CMn_INTFL.tx_done Field Bits Default Access...
Page 253 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Write 1 to clear. Set to 1 by hardware when a transaction is interrupted due to a lost arbitration failure. I2CMn_INTFL.tx_timeout Field Bits Default Access Description tx_timeout Transaction Timed Out Int Status Write 1 to clear.
Page 254 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description rx_ﬁfo_empty Results FIFO Empty Int Status Write 1 to clear. Set to 1 by hardware when the results FIFO is empty. I2CMn_INTFL.rx_ﬁfo_2q_full Field Bits Default Access Description rx_ﬁfo_2q_full Results FIFO 2Q Full Int Status Write 1 to clear.
Page 255 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Set to 1 by hardware when the results FIFO is completely full. 7.1.8.1.6 I2CMn_INTEN I2CMn_INTEN.tx_done Field Bits Default Access Description tx_done Transaction Done Int Enable 0:Associated int disabled; 1:Interrupt enabled I2CMn_INTEN.tx_nacked Field Bits...
Page 256 MAX32600 User’s Guide Communication Peripherals 7.1 I²C 0:Associated int disabled; 1:Interrupt enabled I2CMn_INTEN.tx_ﬁfo_empty Field Bits Default Access Description tx_ﬁfo_empty Transaction FIFO Empty Int Enable 0:Associated int disabled; 1:Interrupt enabled I2CMn_INTEN.tx_ﬁfo_3q_empty Field Bits Default Access Description tx_ﬁfo_3q_empty Transaction FIFO 3Q Empty Int Enable 0:Associated int disabled;...
Page 257 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CMn_INTEN.rx_ﬁfo_3q_full Field Bits Default Access Description rx_ﬁfo_3q_full Results FIFO 3Q Full Int Enable 0:Associated int disabled; 1:Interrupt enabled I2CMn_INTEN.rx_ﬁfo_full Field Bits Default Access Description rx_ﬁfo_full Results FIFO Full Int Enable 0:Associated int disabled; 1:Interrupt enabled 7.1.8.1.7 I2CMn_BB...
Page 258: Module I2Cs Registers
MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CMn_BB.bb_sda_in_val Field Bits Default Access Description bb_sda_in_val Bit Bang SCL Input Value I2CMn_BB.rx_ﬁfo_cnt Field Bits Default Access Description rx_ﬁfo_cnt 20:16 Results FIFO Data Received Count 7.1.8.1.8 I2CMn_FIFO_TRANS Default Access Description I2C Master 0 Transaction FIFO Writes to this space result in pushes to the I2C Master Transaction FIFO.
Page 259 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Address Register Word Len Description 0x40041000 I2CS0_FS_CLK_DIV Full Speed SCL Clock Settings 0x40041004 I2CS0_HS_CLK_DIV High Speed SCL Clock Settings 0x40041008 I2CS0_DEV_IDS Slave Device ID Settings 0x4004100C I2CS0_TIMEOUT Timeout and Auto-Stop Settings 0x40041010 I2CS0_CTRL...
Page 260 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CS0_FS_CLK_DIV.fs_scl_hi_cnt Field Bits Default Access Description fs_scl_hi_cnt 31:20 12’b0 Full Speed SCL High Count Number of clocks to hold SCL high for clock output 7.1.9.1.2 I2CS0_HS_CLK_DIV I2CS0_HS_CLK_DIV.hs_ﬁlter_clk_div Field Bits Default Access Description hs_ﬁlter_clk_div...
Page 261 MAX32600 User’s Guide Communication Peripherals 7.1 I²C 7.1.9.1.3 I2CS0_DEV_IDS I2CS0_DEV_IDS.dev_id0 Field Bits Default Access Description dev_id0 10’b0 Slave Device ID 0 The ﬁrst slave ID which the I2C Slave will respond to. I2CS0_DEV_IDS.dev_id1 Field Bits Default Access Description dev_id1 21:12 10’b0...
Page 262 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CS0_TIMEOUT.max_rx_block_size Field Bits Default Access Description max_rx_block_size 15:8 8’b0 Max RX Block Size The maximum receive block size which will be accepted by the slave. I2CS0_TIMEOUT.max_rx_block_size_en Field Bits Default Access Description max_rx_block_size_en Enforce Max RX Block Size Controls whether the maximum receive block size setting is actually used.
Page 263 MAX32600 User’s Guide Communication Peripherals 7.1 I²C 7.1.9.1.5 I2CS0_CTRL I2CS0_CTRL.rx_ﬁfo_en Field Bits Default Access Description rx_ﬁfo_en Slave RX FIFO Enable Disable to use 1-byte FIFO mode. I2CS0_CTRL.tx_ﬁfo_en Field Bits Default Access Description tx_ﬁfo_en Slave TX FIFO Enable I2CS0_CTRL.rx_en Field Bits...
Page 264 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description slave_reset_en Slave I2C Reset If set to 1, holds I2C slave instance in reset. 7.1.9.1.6 I2CS0_INTFL I2CS0_INTFL.clk_stretch_to Field Bits Default Access Description clk_stretch_to Clock Stretch Timeout Interrupt Status Write 1 to clear.
Page 265 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CS0_INTFL.rx_ﬁfo_empty Field Bits Default Access Description rx_ﬁfo_empty Rx FIFO Empty Interrupt Status Write 1 to clear. Set to 1 by hardware when the Rx FIFO is empty. I2CS0_INTFL.rx_ﬁfo_2q_full Field Bits Default Access Description rx_ﬁfo_2q_full...
Page 266 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Write 1 to clear. Set to 1 by hardware when the Rx FIFO is full. I2CS0_INTFL.rx_clk_stretch Field Bits Default Access Description rx_clk_stretch Rx Clock Stretch Interrupt Status Write 1 to clear. Set to 1 by hardware when the I2C slave begins a clock stretch during a receive cycle.
Page 267 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description restart_id0 Restart Detected (ID0) Interrupt Status Write 1 to clear. Set to 1 by hardware when the I2C slave detects a restart event (ID0). I2CS0_INTFL.restart_id1 Field Bits Default...
Page 268 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Set to 1 by hardware when the I2C slave detects a Stop event (ID1). I2CS0_INTFL.lost_arbitr_id0 Field Bits Default Access Description lost_arbitr_id0 Lost Arbitration (ID0) Interrupt Status Write 1 to clear. Set to 1 by hardware when the I2C slave detects an arbitration loss event (ID0).
Page 269 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description tx_ﬁfo_empty Tx FIFO Empty Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled. I2CS0_INTEN.tx_ﬁfo_3q_empty Field Bits Default Access Description tx_ﬁfo_3q_empty Tx FIFO 3Q Empty Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled.
Page 270 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description rx_ﬁfo_3q_full Rx FIFO 3Q Full Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled. I2CS0_INTEN.rx_ﬁfo_full Field Bits Default Access Description rx_ﬁfo_full Rx FIFO Full Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled.
Page 271 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description tx_clk_stretch_id1 Tx Clock Stretch (ID1) Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled. I2CS0_INTEN.restart_id0 Field Bits Default Access Description restart_id0 Restart Detected (ID0) Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled.
Page 272 MAX32600 User’s Guide Communication Peripherals 7.1 I²C Field Bits Default Access Description stop_id1 Stop Detected (ID1) Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled. I2CS0_INTEN.lost_arbitr_id0 Field Bits Default Access Description lost_arbitr_id0 Lost Arbitration (ID0) Interrupt Enable 0:Interrupt is disabled; 1:Interrupt is enabled.
Page 273 MAX32600 User’s Guide Communication Peripherals 7.1 I²C I2CS0_BB.scl_in_val Field Bits Default Access Description scl_in_val Bit Bang SCL Input Value I2CS0_BB.sda_in_val Field Bits Default Access Description sda_in_val Bit Bang SDA Input Value I2CS0_BB.rx_ﬁfo_word_count Field Bits Default Access Description rx_ﬁfo_word_count 21:16 ssssss RX FIFO Word Count 7.1.9.1.9 I2CS0_SRX_PEEK...
Page 274 The serial peripheral interface (SPI) module of the MAX32600 microcontroller provides a highly conﬁgurable, ﬂexible, and efﬁcient interface to communicate with a wide variety of SPI slave devices. Three SPI Master ports (SPI0, SPI1, and SPI2) are available on the MAX32600 and each supports the following features: •...
Page 275 MAX32600 User’s Guide Communication Peripherals 7.2 SPI • Up to two slave ready (SR) lines with programmable polarity • Programmable interface timing • Programmable SCK frequency and duty cycle • Programmable SCK alternate timing • SS assertion and deassertion timing with respect to leading/trailing SCK edge Figure 7.5: Multi I/O SPI Support...
Page 276 Note Pin Layout for a detailed mapping of MAX32600 multiplexed function locations. Functional priority distinction is included in the mapping. 7.2.2.1 Compact Layout (7mm x 7mm) Conﬁguration The tables below contain the available pin conﬁgurations for each of the SPI Master ports (SPI0, SPI1, and SPI2).
Page 277 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Logic Signal Port and Pin A) P0.4(0), P0.5(1) B) P1.4(0), P1.5(1) SPI1 Logic Signal Port and Pin A) P0.7(0), P0.0(1), P0.1(2), P0.2(3), P0.3(4) B) P1.7(0), P1.0(1), P1.1(2), P1.2(3), P1.3(4) A) P0.4 B) P1.4 SDIO A) P0.2(2), P0.3(3)
Page 278 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Logic Signal Port and Pin SDIO (MISO) A/B) P2.2(1) Optional: Slave Ready Logic Signal Port and Pin A) P1.7(0) B) P2.4(0) A/B) 2.5(1) 7.2.2.2 Standard Layout (12mm x 12mm) Conﬁguration The tables below contain the available pin conﬁgurations for each of the SPI Master ports (SPI0, SPI1, and SPI2):...
Page 279 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Optional: Slave Ready Logic Signal Port and Pin A) P0.4(0), P0.5(1) B) P2.4(0), P2.5(1) C) P6.4(0), P6.5(1) SPI1 Logic Signal Port and Pin A) P0.7(0), P0.0(1), P0.1(2), P0.2(3), P0.3(4) B) P2.7(0), P1.0(1), P1.1(2), P1.2(3), P1.3(4) C) P6.7(0), P6.0(1), P6.1(2), P6.2(3), P6.3(4)
Page 280 7.2.3 Clock Selection and Conﬁguration The MAX32600 supports programmable SPI clock rates, which are a divisor of the system clock. Each of the three SPI ports is able to set its clock rate independently. To set the base clock rate, write to the appropriate Clock Control register with the value desired to achieve the ideal clock rate for the slave devices.
Page 281: Clock Gating
MAX32600 User’s Guide Communication Peripherals 7.2 SPI [3:0] SPI Clock Rate 0010b (System Clock Source / 2) 0011b (System Clock Source / 4) 0100b (System Clock Source / 8) 0101b (System Clock Source / 16) 0110b (System Clock Source / 32)
Page 282: Static Conﬁguration
MAX32600 User’s Guide Communication Peripherals 7.2 SPI – SPIn_MSTR_CFG • Interrupt Servicing: Status and Control used by an application either directly or via the Peripheral Management Unit’s DMA to efﬁciently service SPI data transfer. – SPIn_FIFO_CTRL – SPIn_INTFL – SPIn_INTEN 7.2.4.1 Static Conﬁguration...
Page 283 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Figure 7.6: SPI Clock Polarity The low bit of the spi_mode ﬁeld controls the clock phase. The SPI clock phase is used to determine when data is sampled and valid on the MISO/MOSI lines.
Page 284 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Figure 7.7: SPI Clock Phase SPI Modes SPI Mode spi_mode xxb SPI Clock State SPI Sample Clock Edge Idle High Falling Edge Idle High Rising Edge Idle Low Falling edge Idle Low Rising Edge Rev.1.3 April 2015...
Page 285 MAX32600 User’s Guide Communication Peripherals 7.2 SPI 7.2.5 SPI Fast Mode Setting up SPI “Fast Mode” is done by setting the SPIn_MSTR_CFG.sck_hi_clk SPIn_MSTR_CFG.sck_lo_clk ﬁelds to 0000b. This sets the SPI SCK clock to a gated version of the system clock, based on the SPI Clock Conﬁguration.
Page 286 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Mnemonic Description [3:2] Size Units Units used to interpret the size ﬁeld. • 0 = Bits • 1 = Bytes • 2 = Pages (See SPIn_MSTR_CFG.page_size for page size deﬁnition) [8:4] Size Size of transaction in terms of units. 1 = 1, 2 = 2, ...
Page 287: Module Spi Registers
MAX32600 User’s Guide Communication Peripherals 7.2 SPI SPI[x] FIFO Start Address End Address SPI0_FIFO_TRANS 0x4010_0000 0x4010_07FE SPI1_FIFO_TRANS 0x4010_1000 0x4010_17FE SPI2_FIFO_TRANS 0x4010_2000 0x4010_27FE Writes to this space result in pushes to the SPI Master Transaction FIFO. This space supports single accesses as well as burst accesses. Access widths of 8-bit, 16-bit, and 32-bit are supported.
Page 288 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Address Register Word Len Description 0x40030018 SPI0_INTEN SPI Master Interrupt Enable/Disable Settings 0x40031000 SPI1_MSTR_CFG SPI Master Control Register 0 0x40031004 SPI1_SS_SR_POLARITY Polarity Control for SS and SR Signals 0x40031008 SPI1_GEN_CTRL SPI Master Control Register 1...
Page 289 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Selects which SS slave select (out of those which are supported) will be asserted during a SPI transaction. SPIn_MSTR_CFG.three_wire_mode Field Bits Default Access Description three_wire_mode 3-Wire Mode • 0: Disabled • 1: Enabled - SDIO[0] will serve as both MOSI and MISO (half duplex mode) SPIn_MSTR_CFG.spi_mode...
Page 290 MAX32600 User’s Guide Communication Peripherals 7.2 SPI SPIn_MSTR_CFG.sck_hi_clk Field Bits Default Access Description sck_hi_clk 11:8 0000b SCK High Clocks Number of system clocks SCK will be in the active state (determined by clock polarity setting). If this is set to 0, "Fast Mode" is enabled, in which SCK is a gated version of the system clock.
Page 291 MAX32600 User’s Guide Communication Peripherals 7.2 SPI SPIn_MSTR_CFG.inact_delay Field Bits Default Access Description inact_delay 19:18 SS Inactive Timing Controls the delay between deassertion of SS at the end of a transaction and reassertion of SS to begin the next transaction, for back-to-back SPI transactions.
Page 292 MAX32600 User’s Guide Communication Peripherals 7.2 SPI 7.2.9.1.2 SPIn_SS_SR_POLARITY SPIn_SS_SR_POLARITY.ss_polarity Field Bits Default Access Description ss_polarity SS Signal Polarity Deﬁnes polarity of each implemented SS slave select signal, where 0=active low, 1=active high. SPIn_SS_SR_POLARITY.fc_polarity Field Bits Default Access Description fc_polarity...
Page 293 MAX32600 User’s Guide Communication Peripherals 7.2 SPI • 0: Transaction FIFO is disabled/forced to reset • 1: Transaction FIFO is enabled SPIn_GEN_CTRL.rx_ﬁfo_en Field Bits Default Access Description rx_ﬁfo_en Results FIFO Enable • 0: Results FIFO is disabled/forced to reset • 1: Results FIFO is enabled SPIn_GEN_CTRL.bit_bang_mode...
Page 294 MAX32600 User’s Guide Communication Peripherals 7.2 SPI SPIn_GEN_CTRL.bb_sr_in Field Bits Default Access Description bb_sr_in Bit Bang SR Input Writes have no effect. When read, returns the current state of the ﬂow control (0=deasserted, 1=asserted) SPIn_GEN_CTRL.bb_sck_in_out Field Bits Default Access Description...
Page 295 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Deﬁnes output state of SDIO pins (Bit Bang only) SPIn_GEN_CTRL.bb_sdio_dr_en Field Bits Default Access Description bb_sdio_dr_en 19:16 0000b Bit Bang SDIO Drive Enable Enables output drive of SDIO pins (Bit Bang only) 7.2.9.1.4 SPIn_FIFO_CTRL SPIn_FIFO_CTRL.tx_ﬁfo_ae_lvl...
Page 296 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Deﬁnes number of used FIFO entries (bytes) required to assert Almost Full ﬂag. FIFO depth is 32 bytes. SPIn_FIFO_CTRL.rx_ﬁfo_used Field Bits Default Access Description rx_ﬁfo_used 29:24 Results FIFO Used Returns number of currently used byte entries in the Results FIFO 7.2.9.1.5 SPIn_SPCL_CTRL...
Page 297 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Deﬁnes output mode of SDIO when SS Sample Mode is active. SPIn_SPCL_CTRL.ss_sa_sdio_dr_en Field Bits Default Access Description ss_sa_sdio_dr_en 11:8 0000b SDIO Active Drive Mode Deﬁnes output drive mode of SDIO when SS Sample Mode is active.
Page 298 MAX32600 User’s Guide Communication Peripherals 7.2 SPI Field Bits Default Access Description tx_ready Transaction Ready Int Status Write 1 to clear. 0:Int not active, 1:Interrupt has been triggered Set when transaction FIFO is empty and selected Slave Select is deasserted.
Page 299 MAX32600 User’s Guide Communication Peripherals 7.2 SPI 0:Int not active, 1:Interrupt has been triggered Set when the results FIFO is in the ’almost full’ state. 7.2.9.1.7 SPIn_INTEN SPIn_INTEN.tx_stalled Field Bits Default Access Description tx_stalled Transaction Stalled Int Enable 0: Interrupt source disabled; 1:Interrupt enabled.
Page 300 MAX32600 User’s Guide Communication Peripherals 7.2 SPI 0: Interrupt source disabled; 1:Interrupt enabled. SPIn_INTEN.tx_ﬁfo_ae Field Bits Default Access Description tx_ﬁfo_ae TXFIFO Almost Empty Int Enable 0: Interrupt source disabled; 1:Interrupt enabled. SPIn_INTEN.rx_ﬁfo_af Field Bits Default Access Description rx_ﬁfo_af RXFIFO Almost Full Int Enable 0: Interrupt source disabled;...
Page 301: Uart
7.3 UART 7.3.1 Overview The MAX32600 provides two UART ports which can be used to communicate with external devices requiring an asynchronous serial protocol. Features of the MAX32600 UARTs: • Flexible baud rate generation based on the module clock frequency (equal to the system clock source or a subdivide of the system clock source) •...
Page 302: Rev.1.3 April
MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.2.1 Compact Layout Conﬁguration The tables below contains the available pin conﬁgurations for each of the UART ports (UART0 and UART1): UART0 Logic Signal Port and Pin A) P1.0 B) P2.0 D) P0.0 A) P1.1 B) P2.1 D) P0.1...
Page 303 MAX32600 User’s Guide Communication Peripherals 7.3 UART Logic Signal Port and Pin A) P1.3 B) P1.5 C) P7.3 D) P0.3 UART1 Logic Signal Port and Pin A) P1.2 B) P1.4 C) P7.2 D) P2.6 A) P1.3 B) P1.5 C) P7.3 D) P2.7 A) P2.6 B) P1.6 C) P7.6...
Page 304 7.3.4 UART Clock Selection and Clock Gating The UARTs in the MAX32600 use the System Core Clock. To enable a speciﬁc UART, it is necessary enable clocks for the port. In addition, the baud clock enable bit must be set in UARTn_CTRL.baud_clk_en...
Page 305 MAX32600 User’s Guide Communication Peripherals 7.3 UART The formulas for calculating the UARTn_BAUD_INT UARTn_BAUD_DIV_128 are: System Core Clock DESIRED BAUD RATE • UARTn_BAUD_INT is equal to the integer portion of div. UART n BAUD • UARTn_BAUD_DIV_128 is the decimal portion of div converted to an integer.
Page 306: Clear To Send
MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.6 Transferring and Receiving Data Data to be transferred must be written to the TX FIFO by writing to the UARTn_TX_RX_FIFO register (either directly or using a PMU channel). This data will be transferred out by the hardware automatically a character at a time in the order that it was written to the FIFO.
Page 307: Ready To Send
MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.8.2 Ready to Send The RTS (Ready to Send) line is an output from the UART that notiﬁes an external device whether or not the UART is ready to receive more data. When hardware ﬂow control is enabled, the RTS output is automatically driven low (active state) whenever the RX FIFO on the UART is not full.
Page 308 MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.9.1.1 UARTn_CTRL UARTn_CTRL.rx_threshold Field Bits Default Access Description rx_threshold 100b Receive FIFO Interrupt Threshold Speciﬁes the depth of receive FIFO that triggers an interrupt. Valid settings are 1-7. UARTn_CTRL.parity_enable Field Bits Default Access...
Page 309 MAX32600 User’s Guide Communication Peripherals 7.3 UART Field Bits Default Access Description parity_bias Parity Basis Select • 0:Parity is based on number of 1 bits in the frame. • 1:Parity is based on number of 0 bits in the frame.
Page 310 MAX32600 User’s Guide Communication Peripherals 7.3 UART • 01:6-bit character transfer • 10:7-bit character transfer • 11:8-bit character transfer UARTn_CTRL.stop_bit_mode Field Bits Default Access Description stop_bit_mode Stop Bit Mode Select • 0:One stop bit is generated. • 1:Either 1.5 or 2 stop bits are generated.
Page 311 MAX32600 User’s Guide Communication Peripherals 7.3 UART • 1:Baud clock generation enabled. 7.3.9.1.2 UARTn_STATUS UARTn_STATUS.tx_busy Field Bits Default Access Description tx_busy TX Busy 1: The UART is transmitting data. UARTn_STATUS.rx_busy Field Bits Default Access Description rx_busy RX Busy 1: The UART is receiving data.
Page 312 MAX32600 User’s Guide Communication Peripherals 7.3 UART 1: The Receive FIFO is full. UARTn_STATUS.tx_ﬁfo_empty Field Bits Default Access Description tx_ﬁfo_empty TX FIFO Empty 1: The Transmit FIFO is empty. UARTn_STATUS.tx_ﬁfo_full Field Bits Default Access Description tx_ﬁfo_full TX FIFO Full 1: The Transmit FIFO is full.
Page 313 MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.9.1.3 UARTn_INTEN UARTn_INTEN.rx_frame_error Field Bits Default Access Description rx_frame_error RX Frame Error Interrupt Enable 0:Interrupt is disabled, 1:Interrupt is enabled UARTn_INTEN.rx_parity_error Field Bits Default Access Description rx_parity_error RX Parity Error Interrupt Enable 0:Interrupt is disabled, 1:Interrupt is enabled UARTn_INTEN.cts_change...
Page 314 MAX32600 User’s Guide Communication Peripherals 7.3 UART UARTn_INTEN.rx_over_threshold Field Bits Default Access Description rx_over_threshold RX FIFO Over Threshold Int Enable 0:Interrupt is disabled, 1:Interrupt is enabled UARTn_INTEN.tx_almost_empty Field Bits Default Access Description tx_almost_empty TX FIFO Almost Empty Int Enable 0:Interrupt is disabled, 1:Interrupt is enabled UARTn_INTEN.tx_half_empty...
Page 315 MAX32600 User’s Guide Communication Peripherals 7.3 UART UARTn_INTFL.rx_parity_error Field Bits Default Access Description rx_parity_error RX Parity Error Interrupt Status Write 0 to clear. Set to 1 by hardware when int condition occurs. UARTn_INTFL.cts_change Field Bits Default Access Description cts_change CTS Value Change Interrupt Status Write 0 to clear.
Page 316 MAX32600 User’s Guide Communication Peripherals 7.3 UART Write 0 to clear. Set to 1 by hardware when int condition occurs. UARTn_INTFL.tx_almost_empty Field Bits Default Access Description tx_almost_empty TX FIFO Almost Empty Int Status Write 0 to clear. Set to 1 by hardware when int condition occurs.
Page 317 MAX32600 User’s Guide Communication Peripherals 7.3 UART 7.3.9.1.6 UARTn_BAUD_DIV_128 UARTn_BAUD_DIV_128.div Field Bits Default Access Description Decimal portion of baudrate DIV. DIV=UARTn_BAUD_INT[11:0]+(UARTn_BAUD_DIV_128[6:0]/128) 7.3.9.1.7 UARTn_TX_FIFO_OUT UARTn_TX_FIFO_OUT.tx_ﬁfo Field Bits Default Access Description tx_ﬁfo TX FIFO Output Writes have no effect. Reading from this register returns the current value at the output of the TX FIFO, without changing the contents of the TX FIFO.
Page 318 7.4.1 Overview The MAX32600 includes a Universal Serial Bus (USB) peripheral dedicated to device operation. The peripheral is a USB 2.0 compliant, full-speed device and includes a Serial Interface Engine (SIE) that connects to the internal USB transceiver and pin drivers.
Page 319: Usb Reset Deﬁnitions
MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface 7.4.2 Operation The USB device controller supports a total of eight endpoints with programmable conﬁguration. 7.4.2.1 USB Reset Deﬁnitions The USB device is reset under the following conditions: • USB Bus Reset: Host issues a bus reset.
Page 320 In this document a reset condition without any qualiﬁer refers to a System Reset. The term USB reset refers to either a USB Bus Reset or a USB Device Reset. Figure 7.8: USB Device Block Diagram 7.4.3 USB Endpoints The MAX32600 supports eight USB endpoints that can be individually conﬁgured. Rev.1.3 April 2015 Maxim Integrated Page 302...
Page 321: Endpoint Control Register
MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Each endpoint supports: • Single / Double buffer • Programmable buffer starting address • Programmable interrupt generation • Ability to STALL a packet • Bulk and Interrupt transfer • Control transfer (endpoint 0 only) •...
Page 322: Endpoint Buffer Descriptor
MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface – Enable for IN or OUT data transfers, ep_int_en – Enable for NAK handshakes sent to host ep_nak_en • Endpoint STALL status ep_stall • Send a STALL to host for status stage ep_st_stall •...
Page 323: Module Usb Registers
MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface 7.4.4 Registers (USB) 7.4.4.1 Module USB Registers Address Register Word Len Description 0x4010C000 USB_CN USB Control Register 0x4010C200 USB_DEV_ADDR USB Device Address Register 0x4010C204 USB_DEV_CN USB Device Control Register 0x4010C208 USB_DEV_INTFL...
Page 324 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Enabling the USB Device interface (setting this bit from 0 to 1) causes a reset of the USB Device internal state. • 0: Disabled • 1: Enabled 7.4.4.1.2 USB_DEV_ADDR USB_DEV_ADDR.dev_addr Field...
Page 325 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • 1: Connect internal pullup resistor between DPLUS and VBUS. USB_DEV_CN.ulpm Field Bits Default Access Description ulpm USB Low Power Mode • 0: USB transceiver in normal operation • 1: USB transceiver will enter a low power mode USB_DEV_CN.urst...
Page 326 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_DEV_CN.ﬁfo_mode Field Bits Default Access Description ﬁfo_mode FIFO Mode This register bit, when set, conﬁgures the device controller to respond to an incoming IN request as soon as the device controller’s FIFO become non-empty, instead of waiting for the full packet to be received by the FIFO.
Page 327 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface This interrupt ﬂag indicates that USB bus activity has been detected (the USB controller has received a SYNC ﬁeld). Set to 1 by hardware when the associated interrupt condition has been detected. Write 1 to clear.
Page 328 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description vbus VBUS Detect Interrupt Flag This interrupt ﬂag indicates that VBUS has powered up (level transition from 0 to 1). Set to 1 by hardware when the associated interrupt condition has been detected. Write 1 to clear.
Page 329 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Set to 1 by hardware when the associated interrupt condition has been detected. Write 1 to clear. USB_DEV_INTFL.ep_out Field Bits Default Access Description ep_out Endpoint OUT Interrupt Flag This interrupt ﬂag indicates that an Endpoint OUT Interrupt is pending at one or more endpoints.
Page 330 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description buf_ovr Buffer Overﬂow Interrupt Flag This interrupt ﬂag indicates that a buffer overﬂow error has been detected by one or more endpoints. Set to 1 by hardware when the associated interrupt condition has been detected. Write 1 to clear.
Page 331 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • 1: An interrupt will be reported to the CPU (if not otherwise masked) when the associated interrupt ﬂag is set. USB_DEV_INTEN.bact Field Bits Default Access Description bact USB Bus Activity Interrupt Flag •...
Page 332 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_DEV_INTEN.no_vbus Field Bits Default Access Description no_vbus No VBUS Interrupt Flag • 0: No interrupt will be triggered when the associated interrupt ﬂag is set. • 1: An interrupt will be reported to the CPU (if not otherwise masked) when the associated interrupt ﬂag is set.
Page 333 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description setup Setup Packet Interrupt Flag • 0: No interrupt will be triggered when the associated interrupt ﬂag is set. • 1: An interrupt will be reported to the CPU (if not otherwise masked) when the associated interrupt ﬂag is set.
Page 334 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • 0: No interrupt will be triggered when the associated interrupt ﬂag is set. • 1: An interrupt will be reported to the CPU (if not otherwise masked) when the associated interrupt ﬂag is set.
Page 335 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface 7.4.4.1.7 USB_CUR_BUF USB_CUR_BUF.out_buf Field Bits Default Access Description out_buf 0000h OUT Transfer Current Buffers For double-buffered endpoints, each bit of this ﬁeld indicates the current buffer that the USB controller will use for an OUT transfer, as follows: •...
Page 336 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface For double-buffered endpoints, each bit of this ﬁeld indicates the current buffer that the USB controller will use for an IN transfer, as follows: • bit is set to 0: buffer 0 will be used for this endpoint •...
Page 337 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • bit 2 : owner for Endpoint 2 IN buffer 0 • bit 3 : owner for Endpoint 3 IN buffer 0 • bit 4 : owner for Endpoint 4 IN buffer 0 •...
Page 338 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface 7.4.4.1.9 USB_OUT_OWNER USB_OUT_OWNER.buf0_owner Rev.1.3 April 2015 Maxim Integrated Page 320...
Page 339 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description buf0_owner 00000000h Owner for OUT Buffer 0 for Endpoints Each bit in this ﬁeld indicates the owner of the corresponding Endpoint OUT buffer 0 as follows: •...
Page 340 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • bit 18 : owner for Endpoint 2 OUT buffer 1 • bit 19 : owner for Endpoint 3 OUT buffer 1 • bit 20 : owner for Endpoint 4 OUT buffer 1 •...
Page 341 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description inbav2 Endpoint 2 Buffer Available Interrupt Flag This interrupt ﬂag is set by the USB controller after it has successfully transferred an IN packet to the USB host and has received an ACK handshake in reply. This indicates that the endpoint buffer is now available to be written by software.
Page 342 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface This interrupt ﬂag is set by the USB controller after it has successfully transferred an IN packet to the USB host and has received an ACK handshake in reply. This indicates that the endpoint buffer is now available to be written by software.
Page 343 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Write 1 to clear. USB_OUT_INT.outdav1 Field Bits Default Access Description outdav1 Endpoint 1 Data Available Interrupt Flag This interrupt ﬂag is set by the USB controller when it has successfully received an OUT packet from the host and has loaded it into the designated endpoint buffer.
Page 344 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_OUT_INT.outdav4 Field Bits Default Access Description outdav4 Endpoint 4 Data Available Interrupt Flag This interrupt ﬂag is set by the USB controller when it has successfully received an OUT packet from the host and has loaded it into the designated endpoint buffer.
Page 345 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description outdav7 Endpoint 7 Data Available Interrupt Flag This interrupt ﬂag is set by the USB controller when it has successfully received an OUT packet from the host and has loaded it into the designated endpoint buffer.
Page 346 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description This interrupt ﬂag is set by the USB controller after it sends a NAK handshake to the host in response to an IN request. This indicates that the endpoint buffer has no data available to be transmitted to the USB host.
Page 347 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface This interrupt ﬂag is set by the USB controller after it sends a NAK handshake to the host in response to an IN request. This indicates that the endpoint buffer has no data available to be transmitted to the USB host.
Page 348 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Write 1 to clear. USB_DMA_ERR_INT.dma_err1 Field Bits Default Access Description dma_err1 Endpoint 1 DMA Error Interrupt Flag This interrupt ﬂag is set by the USB controller when a USB DMA error occurs, meaning that the USB controller was unable to transfer data to or from the corresponding endpoint over the AHB bus.
Page 349 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_DMA_ERR_INT.dma_err4 Field Bits Default Access Description dma_err4 Endpoint 4 DMA Error Interrupt Flag This interrupt ﬂag is set by the USB controller when a USB DMA error occurs, meaning that the USB controller was unable to transfer data to or from the corresponding endpoint over the AHB bus.
Page 350 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description dma_err7 Endpoint 7 DMA Error Interrupt Flag This interrupt ﬂag is set by the USB controller when a USB DMA error occurs, meaning that the USB controller was unable to transfer data to or from the corresponding endpoint over the AHB bus.
Page 351 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface This interrupt ﬂag is set by the USB controller when a data packet to or from the USB host is larger than the size of the corresponding endpoint buffer in memory.
Page 352 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Field Bits Default Access Description buf_ovr6 Endpoint 6 Buffer Overﬂow Interrupt Flag This interrupt ﬂag is set by the USB controller when a data packet to or from the USB host is larger than the size of the corresponding endpoint buffer in memory.
Page 353 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_SETUP0.byte2 Field Bits Default Access Description byte2 23:16 SETUP Packet Byte 2 Byte 2 of the last SETUP packet received by the USB controller. USB_SETUP0.byte3 Field Bits Default Access Description byte3...
Page 354 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_SETUP1.byte6 Field Bits Default Access Description byte6 23:16 SETUP Packet Byte 6 Byte 6 of the last SETUP packet received by the USB controller. USB_SETUP1.byte7 Field Bits Default Access Description byte7...
Page 355 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface USB_EP.ep_buf2 Field Bits Default Access Description ep_buf2 Endpoint Double Buffered Enable • 0: Endpoint is single buffered. • 1: Endpoint is double buffered. USB_EP.ep_int_en Field Bits Default Access Description ep_int_en Endpoint Transfer Complete Interrupt Enable 1: Enable generation of interrupts for this endpoint upon completion of an IN or OUT data transfer.
Page 356 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface Write to 1 to reset the data toggle ﬁeld to DATA0 and reset the current buffer to buffer 0. In addition, the IN and OUT Buffer Owner bits for this endpoint will be cleared as well.
Page 357 MAX32600 User’s Guide Communication Peripherals 7.4 USB Device Interface • 0: Do not send ACK. • 1: Send ACK to host for status stage. Upon receiving a SETUP packet, this bit is automatically cleared to 0. Rev.1.3 April 2015 Maxim Integrated...
Page 358: Afe Overview
One key feature of the analog front end functions on the MAX32600 is that they can be set up to run largely without CPU intervention, allowing sequences of ADC readings and/or sequences of DAC channel output voltages to run while the main Cortex-M3 CPU core is in a low-power sleep mode.
Page 359: Rev.1.3 April
The AFE includes four low-power comparators which can be used in parallel with the main op amps. These comparators are speciﬁcally optimized for low power consumption, making them ideal to use as wakeup sources to bring the MAX32600 out of a low power state.
Page 360 Peripheral Management Unit (PMU) the MAX32600 can be used instead of the CPU to perform tasks that must take place during long sequences of analog operations. This allows sequences of ADC readings and/or sequences of DAC channel output voltages to run while the Cortex-M3 core is in a low-power sleep mode (reference...
Page 361 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix analog front end. Prior to conﬁguring the Analog Reconﬁguration Matrix for a speciﬁc application, the user must thoroughly understand the conﬁguration options to prevent setting up an undesirable conﬁguration. Rev.1.3 April 2015...
Page 362 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Note It is possible to conﬁgure the matrix in ways that short pads together or create undesired current levels or loads. Careful attention to all the register settings that control the matrix is imperative.
Page 363 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Figure 8.2: Analog Reconﬁguration Sub-Matrix 1 Diagram Rev.1.3 April 2015 Maxim Integrated Page 345...
Page 364 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Figure 8.3: Analog Reconﬁguration Sub-Matrix 2 Diagram Rev.1.3 April 2015 Maxim Integrated Page 346...
Page 365 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Figure 8.4: Analog Reconﬁguration Sub-Matrix 3 Diagram Rev.1.3 April 2015 Maxim Integrated Page 347...
Page 366 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Reconﬁguration Matrix Inputs The register ﬁelds that control each mux for the inputs to the Analog Reconﬁguration Sub-Matrix are: • dac0_sel Top-Level Multiplexer • dac1_sel Top-Level Multiplexer • sno_or_sel Single-Pole, Single-Throw (SPST) •...
Page 367 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Single-Pole, Single-Throw (SPST) Similarly the four SPST pins SNO0/1/2/3 are selected by a 4:1 mux using register ﬁeld sno_or_sel creating the signal sno_or. scm_or_sel selects between the four SPST pins SCM0/1/2/3 creating the signal scm_or. SPST switches 2 and 3 are only available in the 12mm x 12mm package and cannot be selected in the 7mm x 7mm or WLP packages.
Page 368 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Analog DACOUT Op Amp Positive Op Amp Negative Op Amp Output LED Observe Port SCM Pin SNO Pin Reconﬁguration Input Input Input Matrix SNO1 IND+ IND- OUTD SCM3 SNO3 Within each analog reconﬁguration matrix, there are six multiplexers and one switch that control the op amp and comparator inputs as well as the SPST switch and op amp negative input external pins.
Page 369: Comparators
MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix one n-channel and one p-channel, that together allow rail-to-rail operation. In cases where the op amp input bias is within 600mV of V or 650mV of V , better THD performance and bias-independent offset can be achieved if only one of the two input pairs is selected. Setting control bit...
Page 370 – 3: Reserved Each comparator has a direct output lpcmp[X] that drives into the MAX32600 logic core. The primary purpose of the low-power comparators is to provide a low-power means for detecting external events and wake the device from low-power sleep or stop modes. Each comparator has an associated wake-up detector, set by the...
Page 371: Module Afe Registers
MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Setting clear_wud_comp_X to 1 forces the wake-up detector comparator event seen (ces) output to 0. With en_wud_comp_X[1:0] set to 00b, the wakeup detector is inactive and the wakeup detector ces output stays at 0. With...
Page 372 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_INTR.op_comp_b_int Field Bits Default Access Description op_comp_b_int Op Amp B Comparator Event Interrupt Flag Set by hardware when the associated interrupt condition occurs. Write 1 to clear. AFE_INTR.op_comp_c_int Field Bits...
Page 373 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Set by hardware when the associated interrupt condition occurs. Write 1 to clear. AFE_INTR.lp_comp_b_int Field Bits Default Access Description lp_comp_b_int Low-Power Comparator B Event Interrupt Flag Set by hardware when the associated interrupt condition occurs.
Page 374 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description op_comp_a_nma Op Amp Comparator A Non-Maskable Event Flag Set by hardware when the associated interrupt condition occurs. This is not a standard interrupt ﬂag; instead it is a non-maskable, asynchronous output that goes directly to the associated interrupt detector in the PMU.
Page 375 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description op_comp_d_nma Op Amp Comparator D Non-Maskable Event Flag Set by hardware when the associated interrupt condition occurs. This is not a standard interrupt ﬂag; instead it is a non-maskable, asynchronous output that goes directly to the associated interrupt detector in the PMU.
Page 376 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description lp_comp_c_nma Low-Power Comparator C Non-Maskable Event Flag Set by hardware when the associated interrupt condition occurs. This is not a standard interrupt ﬂag; instead it is a non-maskable, asynchronous output that goes directly to the associated interrupt detector in the PMU.
Page 377 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description op_comp_b_pol Op Amp Comparator B Polarity Select • 0: Rising Edge • 1: Falling Edge AFE_INTR.op_comp_c_pol Field Bits Default Access Description op_comp_c_pol Op Amp Comparator C Polarity Select •...
Page 378 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 0: Rising Edge • 1: Falling Edge AFE_INTR.lp_comp_b_pol Field Bits Default Access Description lp_comp_b_pol Low-Power Comparator B Polarity Select • 0: Rising Edge • 1: Falling Edge AFE_INTR.lp_comp_c_pol Field...
Page 379 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_INTR.op_comp_a_en Field Bits Default Access Description op_comp_a_en Op Amp Comparator A Interrupt Enable/ Disable • 0: Interrupt is disabled • 1: Interrupt is enabled AFE_INTR.op_comp_b_en Field Bits Default Access Description...
Page 380 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description op_comp_d_en Op Amp Comparator D Interrupt Enable/ Disable • 0: Interrupt is disabled • 1: Interrupt is enabled AFE_INTR.lp_comp_a_en Field Bits Default Access Description lp_comp_a_en...
Page 381 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description lp_comp_c_en Low-Power Comparator C Interrupt Enable/ Disable • 0: Interrupt is disabled • 1: Interrupt is enabled AFE_INTR.lp_comp_d_en Field Bits Default Access Description lp_comp_d_en Low-Power Comparator D Interrupt Enable/ Disable •...
Page 382 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description led_cfg_port1 LED Port 1 Drive Conﬁguration • 00b: drive LED SinkPort 1 from OUTC • 01b: drive LED Sink Port 1 from OUTD • 1xb: disable LED Sink Port 1 AFE_CTRL0.clear_wud_comp_a...
Page 383 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description clear_wud_comp_c Clear Wakeup Detect for Low-Power Com- parator C • 0: No operation • 1: Clear wakeup detection mode for comparator AFE_CTRL0.clear_wud_comp_d Field Bits Default...
Page 384 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description en_wud_comp_b 11:10 Set Wakeup Detect for Low-Power Com- parator B • 0xb: No operation • 10b: Set falling edge wakeup detect mode for comparator • 11b: Set rising edge wakeup detect mode for comparator AFE_CTRL0.en_wud_comp_c...
Page 385 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL0.in_mode_comp_a Field Bits Default Access Description in_mode_comp_a 17:16 Low-Power Comparator A Input Mode • 00b: Enable both N-channel and P-channel • 01b: Enable N-channel only • 10b: Enable P-channel only •...
Page 386 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 01b: Enable N-channel only • 10b: Enable P-channel only • 11b: Reserved AFE_CTRL0.in_mode_comp_d Field Bits Default Access Description in_mode_comp_d 23:22 Low-Power Comparator D Input Mode • 00b: Enable both N-channel and P-channel •...
Page 387 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description bias_mode_comp_b 27:26 Low-Power Comparator B Bias Mode • 00b: 0.52uA, delay 4.0us • 01b: 1.4uA, delay 1.7us • 10b: 2.8uA, delay 1.1us • 11b: 5.1uA, delay 0.7us AFE_CTRL0.bias_mode_comp_c...
Page 388 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 11b: 5.1uA, delay 0.7us 8.2.2.1.3 AFE_CTRL1 AFE_CTRL1.tmon_current_en Field Bits Default Access Description tmon_current_en Temperature Sense Current Source Enable • 0: Disabled • 1: Enable the current source for the temperature sensor.
Page 389 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 0: Disabled • 1: Output powers down in milliseconds instead of seconds. Must be reset to 0 before the ref is re-powered on using refadc_outen. Can also be used to improve the REFADC slew rate (when lowering the adcrefsel setting) by setting to 1 for 10ms.
Page 390 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 00b: 1.024V • 01b: 1.5V • 10b: 2.048V • 11b: 2.5V AFE_CTRL1.dacrefsel Field Bits Default Access Description dacrefsel DAC Reference Voltage Select • 00b: 1.024V • 01b: 1.5V • 10b: 2.048V •...
Page 391 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description refadc_outen Internal ADC Reference Output Enable • 0: Internal ADC reference powered down; REFADC may be driven externally • 1: Internal ADC reference powered up; REFADC is driven by internal ADC reference output AFE_CTRL1.refdac_outen...
Page 392 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 0: No additional pole • 1: Additional pole enabled to compensate zero from external resistance AFE_CTRL1.refdac_cp Field Bits Default Access Description refdac_cp DAC Reference Compensation Enable • 0: No additional pole •...
Page 393 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description abus_page_2_0 22:20 000b Reserved Field, Do Not Modify This ﬁeld should not be modiﬁed by the user. Leave at default setting (zero) for proper operation.
Page 394 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description hyst_comp_a Low-Power Comparator A Hysteresis Magnitude Select Selects hysteresis magnitude setting for comparator. • 00b: 0mV • 01b: 7.5mV • 10b: 15mV • 11b: 30mV AFE_CTRL2.hyst_comp_b...
Page 395 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Selects hysteresis magnitude setting for comparator. • 00b: 0mV • 01b: 7.5mV • 10b: 15mV • 11b: 30mV AFE_CTRL2.hyst_comp_d Field Bits Default Access Description hyst_comp_d Low-Power Comparator D Hysteresis Magnitude Select Selects hysteresis magnitude setting for comparator.
Page 396 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 1: Vp Vn-Vhys AFE_CTRL2.hy_pol_comp_b Field Bits Default Access Description hy_pol_comp_b Low-Power Comparator B Hysteresis Polarity Select Selects hysteresis polarity setting for comparator. • 0: Vp Vn+Vhys • 1: Vp Vn-Vhys AFE_CTRL2.hy_pol_comp_c...
Page 397 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Selects hysteresis polarity setting for comparator. • 0: Vp Vn+Vhys • 1: Vp Vn-Vhys AFE_CTRL2.poweru_comp_a Field Bits Default Access Description poweru_comp_a Low-Power Comparator A Powerup/Enable Powerup/enable selection for comparator. • 0: Disabled (powered down) •...
Page 398 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description poweru_comp_c Low-Power Comparator C Powerup/Enable Powerup/enable selection for comparator. • 0: Disabled (powered down) • 1: Enabled (powered up) AFE_CTRL2.poweru_comp_d Field Bits Default Access Description...
Page 399 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description dacout_en1 Connects dac_or1 output (selected by dac_sel_b) to SNO0 pin. • 0: No connect • 1: Connect dac_or1 - SNO0 AFE_CTRL2.dacout_en2 Field Bits Default Access...
Page 400 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description scm_or_sel 22:20 000b Selects source for SCM_or signal SCMx pad select into SCM_or signal feeding OPAMP negative input MUX, comparator positive input, and OPAMP negative input pad •...
Page 401 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL2.dac1_sel Field Bits Default Access Description dac1_sel Internal input stage select for dac1 Connects DAC1P or DAC1N to dac1 input used on DAC_or select MUX and low-power comparator positive input MUX •...
Page 402 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL3.pu_opamp_c Field Bits Default Access Description pu_opamp_c Op Amp C Power Up • 0: Op amp is powered down • 1: Op amp is powered up AFE_CTRL3.pu_opamp_d Field Bits Default...
Page 403 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description gnd_sel_opamp_b Op Amp B Positive Input Ground Select • 0: Internal ground switch for op amp B disabled • 1: Ground switch is enabled, connecting INB+ to ground internally.
Page 404 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix If ADC_INTR.spst_sw0_ctrl = 0, this bit controls the state of SPST switch 0 (from SNO0 to SCM0) as follows: • 0: Switch open • 1: Switch closed If ADC_INTR.spst_sw0_ctrl = 1, the setting of this bit has no effect, and the state of SPST switch 0 is controlled by the output of pulse train PT8.
Page 405 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL3.close_spst3 Field Bits Default Access Description close_spst3 Switch Close for SPST3 If ADC_INTR.spst_sw3_ctrl = 0, this bit controls the state of SPST switch 3 (from SNO3 to SCM3) as follows: •...
Page 406 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL3.en_pch_opamp_c Field Bits Default Access Description en_pch_opamp_c Op Amp C P-Channel Input Stage Enable • 0: P-Channel input stage for this op amp is disabled. • 1: P-Channel input stage for this op amp is enabled.
Page 407 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description en_nch_opamp_b Op Amp B N-Channel Input Stage Enable • 0: N-Channel input stage for this op amp is disabled. • 1: N-Channel input stage for this op amp is enabled.
Page 408 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Connects the positive (noninverting) input of op amp A internally as follows. • 0: Connected to pin INA+ • 1: Connected to the output from DAC • 2: Connected to pin SNO[0-3] or to high impedance (as selected by AFE_CTRL2.sno_or_sel) •...
Page 409 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Connects the positive (noninverting) input of op amp C internally as follows. • 0: Connected to pin INC+ • 1: Connected to the output from DAC • 2: Connected to pin SNO[0-3] or to high impedance (as selected by AFE_CTRL2.sno_or_sel) •...
Page 410 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Connects the negative (inverting) input of op amp A internally as follows. • 0: Connected to pin INA- • 1: Connected to pin OUTA (voltage follower mode) • 2: Connected to pin SCM[0-3] or to high impedance (as selected by AFE_CTRL2.scm_or_sel) •...
Page 411 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 2: Connected to pin SCM[0-3] or to high impedance (as selected by AFE_CTRL2.scm_or_sel) • 3: Connected to both pin SCM[0-3]/high impedance AND INC- AFE_CTRL4.n_in_sel_opamp_d Field Bits Default Access Description...
Page 412 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix AFE_CTRL4.dac_sel_b Field Bits Default Access Description dac_sel_b 19:18 DAC Output Mux Select to dac_or1 Stage MUX that selects 1 of 4 DAC outputs for internal signal DAC_or1, which can be further selected for the OPAMPB positive input, OPAMPB negative pad, or SNO1 pad via other MUX selections •...
Page 413 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description dac_sel_d 23:22 DAC Output Mux Select to dac_or3 Stage MUX that selects 1 of 4 DAC outputs for internal signal DAC_or3, which can be further selected for the OPAMPD positive input, OPAMPD negative pad, or SNO3 pad via other MUX selections •...
Page 414 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix INB- pad select (states 1 and 3 connect two pads together leading to potentially large current ﬂow) • 2’d0: hiZ - INB- • 2’d1: LED Observe Port 0 INB- • 2’d2: DAC_or1 - INB- •...
Page 415 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 2’d1: LED Observe Port 1 - IND- • 2’d2: DAC_or3 - IND- • 2’d3: DAC_or3 - IND- LED Observe Port 1 8.2.2.1.7 AFE_CTRL5 AFE_CTRL5.pos_in_sel_comp_a Field Bits Default Access Description...
Page 416 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 1: SCM0-3 pin • 2: DAC1 positive/negative output • 3: DAC3 output • 4: LED Observe Port 0 • 5: DAC1 positive/negative output AND INB+ • 6: DAC3 output AND INB+ •...
Page 417 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix Field Bits Default Access Description pos_in_sel_comp_d 11:9 000b Low-Power Comparator D Positive Input Select • 0: IND+ • 1: SCM0-3 pin • 2: DAC1 positive/negative output • 3: DAC3 output •...
Page 418 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 7: DAC2 output AND SNO0 AFE_CTRL5.neg_in_sel_comp_b Field Bits Default Access Description neg_in_sel_comp_b 17:15 000b Low-Power Comparator B Negative In- put Select • 0: INB- • 1: SNO0-3 pin • 2: DAC0 positive/negative output •...
Page 419 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 3: DAC2 output • 4: LED Observe Port 1 • 5: DAC0 positive/negative output AND INC- • 6: DAC2 output AND INC- • 7: DAC2 output AND SNO2 AFE_CTRL5.neg_in_sel_comp_d...
Page 420 MAX32600 User’s Guide Analog Front End 8.2 AFE Reconﬁguration Matrix • 0: Op Amp Mode • 1: Comparator Mode AFE_CTRL5.op_cmp_b Field Bits Default Access Description op_cmp_b Mode Select for Op Amp B • 0: Op Amp Mode • 1: Comparator Mode AFE_CTRL5.op_cmp_c...
Page 421 8.3.2 ADC Architecture The ADC on the MAX32600 is a cyclic analog-to-digital converter. This architecture - sometimes referred to as a recycling architecture - does not alter the reference voltage; rather, any error or residue of the ampliﬁer is doubled. There are certain similarities with a Pipeline ADC: each cycle calculates 1-bit. However, unlike a Pipeline ADC, the ampliﬁed value of the input is summed to a reference voltage and residue voltage from this process is further ampliﬁed during each successive...
Page 422 MAX32600 User’s Guide Analog Front End 8.3 ADC cycle until the desired resolution is reached. This corresponds with the output value of the ADC. Figure 8.5: ADC Signal Chain Diagram Rev.1.3 April 2015 Maxim Integrated Page 404...
Page 423 MAX32600 User’s Guide Analog Front End 8.3 ADC 8.3.3 ADC Operation The control registers for the ADC can be accessed directly by the CPU to setup, begin, and retrieve the results of ADC conversion operations. For higher performance, it is often required (depending on the application) to put the CPU into the lower power mode...
Page 424 MAX32600 User’s Guide Analog Front End 8.3 ADC Some of the parameters that can be set for ADC conversion operations in PMU or CPU control modes include: • Sample rate control • Oversampling and decimation ﬁlter operations – The burst sample rate is always the maximum sample rate –...
Page 425 8.3.4.1 Peripheral Clock Conﬁguration The MAX32600 supports multiple clock source options to operate the ADC. To use the ADC, it is necessary to select the source for the ADC Peripheral Clock, select the clock divisor, and disable clock gating to generate the ADC Peripheral Clock (PCLK).
Page 426 MAX32600 User’s Guide Analog Front End 8.3 ADC adc_source_select ADC Input Clock Source PLL 8MHz Output External High Frequency Clock 24MHz Relaxation Oscillator Peripheral Clock Mode (Clock Divisor) The ADC peripheral clock, PCLK, is generated based on the ADC input clock source as set in the previous section. The ADC Peripheral Clock directly clocks the ADC internally and is based on a divisor of the ADC Input Clock Source Selection.
Page 427 8.3.4.3.1 Signal Conditioning The MAX32600 ADC features two signal conditioning modes: bipolar and unipolar mode. Bipolar mode must be used if the negative input could exceed the positive input. Unipolar mode can be used if the positive input will always be greater than the negative input. When using bipolar mode, it is optimal to enable differential input mode;...
Page 428: Input Multiplexer
MAX32600 User’s Guide Analog Front End 8.3 ADC to +V /2. Setting the ADC_CTRL0.range ﬁeld to 1 indicates a range of -V to +V Note There are instances, however, when the signal-to-noise ratio (SNR) can be improved by using differential input mode with unipolar signal conditioning.
Page 429 MAX32600 User’s Guide Analog Front End 8.3 ADC mux_ch_sel mux_diff ADC+ ADC- Notes 0x00 AIN0 Single-ended input SSADC 0x01 AIN1 Single-ended input AGND 0x02 AIN2 Single-ended input AGND 0x03 AIN3 Single-ended input AGND 0x04 AIN4 Single-ended input AGND 0x05 AIN5...
Page 430 MAX32600 User’s Guide Analog Front End 8.3 ADC mux_ch_sel mux_diff ADC+ ADC- Notes 0x31 output buffer REFDAC AGND REFDAC 0x32 output buffer REFADC AGND REFDAC 0x00 AIN0 AIN8 Differential Input 0x01 AIN1 AIN9 Use differential AIN1/9 for external V -Resistor temperature sen-...
Page 431: Scan Modes
Input Mux Channel Scanning Channels can be scanned at any rate up to the maximum 500kHz sample rate supported by the MAX32600 ADC. In scan mode, a single sample or a burst of samples is taken from each enabled channel in the scan sequence. The input mux and PGA settings are automatically conﬁgured to the parameters needed by the next scan channel in the sequence by the ADC state machine.
Page 432: Interrupts
Out of Range Interrupts The MAX32600 ADC supports an upper and lower set point to generate out of range interrupts if a measured sample goes above or below a conﬁgured threshold. The out of range support simpliﬁes monitoring an input signal for a threshold and allows the CPU to only wake when a set condition occurs.
Page 433 8.3.4.7 Programmable Gain Ampliﬁer The MAX32600 ADC signal chain includes a Programmable Gain Ampliﬁer (PGA) between the Input Mux and the ADC. The PGA takes the outputs from the Input Mux and ampliﬁes it prior to processing by the ADC. This improves the signal-to-noise ratio of low amplitude signals. Bypassing the PGA is supported and results in higher sample rates for the ADC.
Page 434 MAX32600 User’s Guide Analog Front End 8.3 ADC The Track portion of the acquisition window is controlled via the ADC_TG_CTRL0.pga_trk_cnt register ﬁeld, and the Hold portion is controlled by the ADC_TG_CT RL1.pga_acq_cnt ﬁeld. Refer to Sample Rate Calculation for details.
Page 435: Sample Rate Calculation
8.3.4.8 Sample Rate Calculation The MAX32600 ADC supports two primary measurement modes for the ADC: Low Power Measurement Mode and High Speed Measurement Mode. Low Power Measurement Mode uses signiﬁcantly less power than High Speed Measurement Mode by putting the ADC and PGA, if enabled, in a sleep state between samples.
Page 436 MAX32600 User’s Guide Analog Front End 8.3 ADC The maximum sample rate achievable that allows the ADC to sleep between samples with the PGA enabled is 180ksps and 333ksps with the PGA in bypass. High Speed Measurement Mode leaves the ADC powered during the entire measurement window, enabling sample rates as high as 500ksps.
Page 437 MAX32600 User’s Guide Analog Front End 8.3 ADC Parameter Description / Register Location Actual ADC Sample Frequency ADC Peripheral Clock Frequency (usually 8MHz) PCLK pga_trk_cnt Value in register ADC_TG_CTRL0.pga_trk_cnt adc_acq_cnt Value in register ADC_TG_CTRL1.adc_acq_cnt pga_acq_cnt Value in register ADC_TG_CTRL1.pga_acq_cnt adc_brst_cnt Value in register ADC_TG_CTRL1.adc_brst_cnt...
Page 438 MAX32600 User’s Guide Analog Front End 8.3 ADC Burst/Decimation Mode PGA Bypass target brst PCLK brst PCLK PGA Enabled target PCLK scan scan PCLK Scan Mode PGA Bypass target PCLK scan scan PCLK PGA Enabled target PCLK scan scan PCLK...
Page 439 MAX32600 User’s Guide Analog Front End 8.3 ADC 8.3.4.8.2 Sample Rate Calculation: Low Power Measurement Mode • 180ksps maximum sample rate with PGA enabled • 333ksps maximum sample rate with PGA bypassed • ADC_TG_CTRL1.adc_sleep_cnt is the register ﬁeld used to set the target sample rate and controls the number of PCLKs that the ADC will sleep after each measurement •...
Page 440: Start The Measurement
MAX32600 User’s Guide Analog Front End 8.3 ADC Scan Mode PGA Bypass target sl p 1 pga scan PCLK 1 pga sl p scan PCLK PGA Enabled target sl p scan PCLK sl p scan PCLK Scan Mode with Burst/Decimation...
Page 441 MAX32600 User’s Guide Analog Front End 8.3 ADC Address Register Word Len Description 0x40054000 ADC_CTRL0 ADC Control Register 0 0x40054004 ADC_PGA_CTRL PGA Control Register 0x40054008 ADC_TG_CTRL0 ADC Timing Generator Control 0 0x4005400C ADC_TG_CTRL1 ADC Timing Generator Control 1 0x40054010 ADC_LIMIT...
Page 442 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description adc_tst_en Reserved Field (Do Not Modify) This ﬁeld should not be modiﬁed by the user. For proper operation, this ﬁeld must be left at its default value.
Page 443 MAX32600 User’s Guide Analog Front End 8.3 ADC • 0: Unipolar operation from 0 to Vref • 1: Bipolar operation as determined by adc_range ADC_CTRL0.adc_dv_reg Field Bits Default Access Description adc_dv_reg Reserved Field - Do Not Modify This ﬁeld should not be modiﬁed by the user. For proper operation, this ﬁeld must be left at its default value.
Page 444 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description adc_smp_ext Reserved Field - Do Not Modify This ﬁeld should not be modiﬁed by the user. For proper operation, this ﬁeld must be left at its default value.
Page 445 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description cpu_adc_strt CPU Start for ADC Data Collection Active high start signal; used to start the ADC’s programmed data collection sequence. Write to 1 to start data collection.
Page 446 MAX32600 User’s Guide Analog Front End 8.3 ADC • 0: FIFO is not empty • 1: FIFO is empty ADC_CTRL0.avg_mode Field Bits Default Access Description avg_mode 21:20 ADC Decimation Filter Mode • 00b: Bypass (decimation ﬁlter not used) • 01b: Output average only •...
Page 447 MAX32600 User’s Guide Analog Front End 8.3 ADC • 000b: Full rate AdcClk=ClkIn (PLL generates 8MHz) • 001b: Half Rate AdcClk=ClkIn / 2 • 010b: Third Rate AdcClk=ClkIn / 3 (default) • 011b: Quarter Rate AdcClk=ClkIn / 4 • 100b: AdcClk = ClkIn / 6 •...
Page 448 MAX32600 User’s Guide Analog Front End 8.3 ADC 8.3.5.1.2 ADC_PGA_CTRL ADC_PGA_CTRL.gain Field Bits Default Access Description gain PGA Gain Setting • 00b: Gain x1 • 01b: Gain x2 • 10b: Gain x4 • 11b: Gain x8 ADC_PGA_CTRL.cpu_pga_rst_clk_en Field Bits Default...
Page 449 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description cpu_pga_trk_dly Reserved Field - Do Not Modify This ﬁeld should not be modiﬁed by the user. For proper operation, this ﬁeld must be left at its default value.
Page 450 MAX32600 User’s Guide Analog Front End 8.3 ADC ADC_PGA_CTRL.mux_sw_ain Field Bits Default Access Description mux_sw_ain Reserved Field - Do Not Modify This ﬁeld should not be modiﬁed by the user. For proper operation, this ﬁeld must be left at its default value.
Page 451 MAX32600 User’s Guide Analog Front End 8.3 ADC ADC_PGA_CTRL.mux_ch_sel Field Bits Default Access Description mux_ch_sel 29:24 000000b ADC Input Mux Select Positive Input to ADC (decoded in concert wtih mux_diff) For mux_ch_sel=0..15, mux_diff=0 (single ended mode): • 00..15: Vp=AIN[0..15], Vn=VSSADC For mux_ch_sel=0..15, mux_diff=1 (differential mode):...
Page 452 MAX32600 User’s Guide Analog Front End 8.3 ADC • 32: Vp=MUXA, Vn=VSSADC • 33: Vp=OUTA, Vn=VSSADC • 34: Vp=MUXB, Vn=VSSADC • 35: Vp=OUTB, Vn=VSSADC • 36: Vp=MUXC, Vn=VSSADC • 37: Vp=OUTC, Vn=VSSADC • 38: Vp=MUXD, Vn=VSSADC • 39: Vp=OUTD, Vn=VSSADC •...
Page 453 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description Used to control the total number of samples collected when adc_mode is x000b or x001b. If the decimation ﬁlter is enabled, this ﬁeld still controls the total number of samples (data points) collected, but the sample data output to the ADC FIFO will be a smaller number of samples, depending on the current decimation ﬁlter setting.
Page 454 MAX32600 User’s Guide Analog Front End 8.3 ADC • 010b: 4 samples • 011b: 8 samples • 100b: 16 samples • 101b: 32 samples • 110b: 64 samples • 111b: 128 samples ADC_TG_CTRL1.adc_acq_cnt Field Bits Default Access Description adc_acq_cnt 15:12...
Page 455 MAX32600 User’s Guide Analog Front End 8.3 ADC Lower limit used by out of range detector. Determines when the out_rng_if and lo_rng_if interrupt ﬂags are set. ADC_LIMIT.hi_limit Field Bits Default Access Description hi_limit 31:16 7FFFh ADC Sample Upper Limit Upper limit used by out of range detector. Determines when the out_rng_if and hi_rng_if interrupt ﬂags are set.
Page 456 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description hi_rng ADC Sample Above High Limit Interrupt Flag Set by hardware when a collected ADC sample is out of range on the high side (above the programmable hi_limit threshold).
Page 457 MAX32600 User’s Guide Analog Front End 8.3 ADC Set by hardware when an ADC FIFO underﬂow condition occurs (empty FIFO is read). Write 1 to clear. ADC_INTR.ﬁfo_of Field Bits Default Access Description ﬁfo_of ADC FIFO Overﬂow Interrupt Flag Set by hardware when an ADC FIFO overﬂow condition occurs (full FIFO is written).
Page 458 MAX32600 User’s Guide Analog Front End 8.3 ADC ADC_INTR.ﬁfo_qf Field Bits Default Access Description ﬁfo_qf ADC FIFO One-Quarter Full Interrupt Flag Set by hardware when the ADC FIFO is more than one-quarter full. Write 1 to clear. ADC_INTR.spst_sw0_ctrl Field Bits...
Page 459 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description spst_sw2_ctrl SPST2 Switch Control Mode • 0: Switch is controlled by AFE_CTRL3.close_spst2. • 1: Switch is controlled by pulse train output PT10. ADC_INTR.spst_sw3_ctrl Field Bits Default Access...
Page 460 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description out_rng_en ADC Sample Out of Range Interrupt Enable • 0: Interrupt is disabled • 1: Interrupt is enabled ADC_INTR.hi_rng_en Field Bits Default Access Description hi_rng_en ADC Sample Above High Limit Interrupt Enable •...
Page 461 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description done_en ADC Data Collection Complete Interrupt Enable • 0: Interrupt is disabled • 1: Interrupt is enabled ADC_INTR.ﬁfo_uf_en Field Bits Default Access Description ﬁfo_uf_en ADC FIFO Underﬂow Interrupt Enable •...
Page 462 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description ﬁfo_tf_en ADC FIFO Three-Quarters Full Interrupt Enable • 0: Interrupt is disabled • 1: Interrupt is enabled ADC_INTR.ﬁfo_hf_en Field Bits Default Access Description ﬁfo_hf_en ADC FIFO Half Full Interrupt Enable •...
Page 463 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description data_reg 15:0 0000h ADC Current Valid Data Sample Direct read of the ADC output data; cleared on cpu_adc_strt and registered during adc_dv. 8.3.5.1.8 ADCCFG_CTRL1 ADCCFG_CTRL1.scan_cnt Field Bits...
Page 464 MAX32600 User’s Guide Analog Front End 8.3 ADC • bits 3:0 - mux_ch_sel setting • bits 5:4 - pga_gain setting • bit 6 - mux_diff setting • bit 7 - Not used, should be set to 0 Note ADC unipolar/bipolar mode and bipolar range must be the same for all channels.
Page 465 MAX32600 User’s Guide Analog Front End 8.3 ADC • bit 7 - Not used, should be set to 0 Note ADC unipolar/bipolar mode and bipolar range must be the same for all channels. ADCCFG_SCAN1.adc_scan3 Field Bits Default Access Description adc_scan3 31:24 ADC Scan Conﬁguration - Channel 3...
Page 466 MAX32600 User’s Guide Analog Front End 8.3 ADC ADCCFG_SCAN2.adc_scan5 Field Bits Default Access Description adc_scan5 15:8 ADC Scan Conﬁguration - Channel 5 • bits 3:0 - mux_ch_sel setting • bits 5:4 - pga_gain setting • bit 6 - mux_diff setting •...
Page 467 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description adc_scan7 31:24 ADC Scan Conﬁguration - Channel 7 • bits 3:0 - mux_ch_sel setting • bits 5:4 - pga_gain setting • bit 6 - mux_diff setting • bit 7 - Not used, should be set to 0 Note ADC unipolar/bipolar mode and bipolar range must be the same for all channels.
Page 468 MAX32600 User’s Guide Analog Front End 8.3 ADC Field Bits Default Access Description ro_cal_load Load Initial RO Calibration Trim 1: Loads trm_init into factory calibration closed loop. ADCCFG_RO_CAL0.trm_mu Field Bits Default Access Description trm_mu 19:8 000h Auto Calibration Loop Gain ADCCFG_RO_CAL0.ro_trm...
Page 469 8.4.1 DAC Overview The MAX32600 features four voltage output DACs, two with 12-bit resolution and two with 8-bit resolution. Each DAC can be set independently to generate either a static output voltage or to generate a series of preloaded sample outputs at a speciﬁed sample rate.
Page 470: Rev.1.3 April
8.4.2 DAC Interface Each DAC instance on the MAX32600 is conﬁgured using a set of control and conﬁguration registers mapped to the APB bus. When generating a series of output voltage samples, the high-speed DAC FIFOs are used to provide the sample values for the DAC; these are loaded over the AHB bus by either the CPU or by the Rev.1.3 April 2015...
Page 471 MAX32600 User’s Guide Analog Front End 8.4 DAC PMU. Burst transfers can be used to quickly load the DAC FIFOs with sample data stored in RAM or constant ﬂash space. Figure 8.8: DAC Interface Diagram 8.4.3 DAC Operation Note The following sections will refer to “the DAC”. It is understood that this means any one of the four DACs available on the device.
Page 472 Where these settings represent choices between multiple options, these apply to all four of the DAC instances. Powering Up the Analog Front End As with other operations/functions involving the analog front end on the MAX32600, the AFE must be globally powered up before any of the DACs can be used. This is performed by setting PWRMAN_PWR_RST_CTRL.afe_powered...
Page 473 MAX32600 User’s Guide Analog Front End 8.4 DAC DAC Clock Enable / Clock Scaling Each DAC instance runs from an independently scalable clock that is generated from the currently selected system clock source. Because this clock is used by the APB and AHB interface logic as well as the internal DAC state machine logic, the clock must be enabled before attempting to access any of the DAC APB registers or the AHB DAC FIFO.
Page 474: Reduced Power Level Modes For 12-Bit Dac Instances
MAX32600 User’s Guide Analog Front End 8.4 DAC DAC Power-Up and Enable Sequence Once the DAC module clock has been enabled, the DAC instance itself may be powered on and enabled for use by the application ﬁrmware. In order to do this, the...
Page 475 MAX32600 User’s Guide Analog Front End 8.4 DAC Note If Interpolation Mode is enabled (as discussed below), this parameter applies to the output rate of values after interpolation. The Rate Count parameter is set by writing to the DACn_RATE.rate_cnt ﬁeld; the actual value of the Rate Count parameter is equal to (rate_cnt + 2).
Page 476 MAX32600 User’s Guide Analog Front End 8.4 DAC Increasing interpolation “smooths” the output waveform (as shown below, where the interpolation rate increases from left to right, but the additional data points inserted may not be exactly accurate for the desired waveform. For the highest quality of the generated output waveform, the maximum number of true waveform data points should be loaded via the DAC FIFO.
Page 477 MAX32600 User’s Guide Analog Front End 8.4 DAC Setting the DAC Start Mode The ﬁnal parameter that must be written to conﬁgure the DAC instance is the DAC Start Mode. This setting determines when the DAC will begin generating output voltage data according to the speciﬁed settings, based on the voltage samples loaded in the DAC FIFO.
Page 478 MAX32600 User’s Guide Analog Front End 8.4 DAC Sample Count Mode When using this DAC operating mode, the total number of sample code values that the DAC should pull from the FIFO to generate the pattern must be speciﬁed. This sample count must be written to DACn_RATE.sample_cnt. Once the DAC has pulled this number of samples from the FIFO, the DAC will halt and hold the last output voltage.
Page 479: Correcting For Distortion At High Output Frequency
MAX32600 User’s Guide Analog Front End 8.4 DAC The DAC outputs are high impedance. Each DAC has a built-in load that is correct on the positive output at full power and is correct on the negative output at all power levels. It is possible to add an external load in some conﬁgurations, but this is not advised.
Page 480: Module Dac Registers
MAX32600 User’s Guide Analog Front End 8.4 DAC 8.4.5 Registers (DAC) 8.4.5.1 Module DAC Registers Address Register Word Len Description 0x40050000 DAC0_CTRL0 DAC Control Register 0 0x40050004 DAC0_RATE DAC Output Rate/Sample Control 0x40050008 DAC0_CTRL1_INT DAC Control Register 1, Interrupt Flags and Enable/Disable...
Page 481 MAX32600 User’s Guide Analog Front End 8.4 DAC Field Bits Default Access Description Sets the programmable threshold for detection of the Almost Empty condition for the DAC output FIFO. The default value for this setting is 4. The allowable range is from 0 to 15, with 8 being a typically used value.
Page 482 MAX32600 User’s Guide Analog Front End 8.4 DAC Field Bits Default Access Description interp_mode 10:8 DAC Output Interpolation Mode • 000b: Disabled • 001b: 2:1 Interpolation • 010b: 4:1 Interpolation • 011b: 8:1 Interpolation • 1xxb: Reserved DACn_CTRL0.ﬁfo_af_cnt Field Bits...
Page 483 MAX32600 User’s Guide Analog Front End 8.4 DAC • 11b: Reserved DACn_CTRL0.cpu_start Field Bits Default Access Description cpu_start DAC Output CPU Start Manual control for DAC output sequence start, controlled by CPU (that is, written by application ﬁrmware) as opposed to a start condition generated by the ADC or an automatic start triggered by data being loaded into the DAC FIFO.
Page 484 MAX32600 User’s Guide Analog Front End 8.4 DAC The entire power_mode ﬁeld (which consists of bits 30, 27, and 26) sets the power mode for the DAC instance as: • 001b: PwrLvl0 Mode (48 uA) • 011b: PwrLvl1 Mode (130 uA) •...
Page 485 MAX32600 User’s Guide Analog Front End 8.4 DAC DACn_CTRL0.reset Field Bits Default Access Description reset DAC Reset Write to 1 to reset the DAC. Automatically cleared to 0 by hardware when operation has completed. 8.4.5.1.2 DACn_RATE DACn_RATE.rate_cnt Field Bits Default...
Page 486 MAX32600 User’s Guide Analog Front End 8.4 DAC Field Bits Default Access Description out_done_if DAC Output Done Interrupt Flag Write 1 to clear. Written to 1 by hardware when DAC output has completed. DACn_CTRL1_INT.underﬂow_if Field Bits Default Access Description underﬂow_if FIFO Underﬂow Interrupt Flag...
Page 487 MAX32600 User’s Guide Analog Front End 8.4 DAC Read-only. 0: FIFO is not in underﬂow condition 1: FIFO is in underﬂow condition DACn_CTRL1_INT.out_done_ie Field Bits Default Access Description out_done_ie DAC Output Done Interrupt Enable Write 1 to enable interrupt source; 0 to disable.
Page 488 LED conﬁgurations will be used. Each particular LED conﬁguration requires speciﬁc organization of components both within and external to the chip. The simplest LED conﬁgurations require one DAC, one op amp, and one I/O pair on the MAX32600. External components—an LED and a sense resistor (Rs)—are also needed, necessitating the use of additional...
Page 489: Led Driver Details
MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.1.1 LED Driver Details • Eight switches (CSAx CSBx) • Up to two control control loops (one illustrated) • Register and digital generator control of IO_cfg • Digital Generators: – Pulse Train –...
Page 490: Led Conﬁguration
MAX32600 User’s Guide Analog Front End 8.5 LED Figure 8.10: LED Block Diagram 8.5.2 LED Conﬁguration Note In each block diagram below, integrated components are rendered in black and external components are depicted in grey boxes. Also, in conﬁgura- tions with more than one LED, current is not necessarily run simultaneously; internal switches are used to manage current.
Page 491: Basic Led Conﬁguration
DAC. The op amp drives the gate of an NMOS switch transistor in the I/O; the I/O regulates digitally whether the switch in the I/O is connected to the op amp or turned off. The MAX32600 I/O switch can drive up to 100mA. This conﬁguration requires two GPIO pins to implement the switch transistor and activate the LED.
Page 492: Multiple Led Conﬁguration
MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.2.2 Multiple LED Conﬁguration Figure 8.12: Multiple LED Conﬁguration The multiple LED conﬁguration is an extension of the Basic LED Conﬁguration. The mechanics of the conﬁguration remains the same; the only adaptation is multiple diodes on the control loop.
Page 493: H-Bridge Led Conﬁguration
The H-bridge LED conﬁguration uses a pair of source/sink LED I/O to drive a pair of diodes connected back-to-back. This design only requires two pins on the LED package and cable; however, it necessitates the use of a pullup device within the MAX32600. The onboard pullup devices on the MAX32600 can usefully source 25mA from diodes with forward voltages as high as 2.5V.
Page 494: Independent Loop H-Bridge Led Conﬁguration
When the digital controls switch the loop open then closed again, undesirable loop behavior may occur and must be controlled. Further, only one diode can be activated at any one time. These circumstances may necessitate the use of more than one op amp. Here, the MAX32600 can provide two independent control loop paths as a possible solution to these problems.
Page 495: Integrated Feedback Loops Led Conﬁguration
Figure 8.15: Integrated Feedback Loops LED Conﬁguration The MAX32600 features the ability to integrate the feedback loop. This conﬁguration enables time-division multiplexing of diodes with separate sense resistors and requires only one uncommitted switch for overshoot control instead of two. These control loops can time multiplex the DAC and op amp resources—creating multiple instances of the above Basic LED Conﬁguration...
Page 496: Internal Feedback With Common Sense Resistor Led Conﬁguration
MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.2.6 Internal Feedback with Common Sense Resistor LED Conﬁguration Figure 8.16: Internal Feedback with Common Sense Resistor LED Conﬁguration An alternate feedback conﬁguration is to feed diodes on a control loop to a common sense resistor. Here, only one source pad needs to be connected back to the op amp—the one pad is common to every diode connected in the control loop.
Page 497: Double H-Bridge Led Conﬁguration
MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.2.7 Double H-bridge LED Conﬁguration Figure 8.17: Double H-bridge LED Conﬁguration The H-bridge application can be doubled: one terminal of a back-to-back diode pair shares a terminal of the second diode pair. This extension of the H-bridge LED Conﬁguration...
Page 498: Multiple High Voltage Led Control Conﬁguration
This conﬁguration provides for the high drive voltage requirements inherent to some LEDs. LEDs, particularly blue and green, often have high forward voltages; even red LEDs have high drive voltage requirements at high currents due to internal resistances. In these cases, the MAX32600 3.6V maximum voltage becomes a limiting factor.
Page 499 MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.2.9 3x3 LED Matrix Conﬁguration Figure 8.19: 3x3 LED Matrix Conﬁguration In LED matrix conﬁguration, LED capable I/Os are used at the bottom of the matrix structure, and simple I/Os for the top sides. For proper operation, the top and bottom I/Os must be switched in a time multiplexed manner.
Page 500: Register Conﬁgurations
• Set up the pulse trains or timers 8.5.3.1 Current Mode Request Note for a detailed mapping of MAX32600 multiplexed function locations. Functional priority distinction is included in the mapping. Pin Layout Mapping of Logical Current Ports (7mm x 7mm Compact Package)
Page 501 MAX32600 User’s Guide Analog Front End 8.5 LED Note The mapping of the WLP Package is equivalent to the 7mm x 7mm Compact package; however, all LED drivers are 2X on the WLP (replace drive ﬁgures in above table). Mapping of Logical Current Ports (12mm x 12mm Standard Package)
Page 502 MAX32600 User’s Guide Analog Front End 8.5 LED GPIO_OUT_VAL IOMAN_CRNT_MODE DRAIN SOURCE LOGIC 1 LOGIC 0 LOGIC 1 LOGIC 0 0x03 N-gate=OpAmp C/D Feedback channel=Source 0x04 0x05 Reserved 0x06 N-gate=GND N-gate=OpAmp C/D N-gate=GND 0x07 P-gate=On P-gate=Off Feedback channel=Source N-gate=OpAmp A/B...
Page 503: Control Loop Setup
MAX32600 User’s Guide Analog Front End 8.5 LED For the compact packages (7mm x 7mm and WLP packages) switching between sink and source is more simple. Set the IOMAN_CRNT_MODE to 0x7 and use GPIO_OUT_VAL_Pn to switch between sink and source. Since...
Page 504: Fault Detection Setup
MAX32600 User’s Guide Analog Front End 8.5 LED 8.5.5 Fault Detection Setup Fault detection is accomplished by monitoring the source pad of the sink, which is connected to the analog matrix, during operation by a pair of comparators, each with a reference level set by a DAC.
Page 505: Design Current
It is recommended that parts with a high duty cycle and multiple I/O connected in parallel do not exceed an average current of 200mA. Transient currents will be limited by the switch Ids to a point that is safe for the MAX32600. Transient currents may damage external components or possibly have safety implications—it is Rev.1.3 April 2015...
Page 506 MAX32600 User’s Guide Analog Front End 8.5 LED required that transient behavior be controlled within acceptable limits. There are several methods for ensuring that the output current it not out of bounds: • Use of the comparators for fault detection is recommended; this enables the detection of short-circuit or over-current conditions.
Page 507 Pulse Train Engine 9 Pulse Train Engine 9.1 Pulse Train Engine (PTE) Overview The MAX32600 includes 13 separate pulse train generators. Eight of these (PT0 - PT7) can be used to generate output sequences on General-Purpose I/O pins. The remaining ﬁve are routed to the Analog Front End (AFE). For details on how the pulse trains (PT8 - PT11 and PT15) are used by the AFE, refer to Overview.
Page 508: Enabling And Disabling Pulse Train Outputs 9.4.1 Master Enable/Disable
MAX32600 User’s Guide Pulse Train Engine 9.4 Enabling and Disabling Pulse Train Outputs pulse_train_clk_scale (4-bit value) PT Peripheral Clock Rate (PTE PCLK 1.5MHz 750kHz 375kHz 187.5kHz 93.75kHz 10-15 24MHz 9.4 Enabling and Disabling Pulse Train Outputs 9.4.1 Master Enable/Disable The Pulse Train Engine supports the ability to start all conﬁgured and stop all active pulse trains simultaneously. This enables master control of all pulse train outputs by ﬁrmware.
Page 509 MAX32600 User’s Guide Pulse Train Engine 9.5 Pulse Train Engine Modes Table 9.1: Pulse Train Output Options PT10 PT11 PT15 Rev.1.3 April 2015 Maxim Integrated Page 491...
Page 510: Square Wave Mode
MAX32600 User’s Guide Pulse Train Engine 9.6 Synchronization 9.5.2 Square Wave Mode In Square Wave mode, the PTE simply toggles the output state when the rate counter, as deﬁned in the PTn_RATE_LENGTH.rate_control ﬁeld, expires. In Square Wave mode, if the rate is set to a value of 1, the Pulse Train Peripheral clock rate is output directly.
Page 511 MAX32600 User’s Guide Pulse Train Engine 9.7 Registers (PT) Address Register Word Len Description 0x40001000 PTG_CTRL Global Pulse Train Enable/Disable 0x40001004 PTG_RESYNC Global Resync (All Pulse Trains) Control 0x40001008 PT0_RATE_LENGTH Pulse Train Conﬁguration 0x4000100C PT0_TRAIN Pulse Train Output Pattern 0x40001010 PT1_RATE_LENGTH Pulse Train 1 Conﬁguration...
Page 512: Ptg_Ctrl
MAX32600 User’s Guide Pulse Train Engine 9.7 Registers (PT) Address Register Word Len Description 0x40001060 PT11_RATE_LENGTH Pulse Train 11 Conﬁguration 0x40001064 PT11_TRAIN Pulse Train 11 Output Pattern 0x40001068 PT12_RATE_LENGTH Pulse Train 12 Conﬁguration 0x4000106C PT12_TRAIN Pulse Train 12 Output Pattern...
Page 513 MAX32600 User’s Guide Pulse Train Engine 9.7 Registers (PT) Field Bits Default Access Description Resync control for PT1 Resync control for PT2 Resync control for PT3 Resync control for PT4 Resync control for PT5 Resync control for PT6 Resync control for PT7 Write 1: Resets the rate counter and pulse train pointer for this pulse train.
Page 514: Ptn_Rate_Length
MAX32600 User’s Guide Pulse Train Engine 9.7 Registers (PT) 9.7.1.3 PTn_RATE_LENGTH PTn_RATE_LENGTH.rate_control Field Bits Default Access Description rate_control 26:0 26’b0 Pulse Train Enable/Rate Control Deﬁnes rate at which the pulse train output changes state. If this ﬁeld is zero, the pulse train is disabled; otherwise, the output changes to the next state (toggling for square wave mode, or advancing to the next pulse train pattern bit for pulse train output mode) at a rate equal to (Pulse Train Module Clock / Pulse Train Rate).
Page 515 MAX32600 User’s Guide Pulse Train Engine 9.7 Registers (PT) In square wave mode, this register has no effect. In pulse train mode, this register contains the repeating pattern that will be shifted out as the pulse train output stream (starting with LSB) Rev.1.3 April 2015...
Page 516: System Clock
All external clock sources must meet the electrical/timing requirements given in the datasheet. All functional units in the MAX32600 are synchronized to the system clock that can be generated from either an external oscillator or internal ring oscillator or with Rev.1.3 April 2015...
Page 517 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock an external crystal/resonator. A block diagram of the MAX32600 clock subsystem is provided below. Figure 10.1: Clock System Block Diagram Rev.1.3 April 2015 Maxim Integrated...
Page 518: Khz Crystal Oscillator
Time Clock (RTC) module. An external clock source may also be used by the MAX32600 in place of a 32kHz crystal. For this conﬁguration, the external clock source is connected to the part on the 32KIN pin. 10.1.1.3 48MHz USB Clock PLL...
Page 519: Rev.1.3 April
10.1.2 System Clock Conﬁguration The MAX32600 clock subsystem provides a high degree of ﬂexibility to optimize an embedded system implementation. The user has options to trade-off external components depending on the circuitry required by the desired application(s). A block diagram of the MAX32600 clock subsystem is provided in the ﬁgure...
Page 520: External Clock
Crystal speciﬁcations, operating temperature, operating voltage, and parasitic capacitance must be considered when designing or choosing the external oscillator. The MAX32600 is designed to operate at a maximum frequency of 24MHz; however, the oscillator is not limited to this frequency as the PLL 2X, 4X, and 6X modes are regularly used to achieve higher frequencies.
Page 521 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock capacitance value. Figure 10.2: On-Chip High-Frequency Crystal Oscillator Rev.1.3 April 2015 Maxim Integrated Page 503...
Page 522: External 32Khz Clock (Crystal Or Resonator)
The MAX32600 oscillator drives a standard 32.768kHz watch crystal. These crystals are very high-impedance and do not require a high-current oscillator circuit. The MAX32600 oscillator is speciﬁcally designed to operate with these crystals and is compatible with their high impedance and limited power handling capability.
Page 523: Phase Lock Loop
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Firmware Control of the External 32kHz Clock The 32kHz RTC clock is enabled with the PWRSEQ_REG0.pwr_rtcen_run bit for LP2: PMU and LP3: RUN PWRSEQ_REG0.pwr_rtcen_slp bit for...
Page 524 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Figure 10.3: Phase Lock Loop Functional Diagram Firmware Control of the Phase Lock Loop The PLL is disabled by default. However, the PLL is needed to generate the required 48MHz clock for USB operation. The PLL can multiply an 8MHz, 12MHz, or 24MHz clock up to the required 48MHz.
Page 525: Relaxation Oscillator
System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock 10.1.3.5 Relaxation Oscillator The MAX32600 can source its main system clock directly from an internal 24MHz 1% Relaxation Oscillator. The system Relaxation Oscillator is controlled via CLKMAN_CLK_CONFIG, PWRSEQ_REG0, ADCCFG_RO_CAL0, and ADCCFG_RO_CAL1 registers.
Page 526: Crypto Clock Relaxation Oscillator
= (FinalTrim[8:2] Disable RTC (if not needed) PWRSEQ_REG0.pwr_rtcen_run 10.1.3.6 Crypto Clock Relaxation Oscillator The MAX32600 sources the Trust Protection Unit (TPU) from an internal 44MHz Relaxation Oscillator (note: this is separate from the 24MHz 1% Relaxation Oscillator). A one-time factory trim is utilized to achieve the accuracy over process, temperature, and supply voltage. The Crypto Relaxation Oscillator is controlled Rev.1.3 April 2015...
Page 527: Adc Clock Source Conﬁguration
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_CONFIG register. CLKMAN_CLK_CONFIG ﬁeld Function crypto_enable Enable the Crypto Relaxation Oscillator crypto_reset_n Active low holds the Crypto Relaxation Oscillator in reset state crypto_stability_count Crypto Relaxation Oscillator stability select 10.1.4 ADC Clock Source Conﬁguration...
Page 528: Registers (Clkman)
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Control of the ADC Clock Source Conﬁguration Clock conﬁguration involves a trade-off with power and performance. The lowest jitter 8MHz clock with the best duty cycle provides the smallest degradation from aperture jitter.
Page 529 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Address Register Word Len Description 0x40090448 CLKMAN_CLK_CTRL_2_PT Control Settings for CLK2 - Pulse Train Module Clock 0x4009044C CLKMAN_CLK_CTRL_3_SPI0 Control Settings for CLK3 - SPI0 Master Clock...
Page 530 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Address Register Word Len Description 0x40090548 CLKMAN_CLK_GATE_CTRL2 Dynamic Clock Gating Control Register 2 10.1.5.1.1 CLKMAN_CLK_CONFIG CLKMAN_CLK_CONFIG.hfx_enable Field Bits Default Access Description hfx_enable no effect HFX Enable •...
Page 531 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock This register ﬁeld must be left at its default value for proper operation. CLKMAN_CLK_CONFIG.hfx_gm_adjust Field Bits Default Access Description hfx_gm_adjust no effect HFX GM Adjust GM Adjust for Crystal Oscillator Amp CLKMAN_CLK_CONFIG.hfx_dc_control...
Page 532 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Active low reset for PLL CLKMAN_CLK_CONFIG.pll_input_select Field Bits Default Access Description pll_input_select no effect PLL Input Select Selects input clock source for PLL • 0: Selects HFX output as PLL input clock source •...
Page 533 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0: Disabled • 1: Enable the 8MHz output of the PLL CLKMAN_CLK_CONFIG.pll_bypass Field Bits Default Access Description pll_bypass no effect Reserved Field; Do Not Modify This register ﬁeld must be left at its default value for proper operation.
Page 534 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description crypto_enable Crypto Oscillator Enable Enable crypto oscillator (power up) CLKMAN_CLK_CONFIG.crypto_reset_n Field Bits Default Access Description crypto_reset_n Crypto Oscillator ResetN Active low - 0 holds crypto oscillator in reset state CLKMAN_CLK_CONFIG.crypto_stability_count...
Page 535 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock 10.1.5.1.2 CLKMAN_CLK_CTRL CLKMAN_CLK_CTRL.system_source_select Field Bits Default Access Description system_source_select no effect System Clock Source Select • 00b: 24MHz Relaxation Osc output (divided by 8) • 01b: 24MHz Relaxation Osc output (undivided) •...
Page 536 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_CTRL.adc_gate_n Field Bits Default Access Description adc_gate_n ADC Clock GateN Gates off ADC clock when asserted to 0 (active low) CLKMAN_CLK_CTRL.adc_source_select Field Bits Default Access...
Page 537 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_CTRL.watchdog0_gate_n Field Bits Default Access Description watchdog0_gate_n no effect Watchdog 0 Clock GateN Gates off watchdog clock when asserted (active low) CLKMAN_CLK_CTRL.watchdog0_source_select Field Bits Default...
Page 538 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_CTRL.watchdog1_source_select Field Bits Default Access Description watchdog1_source_select 22:21 no effect Watchdog 1 Clock Source Select Selects the source for the watchdog external clock: • 00b: Scaled Sys Clock Source (as set by SYS_CLK_CTRL_12) •...
Page 539 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Set to 1 by hardware when the 24MHz relaxation oscillator is considered stable. CLKMAN_INTFL.pll_stable Field Bits Default Access Description pll_stable PLL Output Stable Int Flag Write 1 to clear.
Page 540 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description pll_stable PLL Output Stable Int Enable 0:Interrupt disabled; 1:Interrupt enabled CLKMAN_INTEN.crypto_stable Field Bits Default Access Description crypto_stable Crypto Oscillator Stable Int Enable 0:Interrupt disabled;...
Page 541 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Write to 1 to start a new trim calculation; self clearing. CLKMAN_TRIM_CALC.trim_calc_completed Field Bits Default Access Description trim_calc_completed Trim Calculation Completed Status bit; this bit is set to 1 by hardware when a trim calculation is completed, and is cleared to 0 by hardware when a new trim calculation is started.
Page 542 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description i2c_1ms_timer_en I2C 1ms Timer Enable 1:Enables the general purpose timer used by the I2C blocks for determining timeout events. 10.1.5.1.7 CLKMAN_CLK_CTRL_0_SYSTEM CLKMAN_CLK_CTRL_0_SYSTEM.sys_clk_scale...
Page 543 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description gpio_clk_scale 0000b Control Settings for CLK1 - GPIO Module Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) •...
Page 544 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0011b: CLK = (System Clock Source / 4) • 0100b: CLK = (System Clock Source / 8) • 0101b: CLK = (System Clock Source / 16) •...
Page 545 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 1001b: CLK = (System Clock Source / 256) • other: CLK = (System Clock Source / 1) This clock is disabled by default following reset.
Page 546 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description spi2_clk_scale 0000b Control Settings for CLK5 - SPI2 Master Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) •...
Page 547 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0011b: CLK = (System Clock Source / 4) • 0100b: CLK = (System Clock Source / 8) • 0101b: CLK = (System Clock Source / 16) •...
Page 548 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 1001b: CLK = (System Clock Source / 256) • other: CLK = (System Clock Source / 1) This clock is disabled by default following reset.
Page 549 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description puf_clk_scale 0000b Control Settings for CLK9 - PUF Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) •...
Page 550 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0011b: CLK = (System Clock Source / 4) • 0100b: CLK = (System Clock Source / 8) • 0101b: CLK = (System Clock Source / 16) •...
Page 551 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 1000b: CLK = (System Clock Source / 128) • 1001b: CLK = (System Clock Source / 256) • other: CLK = (System Clock Source / 1) This clock is disabled by default following reset.
Page 552 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock 10.1.5.1.20 CLKMAN_CLK_CTRL_13_RTC_INT_SYNC CLKMAN_CLK_CTRL_13_RTC_INT_SYNC.rtc_clk_scale Field Bits Default Access Description rtc_clk_scale 0000b Control Settings for CLK13 - RTC Interrupt Sync Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) •...
Page 553 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) • 0010b: CLK = (System Clock Source / 2) • 0011b: CLK = (System Clock Source / 4) •...
Page 554 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0101b: CLK = (System Clock Source / 16) • 0110b: CLK = (System Clock Source / 32) • 0111b: CLK = (System Clock Source / 64) •...
Page 555 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock 10.1.5.1.24 CLKMAN_CLK_CTRL_17_DAC3 CLKMAN_CLK_CTRL_17_DAC3.dac3_clk_scale Field Bits Default Access Description dac3_clk_scale 0000b Control Settings for CLK17 - 8-bit DAC 1 Clock • 0000b: CLK is Disabled • 0001b: CLK = (System Clock Source / 1) •...
Page 556 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0000b: CLK is Disabled • 0001b: CLK = (Crypto Clock Source / 1) • 0010b: CLK = (Crypto Clock Source / 2) • 0011b: CLK = (Crypto Clock Source / 4) •...
Page 557 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 0110b: CLK = (Crypto Clock Source / 32) • 0111b: CLK = (Crypto Clock Source / 64) • 1000b: CLK = (Crypto Clock Source / 128) •...
Page 558 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock 10.1.5.1.28 CLKMAN_CLK_GATE_CTRL0 CLKMAN_CLK_GATE_CTRL0.cm3_clk_gater Field Bits Default Access Description cm3_clk_gater Clock Gating Control for CM3 CPU Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 559 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description icache_clk_gater Clock Gating Control for Instruction Cache Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 560 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On CLKMAN_CLK_GATE_CTRL0.apb_bridge_clk_gater Field Bits Default Access Description apb_bridge_clk_gater 11:10 Clock Gating Control for AHB-to-APB Bridge Dynamic clock gating control.
Page 561 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_GATE_CTRL0.uart0_clk_gater Field Bits Default Access Description uart0_clk_gater 15:14 Clock Gating Control for UART 0 Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 562 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On CLKMAN_CLK_GATE_CTRL0.timer1_clk_gater Field Bits Default Access Description timer1_clk_gater...
Page 563 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_GATE_CTRL0.timer3_clk_gater Field Bits Default Access Description timer3_clk_gater 25:24 Clock Gating Control for Timer Module 3 Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 564 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On CLKMAN_CLK_GATE_CTRL0.usb_clk_gater Field Bits Default Access Description usb_clk_gater...
Page 565 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 1xb: Clock On CLKMAN_CLK_GATE_CTRL1.adc_clk_gater Field Bits Default Access Description adc_clk_gater Clock Gating Control for ADC Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 566 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Field Bits Default Access Description dac12_1_clk_gater Clock Gating Control for DAC1 Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 567 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On CLKMAN_CLK_GATE_CTRL1.pmu_clk_gater Field Bits Default Access Description pmu_clk_gater 13:12 Clock Gating Control for DMA (PMU) Dynamic clock gating control.
Page 568 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_GATE_CTRL1.gpio_clk_gater Field Bits Default Access Description gpio_clk_gater 17:16 Clock Gating Control for GPIO Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 569 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On CLKMAN_CLK_GATE_CTRL1.spi1_clk_gater Field Bits Default Access Description spi1_clk_gater...
Page 570 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock CLKMAN_CLK_GATE_CTRL1.i2cm0_clk_gater Field Bits Default Access Description i2cm0_clk_gater 27:26 Clock Gating Control for I2C Master 0 Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled •...
Page 571 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock Dynamic clock gating control. • 00b: Clock Off • 01b: Dynamic Clock Gating Enabled • 1xb: Clock On 10.1.5.1.30 CLKMAN_CLK_GATE_CTRL2 CLKMAN_CLK_GATE_CTRL2.crc_clk_gater Field Bits Default Access...
Page 572: Watchdog Timers
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers • 1xb: Clock On CLKMAN_CLK_GATE_CTRL2.ssbmux_clk_gater Field Bits Default Access Description ssbmux_clk_gater Clock Gating Control for SSB Mux Dynamic clock gating control. • 00b: Clock Off •...
Page 573: Watchdog Timers Overview
10.2.2 Clock Source Selection and Gating The MAX32600 supports multiple clock source selection options. This enables the use of both WWDTs to ensure that in the event a speciﬁc clock source fails, the second WWDT will still catch the failure.
Page 574: Watchdog Timer Conﬁguration
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers 10.2.3 Watchdog Timer Conﬁguration Each watchdog timer supports independent settings for three independent time delay periods: 1. Pre-window period: minimum time interval required between watchdog timer clear events 2.
Page 575: Enabling And Disabling The Watchdog Timer Counter
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers 10.2.3.2 Enabling and Disabling the Watchdog Timer Counter The application software must set the WDTn_CTRL.en_timer to a 1 to start the Watchdog Timer. The Watchdog Timer is free-running; the following procedure must be followed when enabling to prevent an unintended reset during the enable process.
Page 576 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers Address Register Word Len Description 0x40021000 WDT0_CTRL WDT0 - Watchdog Timer Control Register 0x40021004 WDT0_CLEAR WDT0 - Watchdog Clear Register (Feed Dog) 0x40021008 WDT0_FLAGS WDT0 - Watchdog Interrupt and Reset Flags...
Page 577 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers • Eh: 2 • Fh: 2 WDTn_CTRL.rst_period Field Bits Default Access Description rst_period Period from WDT Clear to Reset Flag Set Reset Period - the time period from the beginning of the watchdog timer count (WDT is cleared to zero by being enabled or when the watchdog timer is cleared by writing to the CLEAR register) until the Watchdog Reset Flag is set.
Page 578 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers WDTn_CTRL.en_clock Field Bits Default Access Description en_clock Watchdog Clock Gate Watchdog Clock Gate. This enables the WDC clock which allows ﬂags to be set/cleared (not the same as WDEN which allows the timer to increment).
Page 579 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b WDT0 - Watchdog Clear Register (Feed Dog) Write 0xA5,0x5A sequence to clear watchdog timer (feed watchdog) Reads always return zero.
Page 580 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.2 Watchdog Timers Write 1 to clear this ﬂag to 0. Set to 1 by hardware when the watchdog timer reaches the end of the reset period without being cleared.
Page 581: Real Time Clock (Rtc)
10.3.1 Real Time Clock Overview The Real Time Clock (RTC) on the MAX32600 is designed to operate largely independent of other the digital and analog functions on the device. The RTC has its own clock that runs off a 4kHz clock derived from the external crystal 32kHz oscillator output. While one of the main power supplies (V...
Page 582: Rtc Resets
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) • Dedicated low-frequency, low-power 4kHz clock source (derived from 32kHz external crystal oscillator) • Continued operation when main portion of system is powered off –...
Page 583: Rtc Conﬁguration
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Although the 4kHz clock domain interrupt ﬂag can be set while the main system is powered off (e.g., if a time of day alarm is matched), main power must be present in order for the system to wake up and service the interrupt.
Page 584 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) 4. The RTC can is now be enabled by setting RTCTMR_CTRL.enable bit to 1. Turning on the RTC Block and 32kHz Crystal Oscillator By default, the RTC block and the 32kHz crystal oscillator are disabled following an RTC POR event.
Page 585 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) • The RTCTMR_CTRL.pending status bit will change to 1 to indicate that clock domain synchronization is pending; the bit will change back to 0 once the synchronization has completed.
Page 586: Registers (Rtctmr)
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) The PRESCALE==0h setting represents the minimum prescale reload value, which means that the RTC timer will be incremented each 4kHz clock period. This is also reﬂected in the value in the ’4kHz ticks in LSB’...
Page 587 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Address Register Word Len Description 0x40090A2C RTCTMR_TRIM_VALUE RTC Timer Trim Adjustment Interval 10.3.5.1.1 RTCTMR_CTRL RTCTMR_CTRL.enable Field Bits Default Access Description enable 0 (RTC POR only) RTC Timer Enable •...
Page 588 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) • 1: One or more RTC transactions are pending as indicated by the associated _active ﬂags in this register. RTCTMR_CTRL.use_async_ﬂags Field Bits Default...
Page 589 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Field Bits Default Access Description en_active tmr_en_active Reads 1 when the associated transaction is pending RTCTMR_CTRL.osc_goto_low_active Field Bits Default Access Description osc_goto_low_active osc_goto_low_active Reads 1 when the associated transaction is pending RTCTMR_CTRL.osc_frce_sm_en_active...
Page 590 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Field Bits Default Access Description set_active timer_set_active This sync transaction with the 4kHz clock domain occurs when a new timer value is written to the RTCTMR_TIMER register.
Page 591 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) RTCTMR_CTRL.prescale_update_active Field Bits Default Access Description prescale_update_active prescale_update_active Reads 1 when the associated transaction is pending RTCTMR_CTRL.cmpr1_clr_active Field Bits Default Access Description cmpr1_clr_active...
Page 592 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) 10.3.5.1.3 RTCTMR_COMP Default Access Description FFFFFFFFh (RTC POR only) RTC Time of Day Alarm [0..1] Compare Register The compare value that causes the COMP{0,1}_FLAG to go active high when COMP{0,1}[31:0] matches TIMER_A[31:0].
Page 593 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) RTCTMR_FLAGS.comp1 Field Bits Default Access Description comp1 0 (RTC POR only) RTC Compare 1 Interrupt Status Write 1 to clear. Set to 1 by hardware when a match occurs between the RTC timer and the Compare Value 0.
Page 594 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Field Bits Default Access Description trim 0 (RTC POR only) RTC Trim Interrupt Status Write 1 to clear. Set to 1 by hardware when a trim adjustment event occurs.
Page 595 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) RTCTMR_FLAGS.overﬂow_ﬂag_a Field Bits Default Access Description overﬂow_ﬂag_a 0 (RTC POR only) RTC Overﬂow 4kHz Flag Original event detection ﬂag from 4kHz domain. RTCTMR_FLAGS.trim_ﬂag_a...
Page 596 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) • 0: Disabled. • 1: The RTC Time of Day Alarm 0 Interrupt is enabled. RTCTMR_INTEN.comp1 Field Bits Default Access Description comp1 RTC Time of Day Alarm (Compare 1) Interrupt Enable •...
Page 597 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) RTCTMR_INTEN.trim Field Bits Default Access Description trim RTC Trim Adjust Event Interrupt Enable • 0: Disabled. • 1: The RTC Trim Adjust Event Interrupt is enabled.
Page 598 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) • 1010b: 3FFh (4Hz) • 1011b: 7FFh (2Hz) • 1100b: FFFh (1Hz) 10.3.5.1.9 RTCTMR_PRESCALE_MASK RTCTMR_PRESCALE_MASK.comp_mask Field Bits Default Access Description comp_mask 0000b (RTC POR only)
Page 599 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) 10.3.5.1.10 RTCTMR_TRIM_CTRL RTCTMR_TRIM_CTRL.trim_enable_r Field Bits Default Access Description trim_enable_r 0 (RTC POR only) Enable RTL Trim of RTC Timer • 0: Trim disabled •...
Page 600 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Any changes must occur with RTC timer disabled. 10.3.5.1.11 RTCTMR_TRIM_VALUE RTCTMR_TRIM_VALUE.trim_value Field Bits Default Access Description trim_value 17:0 18’b0 (RTC POR only) Trim PPM Value Only bits 17:8 are writeable;...
Page 601 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) Address Register Word Len Description 0x40090A78 RTCCFG_DSEN_CTRL Dynamic Tamper Sensor Control 0x40090A7C RTCCFG_OSC_CTRL RTC Oscillator Control 10.3.6.1.1 RTCCFG_NANO_CNTR RTCCFG_NANO_CNTR.nanoring_counter Field Bits Default Access...
Page 602 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC) RTCCFG_CLK_CTRL.nano_en Field Bits Default Access Description nano_en nano_en 1:Enable clk_nano_gated that goes to the rtc_nano_cntr_0. The source of this clock is clk_nano. 10.3.6.1.3 RTCCFG_DSEN_CTRL RTCCFG_DSEN_CTRL.dsen_disable...
Page 603 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Field Bits Default Access Description osc_disable_r 0 (RTC POR) osc_disable_r • 0: No effect (default) • 1: If (osc_disable_sel == 1), the RTC oscillator is held in reset.
Page 604: Timers/Counters Overview
10.4.1 Timers/Counters Overview The MAX32600 supports four 32-bit reloadable timers that can be used for timing, event counting, and generation of pulse-width modulated (PWM) signals. The clock timer input (for all modes) is the ARM Cortex-M3 System Clock. Featured is a programmable prescaler with prescale values from 1 to 4096 from the system clock.
Page 605 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Figure 10.6: Timer Block Diagram Rev.1.3 April 2015 Maxim Integrated Page 587...
Page 606: Bit Mode Timer Operation
Note Pin Conﬁgurations, Packages, and Special Function Multiplexing for a detailed mapping of MAX32600 multiplexed function locations and priority distinction. Timer modules interface with the GPIO pins, which claim the lowest functional priority (see GPIO Pins and Peripheral Mode Functions for further information).
Page 607: Continuous Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters disabled and stops counting. Also, if the Timer Output function is enabled in the GPIO, the Timer output pin will change state for one clock cycle and then return to the polarity value (the TMRn_CTRL.polarity...
Page 608: Counter Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • Set the prescale value, TMRn_CTRL.prescale 2. If using the Timer Output function, set the initial output level (High or Low) via TMRn_CTRL.polarity ﬁeld 3. Write to the Timer Count register to set the starting count value TMRn_COUNT32 •...
Page 609: Pwm Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • Select either the rising edge or falling edge of the Timer Input signal for the count, TMRn_CTRL.polarity (NOTE: This also sets the initial logic level (High or Low) for the Timer Output function;...
Page 610 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • Select 32-bit timer mode, TMRn_CTRL.tmr2x16 = "0" • Conﬁgure the timer for PWM Mode, TMRn_CTRL.mode = “011” • Set the prescale value, TMRn_CTRL.prescale • Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output function, TMRn_CTRL.polarity.
Page 611: Capture Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters 10.4.2.5 Capture Mode In Capture Mode, the current timer count value is recorded when the desired external Timer Input transition occurs. The Capture Mode count value is stored in the Timer PWM register.
Page 612: Gated Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • Disable the timer, TMRn_CTRL.enable0 = “0” • Select 32-bit timer mode, TMRn_CTRL.tmr2x16 = "0" • Conﬁgure the timer for Compare Mode, TMRn_CTRL.mode = “101” • Set the prescale value, TMRn_CTRL.prescale...
Page 613: Capture/Compare Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • This only affects the ﬁrst pass in Gated Mode • Counting always begins at 0x0000_0001 after the ﬁrst timer reset 3. Write to the Timer Compare register, TMRn_TERM_CNT32, to set the Compare value 4.
Page 614: Bit Mode Timer Operation
10.4.3 16 bit Mode Timer Operation Each of the four 32-bit timers on the MAX32600 can be split into 2 x 16-bit timers, for a total of up to eight 16-bit timers. Conﬁguration and operation of 16-bit mode is very similar to the 32-bit modes of operation, but when conﬁgured as two 16-bit timers, only One-Shot and Continuous Modes of operation are supported.
Page 615: One-Shot Mode
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters 10.4.3.1 One-Shot Mode In One-Shot mode, the timer counts from the start count value stored in the Timer register up to the 16-bit Compare value stored in the Timer Compare register. Upon reaching the Compare value, the timer generates an interrupt, and the count value in the Timer register is reset to 0x0001;...
Page 616: Registers (Tmr)
MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters 2. Write to the Timer register to set the starting count value, TMRn_COUNT16_0.value or TMRn_COUNT16_1.value, depending on which one of the 16-bit timers is being used •...
Page 617 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Address Register Word Len Description 0x40013000 TMR1_CTRL Timer Control Register 0x40013004 TMR1_COUNT32 [32 bit] Current Count Value 0x40013008 TMR1_TERM_CNT32 [32 bit] Terminal Count Setting 0x4001300C TMR1_PWM_CAP32...
Page 618 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Address Register Word Len Description 0x40015010 TMR3_COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x40015014 TMR3_TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x40015018...
Page 619 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • 0: One Shot Mode • 1: Continuous Mode Bit 1 controls operating mode for 16-bit timer 1: • 0: One Shot Mode • 1: Continuous Mode Bit 2 is not used in dual 16-bit timer mode.
Page 620 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters • 0001b: Divide by 2 • 0010b: Divide by 4 • 0011b: Divide by 8 • 0100b: Divide by 16 • 0101b: Divide by 32 • 0110b: Divide by 64 •...
Page 621 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Field Bits Default Access Description enable0 Enable 32-bit timer / 16-bit timer 0 For single 32-bit timer mode (tmr2x16=0): • 0: 32-bit timer is disabled • 1: 32-bit timer is enabled For dual 16-bit timer mode (tmr2x16=1): •...
Page 622 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters In 32-bit timer mode (tmr2x16=0), this register holds the current count value for the 32-bit timer. In 16-bit timer mode (tmr2x16=1), this register cannot be accessed and all reads from this location will return zero.
Page 623 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters 10.4.4.1.6 TMRn_TERM_CNT16_0 TMRn_TERM_CNT16_0.term_count Field Bits Default Access Description term_count 15:0 0000h Terminal Count Setting In 16-bit timer mode (tmr2x16=1), this register holds the terminal count setting for 16-bit timer 1.
Page 624 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters 10.4.4.1.9 TMRn_INTFL TMRn_INTFL.timer0 Field Bits Default Access Description timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 Hardware sets this ﬂag to 1 when the timer reaches the terminal count or a capture value is obtained or when the input pad is deasserted in Gated mode.
Page 625 MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.4 Timers/Counters Field Bits Default Access Description timer1 Interrupt Enable for 16-bit Timer 1 Enable/disable setting to allow a timer interrupt to be triggered when the corresponding interrupt ﬂag is set.
Page 626: Registers (Aes)
Trust Protection Unit (TPU) The TPU on the MAX32600 provides support for cryptographic data security and automatic response to external attacks against the device. Although the MAA and the AES engine are covered in separate sections, these are also considered to be part of the TPU as well.
Page 627: Rev.1.3 April
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine Address Register Word Len Description 0x4010A008 AES_MEM_INP2 AES Input 2 0x4010A00C AES_MEM_INP3 AES Input 3 (most signiﬁcant 32 bits) 0x4010A010 AES_MEM_KEY0 AES Key 0 (least signiﬁcant 32 bits) 0x4010A014...
Page 628 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine 11.1.1.1.1 AES_CTRL AES_CTRL.start Field Bits Default Access Description start AES Start/Busy Writing this bit to 1 initiates an AES operation. This bit is cleared from 1 to 0 by hardware when an AES operation has completed.
Page 629 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine AES_CTRL.key_size Field Bits Default Access Description key_size AES Key Size Select This ﬁeld can only be written when the AES engine is idle (AES Busy == 0). Size of key to use for AES operation.
Page 630 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine If AES Interrupt Enable is set, this bit will trigger an AES Interrupt when set to 1. 11.1.1.1.2 AES_ERASE_ALL Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b...
Page 631 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine Default Access Description 11.1.1.1.7 AES_MEM_INP3 Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Input 3 (most signiﬁcant 32 bits) 11.1.1.1.8 AES_MEM_KEY Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b...
Page 632 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Key 2 11.1.1.1.12 AES_MEM_KEY3 Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Key 3 11.1.1.1.13 AES_MEM_KEY4...
Page 633 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Key 7 (most signiﬁcant 32 bits) 11.1.1.1.17 AES_MEM_OUT Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Output Data (128 bits) 11.1.1.1.18 AES_MEM_OUT0...
Page 634 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.1 AES Cryptographic Engine Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b AES Output 3 (most signiﬁcant 32 bits) 11.1.1.1.22 AES_MEM_EXPKEY Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b...
Page 635: Modular Arithmetic Accelerator (Maa)
AES Expanded Key Data 7 11.2 Modular Arithmetic Accelerator (MAA) Registers (MAA)} The Modular Arithmetic Accelerator (MAA) module on the MAX32600 is used to perform rapid calculation of modular arithmetic operations (with operands up to Rev.1.3 April 2015 Maxim Integrated Page 617...
Page 636: Registers (Maa)
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) 512-bits in length). These modular math operations can then be used as the basis for cryptographic operations such as RSA public/private key cryptography. Operations supported by the MAA (up to 512-bits): •...
Page 637 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) 11.2.1.1.1 MAA_CTRL MAA_CTRL.start Field Bits Default Access Description start Start MAA Calculation • Write to 1: Start a MAA calculation. • Write to 0: Reset MAA and stop operation.
Page 638 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) Field Bits Default Access Description ocalc Optimized Calculation Control • 0: No optimization is used • 1: Skip unneeded multiply operations MAA_CTRL.if_done Field Bits Default Access Description if_done Interrupt Flag - Calculation Done Write to 0 to clear.
Page 639 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) Write to 0 to clear. This bit is set to 1 by hardware when an MAA operation is terminated by an error condition. MAA_CTRL.ofs_a Field Bits Default Access...
Page 640 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) MAA_CTRL.ofs_exp Field Bits Default Access Description ofs_exp 13:12 Exponent Memory Offset Select These bits select the starting position of the ’E’ parameter within its logical segment. (Same as "A" Memory Offset Select) MAA_CTRL.ofs_mod...
Page 641 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) • 0101b: xA8A0..xA8BF, xA880..xA89F • 0110b: xA8C0..xA8FF • 0111b: xA8E0..xA8FF, xA8C0..xA8DF • 1000b: xA900..xA93F • 1001b: xA920..xA93F, xA900..xA91F • other: reserved For (MAA Word Size) from 257..512 • 000xb: xA800..xA83F •...
Page 642 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) Field Bits Default Access Description seg_res 27:24 0000b Result Memory Segment Select These bits select the memory segment for the results output. (Same as select settings for Operand A) MAA_CTRL.seg_tmp...
Page 643 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.2 Modular Arithmetic Accelerator (MAA) 11.2.1.1.3 MAA_MEM_SEG0 Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b [64 bytes] MAA Memory Segment 11.2.1.1.4 MAA_MEM_SEG1 Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b [64 bytes] MAA Memory Segment 11.2.1.1.5 MAA_MEM_SEG2...
Page 644: Registers (Tpu)
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.3 Registers (TPU) 11.2.1.1.8 MAA_MEM_SEG5 Default Access Description 0000 0000 0000 0000 0000 0000 0000 0000b [64 bytes] MAA Memory Segment 11.3 Registers (TPU) 11.3.1 Module TPU Registers Address Register Word Len Description...
Page 645: Tpu_Tsr_Status
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.3 Registers (TPU) 11.3.1.2 TPU_PRNG_RND_NUM Default Access Description 00000000h PRNG Random Number Output [15:0] Random number output from PRNG. 11.3.1.3 TPU_TSR_STATUS Default Access Description 0000 0000 0000 0000 0000 000s 0000 000sb Dynamic Tamper Sensor Status [bit 0] Set to 1 by hardware when the dynamic tamper sensor is triggered.
Page 646 MAX32600 User’s Guide Trust Protection Unit (TPU) 11.3 Registers (TPU) Field Bits Default Access Description out_freq 000b Dynamic Sensor Output Frequency Sets the tamper sensor output frequency based on a divide down of the module clock, as follows: • 000b: divide by 4 (max error threshold is 3) •...
Page 647: Tpu_Tsr_Ctrl1
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.3 Registers (TPU) • 101b: divide by 32 • 110b: divide by 64 • 111b: Reserved TPU_TSR_CTRL0.rtc_tx_busy Field Bits Default Access Description rtc_tx_busy RTC Domain Tx Busy • 0: No RTC transfer in progress •...
Page 648: Tpu_Tsr_Sks0
MAX32600 User’s Guide Trust Protection Unit (TPU) 11.3 Registers (TPU) 11.3.1.6 TPU_TSR_SKS0 Default Access Description TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) 11.3.1.7 TPU_TSR_SKS1 Default Access Description TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) 11.3.1.8 TPU_TSR_SKS2...
Page 649: Crc16 And Crc32 Hardware Accelerator 12.1 Overview
12.3 CRC Operation The MAX32600 CRC hardware peripheral calculates a 16-bit or 32-bit CRC value based on a 32-bit data value combined with an initial seed value (default is 0xFFFF for 16-bit CRC and 0xFFFFFFFF for 32-bit CRC calculations). For data values that are not 32-bits wide, the upper bytes must be padded with zeroes to the next 32-bit boundary.
Page 650: Crc-16-Ccitt Example Calculation
MAX32600 User’s Guide CRC16 and CRC32 Hardware Accelerator 12.4 CRC-16-CCITT Example Calculation 12.4 CRC-16-CCITT Example Calculation 1. If an initial seed value other than 0xFFFF is desired, write initial seed value into CRC_SEED16. 2. Set CRC_RESEED.crc16 to apply new initial seed value.
Page 651: Crc_Reseed
MAX32600 User’s Guide CRC16 and CRC32 Hardware Accelerator 12.6 Registers (CRC) Address Register Word Len Description 0x40010000 CRC_RESEED CRC-16/CRC-32 Reseed Controls 0x40010004 CRC_SEED16 Reseed Value for CRC-16 Calculations 0x40010008 CRC_SEED32 Reseed Value for CRC-32 Calculations 0x4010B000 CRC_DATA_VALUE16 Write Next CRC-16 Data Value / Read CRC-16 Result Value...
Page 652: Crc_Seed32
MAX32600 User’s Guide CRC16 and CRC32 Hardware Accelerator 12.6 Registers (CRC) Default Access Description 00000000h Reseed Value for CRC-16 Calculations This register contains the value that will be used when a CRC16 reseed operation is triggered. 12.6.1.3 CRC_SEED32 Default Access...
Page 653: Rev.1.3 April
13 LCD Controller 13.1 LCD Overview The standard package of the MAX32600 incorporates an LCD controller with a boost regulator that interfaces with common low-voltage displays ( 3.3V or below, AC coupled). An external LCD module is not needed: by incorporating the LCD controller into the microcontroller itself, the design only requires an external LCD glass for full LCD functionality.
Page 654: Lcd Operation
MAX32600 User’s Guide LCD Controller 13.2 LCD Operation Note LCD functionality is not available on the Compact or WLP pin layouts. See Pin Conﬁgurations, Packages, and Special Function Multiplexing further information. Figure 13.1: LCD Controller Block Diagram 13.2 LCD Operation Four display modes are supported by the LCD controller: •...
Page 655: Lcd Conﬁguration
LCD power and clock registers must be conﬁgured ﬁrst to ensure proper device conﬁguration. If a clock is off to the block, writes to the APB registers may not be recognized. 13.3.1 LCD Clock The MAX32600 LCD controller uses the device’s on-board 32kHz RTC as a source clock. Comprehensive conﬁguration details for the RTC can be found in the Real Time Clock (RTC) section.
Page 656: Lcd Internal Register Adjust
LCD ground register from 0-72kOhms. This should only be written when LCD operation is suspended (i.e., OPM=0). The MAX32600 LCD output frequency is set with the LCD_LCRA.frame_rate register.
Page 657 MAX32600 User’s Guide LCD Controller 13.3 LCD Conﬁguration FRAME FRAME FRAME FRAME LCD Frame Frequencies (1/3 duty) with f = 512 Hz FRAME FRAME FRAME FRAME Note For most LCD, the best drive performance Frame Frequency, f , is between 30 Hz and 128 Hz (these instances are in bold in the above tables).
Page 658: Lcd Port Conﬁguration
MAX32600 User’s Guide LCD Controller 13.3 LCD Conﬁguration • 10b: 1/3 duty (1/3 bias, 3X segment mux) • 11b: 1/4 duty (1/3 bias, 4X segment mux) The following table outlines the bit addresses for the LCD Internal Register Adjust registers. Writes to this register can only occur when OPM=0.
Page 659: Lcd Memory Conﬁguration
LCD glass mapping to LCD_LCDATA LCD_LCADDR values are dependent on LCD glass type and its pin interconnection to the MAX32600 LCD segment pins. Further information can be found in the relevant application note. LCD_LCDATA / LCD_LCADDR Register Details Rev.1.3 April 2015...
Page 660: Registers (Lcd)
MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) Register Operation Read/Write Details LCD_LCADDR.addr_sel LCD Memory Index 0 = reset LCD_LCADDR 15:5 Reserved always write 0 value LCD_LCDATA LCD Glass Segment Mapping See application note showing LCD_LCDATA bit mapping for all four display mux modes 13.4 Registers (LCD)
Page 661 MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) LCD_LCFG.operating_mode Field Bits Default Access Description operating_mode OPM - LCD Operating Mode 0: LCD controller off; 1: LCD controller on LCD_LCFG.stop_mode_en Field Bits Default Access Description stop_mode_en SMO - Stop Mode Operation Enable Set to 1 to enable operation in stop mode LCD_LCFG.autopage_en...
Page 662: Lcd_Lcra
MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) Should be set to 00b. LCD_LCFG.datahold Field Bits Default Access Description datahold Datahold Set to 1 to hold the current data being displayed on the LCD COM/SEG regardless of changes to display memory; setting to 0 will allow display memory changes to propagate to the LCD glass.
Page 663 MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) LCD_LCRA.. Field Bits Default Access Description Reserved Should be set to 00b LCD_LCRA.frame_rate Field Bits Default Access Description frame_rate 12:8 00000b FRM Frame Rate Selects frame rate / frequency for LCD output.
Page 664: Lcd_Lpcf
MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) 13.4.1.3 LCD_LPCF LCD_LPCF.none Field Bits Default Access Description 31:0 32’0b LCD Port Conﬁguration Register Each bit enables two segments when set to 1. bit 0: enables SEG0+SEG1 bit 1: enables SEG2+SEG3 bit 19: enables SEG38+39 13.4.1.4 LCD_LCADDR...
Page 665: Lcd_Lcdata
MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) 13.4.1.5 LCD_LCDATA LCD_LCDATA.none Field Bits Default Access Description LCD Display Memory Read/Write Reading from or writing to accesses the current location in LCD data memory selected by LCADDR. 13.4.1.6 LCD_LPWRCTRL LCD_LPWRCTRL.powerup Field...
Page 666 MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) LCD_LPWRCTRL.bias_powerup Field Bits Default Access Description bias_powerup lcd_bias_pu LCD_LPWRCTRL.enbg4_lcd Field Bits Default Access Description enbg4_lcd enbg_4_lcd LCD_LPWRCTRL.vsel Field Bits Default Access Description vsel lcd_vsel LCD_LPWRCTRL.pump_up Field Bits Default Access Description pump_up lcd_pump_up Status indicator for LCD charge pump.
Page 667 MAX32600 User’s Guide LCD Controller 13.4 Registers (LCD) Status indicator for LCD charge pump. Rev.1.3 April 2015 Maxim Integrated Page 649...
Page 668: Registers (Flc)
14 Flash Controller and Instruction Cache The ﬂash memory controller on the MAX32600 handles control and timing signals for programming and erase operations on both the main program ﬂash memory array and the ﬂash information block. The ﬂash information block is normally written during production test only, and is not generally intended to be modiﬁed by the user application.
Page 669: Flc_Faddr
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Address Register Word Len Description 0x400F0144 FLC_INTFL1 Interrupt Flags Register 1 0x400F0148 FLC_INTEN1 Interrupt Enable/Disable Register 1 0x400F0150 FLC_DISABLE_XR0 Disable Flash Page Exec/Read Register 0 0x400F0154 FLC_DISABLE_XR1 Disable Flash Page Exec/Read Register 1...
Page 670: Flc_Ctrl
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) The value of this ﬁeld is used to generate a 1 microsecond width pulse from the system clock source. This pulse is used when performing write or erase operations on the ﬂash memory.
Page 671: Rev.1.3 April
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Writing this bit to 1 attempts to start a ﬂash page erase operation (in the main program ﬂash for addresses from 00_0000h-1F_FFFFh). The Flash Erase Code must ﬁrst be written to 55h for this operation to be accepted by the FLC.
Page 672 MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) • 0: Flash writes are not currently enabled. • 1: Flash writes are currently enabled. FLC_CTRL.pending Field Bits Default Access Description pending Flash Controller Status This bit goes to an active high state (1) whenever the ﬂash controller is performing a read, write, or erase operation. Once the operation has completed, the bit will return to 0.
Page 673: Flc_Intr
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) FLC_CTRL.ﬂsh_unlock Field Bits Default Access Description ﬂsh_unlock 31:28 0000b Flash Write/Erase Enable 0010b/2d: Flash write and erase operations are enabled. 14.1.1.4 FLC_INTR FLC_INTR.started_if Field Bits Default Access Description started_if Flash Operation Started Write to zero to clear bit to 0.
Page 674: Flc_Fdata
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Field Bits Default Access Description started_ie Flash Operation Started Interrupt Enable • 0: Interrupt disabled. • 1: Setting the Flash Operation Started bit to 1 will cause the FLC to generate an interrupt.
Page 675: Flc_Status
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) • 0: Original ﬂash access design; xaddr and yaddr are activated the same clock edge as SE • 1: Inserts an additional clock cycle before SE is driven active (safety margin, slows down read accesses) (default) FLC_PERFORM.delay_se_en...
Page 676: Flc_Security
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) • 0: No lockout from this source • 1: The debug lockout is being asserted because the Disable Debug (bit 0) in the FLC_SECURITY register has been set to 1. This is typically done by ﬁrmware as part of a user-deﬁned security scheme.
Page 677: Flc_Bypass
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Field Bits Default Access Description mass_erase_lock 11:8 Mass Erase Lockout This ﬁeld can be set to two values as follows: • 0h: (default) Mass erase of the main ﬂash program area can be performed in the usual manner.
Page 678: Flc_User_Option
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Field Bits Default Access Description superwipe_erase Superwipe Erase In Progress 1:Operation is in progress. FLC_BYPASS.destruct_bypass_complete Field Bits Default Access Description destruct_bypass_complete Destructive Security Bypass Erase Complete 1:Operation has completed.
Page 679: Flc_Ctrl2
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) • Write 16’h7502 to this FLC_USER_OPTION[15:0] register. • Wait for write to ﬂash to complete. • The code will be saved into the INFO block array of the ﬂash.
Page 680: Flc_Intfl1
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) This active high signal causes the FAIL signal to AHB_slave to be ignored. (At the moment, the bus is held off until the FLC state machine is ﬁnished with current task so ignorning FAIL is ok.)
Page 681: Flc_Inten1
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) 14.1.1.13 FLC_INTEN1 FLC_INTEN1.sram_addr_wrapped Field Bits Default Access Description sram_addr_wrapped SRAM Address Wrapped Interrupt Enable/Disable FLC_INTEN1.invalid_ﬂash_addr Field Bits Default Access Description invalid_ﬂash_addr Invalid Flash Address Interrupt Enable/ Disable FLC_INTEN1.ﬂash_read_locked Field...
Page 682: Flc_Disable_Xr1
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Default Access Description 00000000h Disable Flash Page Exec/Read Register 0 Each bit in this register controls the execution/read permission for one page of the main ﬂash memory, as follows: •...
Page 683: Flc_Disable_Xr3
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Default Access Description 00000000h Disable Flash Page Exec/Read Register 2 Each bit in this register controls the execution/read permission for one page of the main ﬂash memory, as follows: •...
Page 684: Flc_Disable_We1
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.1 Registers (FLC) Pages 0 through 31. 14.1.1.19 FLC_DISABLE_WE1 Default Access Description 00000000h Disable Flash Page Write/Erase Register 1 Each bit in this register controls the write/erase permission for one page of the main ﬂash memory: •...
Page 685: Registers (Icc)
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.2 Registers (ICC) • 0 - Flash page operates normally. • 1 - Flash page contents may not be modiﬁed using write operations or page erase operations. 14.2 Registers (ICC) 14.2.1 Module ICC Registers...
Page 686: Icc_Mem_Cfg
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.2 Registers (ICC) Field Bits Default Access Description cache_id 15:10 ssssss Cache ID 14.2.1.2 ICC_MEM_CFG ICC_MEM_CFG.cache_size Field Bits Default Access Description cache_size 15:0 Cache size Reported in units of 1024 bytes. ICC_MEM_CFG.main_memory_size...
Page 687: Icc_Invdt_All
MAX32600 User’s Guide Flash Controller and Instruction Cache 14.2 Registers (ICC) ICC_CTRL_STAT.ready Field Bits Default Access Description ready Cache Ready Status • 0: Cache is invalidated/in a reset state • 1: Cache is active and ready for use 14.2.1.4 ICC_INVDT_ALL...

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