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S3F80JB
HARDWARE RESET VALUES
Tables 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data
registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined after a reset.
— A dash ('–') means that the bit is either not used or not mapped (but a 0 is read from the bit position)
Register Name
Timer 0 Counter Register
Timer 0 Data Register
Timer 0 Control Register
Basic Timer Control Register
Clock Control Register
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer (Low Byte)
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register (Read-
Only)
Interrupt Mask Register
System Mode Register
Register Page Pointer
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 2 Interrupt Enable Register
Port 2 Interrupt Pending Register
Port 0 Pull-up Enable Register
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
Table 8-3. Set 1, Bank 0 Register Values After Reset
Mnemonic
T0CNT
T0DATA
T0CON
BTCON
CLKCON
FLAGS
RP0
RP1
Location D8H (SPH) is not mapped.
SPL
IPH
IPL
IRQ
IMR
SYM
PP
P0
P1
P2
P3
P4
P2INT
P2PND
P0PUR
P0CONH
P0CONL
Address
Dec
Hex
7
6
208
D0H
0
0
209
D1H
1
1
210
D2H
0
0
211
D3H
0
0
212
D4H
0
0
213
D5H
x
x
214
D6H
1
1
215
D7H
1
1
217
D9H
x
x
218
DAH
x
x
219
DBH
x
x
220
DCH
0
0
221
DDH
x
x
222
DEH
0
–
223
DFH
0
0
224
E0H
0
0
225
E1H
0
0
226
E2H
0
0
227
E3H
0
–
228
E4H
0
0
229
E5H
0
0
230
E6H
0
0
231
E7H
0
0
232
E8H
0
0
233
E9H
0
0
Bit Values After Reset
5
4
3
2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
−
0
0
0
−
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
x
x
x
x
–
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
1
0
0
0
1
1
0
0
0
0
0
0
0
0
−
−
−
−
x
x
x
x
x
x
0
0
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8-15
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