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LeCroy 4300B Operator's Manual

Camac 16 channel, fast encoding & readout adc fera
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OPERATOR'S MANUAL
MODEL 4300B
CAMAC 16 CHANNEL,
FAST ENCODING &
READOUT ADC (FERA)
Revised
March, 1998
(ECO 1007)
1

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Summary of Contents for LeCroy 4300B

  • Page 1 OPERATOR'S MANUAL MODEL 4300B CAMAC 16 CHANNEL, FAST ENCODING & READOUT ADC (FERA) Revised March, 1998 (ECO 1007)
  • Page 2 Corporate Headquarters 700 Chestnut Ridge Road Chestnut Ridge, NY 10977-6499 Tel: (914) 578-6013 Fax: (914) 578-5984 E-mail: lrs_sales@lecroy.com lrs_support@lecroy.com Copyright© March 1998. LeCroy™ is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publication supersedes all earlier versions.
  • Page 3 CE CONFORMITY CONDITIONS FOR CE CONFORMITY Since this product is a subassembly, it is the responsibility of the end user, acting as the system integrator, to ensure that the overall system is CE compliant. This product was demonstrated to meet CE conformity using a CE compliant crate housed in an EMI/RFI shielded enclosure.
  • Page 4 CAUTION GENERAL Crate power should be turned off during insertion and removal of unit to avoid possible damage caused by momentary misalignment of contacts. See pocket in back of manual for schematics, parts list and additional addenda with any changes to manual.

  • Page 5: Table Of Contents

    TABLE OF CONTENTS General Information Purpose Unpacking and Inspection Warranty Product Assistance Maintenance Agreements Documentation Discrepancies Software Licensing Agreement Service Procedure Front-Panel Diagram 1. Product Description General Specifications Analog Inputs Clear Function External Gate Input (GATE) ADC Pedestals Test Function Pedestal Memory Status Register 1.10 ECL Port Output...
  • Page 6 1.1b Table: Readout Format Model 4300B Block Diagram Charge-to-Time Converter Block Diagram Time-to-Digital Converter Blcok Diagram and Timing 4.0 Appendix ECL Differntial I/O Levels ECL Single-Ended I/O Levels...

  • Page 7: General Information

    LeCroy are covered by the original equipment manufacturers' warranty only. In exercising this warranty, LeCroy will repair or, at its option, replace any product returned to the Customer Service Department or an authorized service facility within the warranty period, provided that the...

  • Page 8: Documentation Discrepancies

    Products requiring maintenance should be returned to the Customer Service Department or authorized service facility. If under warranty, LeCroy will repair or replace the product at no charge. The purchaser is only responsible for the transportation charges arising from return of the goods to the service facility.

  • Page 9: Front-Panel Diagram

    MODEL 4300B FRONT-PANEL Pull Down ON (LED indicator) indicates that pull down and input resistors are Not connected mounted on Command Write Strobe (Sec. 1.11) bus (Sec. 1.15) Readout Request (Sec. 1.11) Clear (Sec. 1.4) Gate (Sec. 1.5) Write Acknowledge (Sec. 1.11)

  • Page 10: Product Description

    3) compacted, i.e., all data < 1 are eliminated (Zero suppression). A system for testing the 16 ADCs is incorporated in the Model 4300B. The test is initiated by the CAMAC command F(25) A(0). This command opens the ADC GATEs and applies, at the input of each one, a charge proportional to the continuous voltage that must be given on the front panel TRV input.

  • Page 11: Analog Inputs

    The Model 4300B will be in one of two states: “ready” or “busy”; depend- ing on the GATE and CLEAR signals sent via either the front-panel or CAMAC command. After a CLEAR, the module is in the “ready” state, i.e., ready to receive a GATE (front-panel or test): the logic and the ADCs are permanently cleared.

  • Page 12: External Gate Input (Gate)

    GATE width. The Model 4300B is adjusted so that the pedestals remain between 1 and 13 pC for GATE durations of 50 ns to 500 ns. For a GATE larger than 500 ns, some ADCs channels may have pedestals below 0 pC.

  • Page 13: Pedestal Memory

    1.8 Pedestal Memory The Model 4300B contains an 8-bit, 16-word Pedestal where each word corresponds to an ADC pedestal (or offset) value to be subtracted during readout (maximum digital value 255). This memory may be loaded or read via CAMAC in random access mode if the module is in the “ready”...
  • Page 14 ECE: ECL port data Compression Enable (W10, R10). ECE = 0: Blocks the suppression of data < 1 for ECL port readout. All 16 ADC values, with or without pedestal subtraction, are sent sequentially to the ECL port. Note: The channel subaddress is not provided and the data cannot be negative (minimum value 0).

  • Page 15: Ecl Port Output

    CAMAC readout. This procedure takes again 2.5 µs as in the case of zero suppression alone. Note: The CAMAC initialization command Z sets the Model 4300B Status Register for the ECL port readout to be followed by CAMAC sequential readout with transmission of the LAM.

  • Page 16: Ecl Port Readout Handshake

    4300B module. The Model 4300B is designed to allow direct connection of WST on WAK and thus obtain data on the ECL port at a frequency of approximately 10 MHz.

  • Page 17: Halt Of Readout On The Ecl Port

    The ECL port outputs and WST are inhibited when REN is released. When several 4300B modules are connected on the same ECL port bus, one must take into account the fact that the REN signal, applied to the first module, must transit through all the others (PASS output connected to REN input of the subsequent module).

  • Page 18: Lam Handling

    Readout Enable/Pass: between REQ output of Model 4301 and REN input of the first Model 4300B to be read. Also, between each Model 4300B, the PASS output is to be connected to the REN input of the next unit; 1 x 2 wire cable (LeCroy type STP-DC/02-00).

  • Page 19: Packaging And Power Requirements

    See Figure 1.4, Model 4301 FERA Driver Block Diagram. 1.16 Packaging and Power Requirements The Model 4300B FERA is packaged in a standard # 1 CAMAC module. It dissipates a total of 30 watts with the following current distribution: < 0.1 A at +24 V <...
  • Page 20 T3: Depends on the ECE status, data values and ECL port readout rate (> 100 nsec per word). ECE = 0 : T3 = 16 (> 100 nsec per word); ECE = 1 and all or part of the data = 0 : T3 = 2 to 17 (>...
  • Page 21 Figure 1.2: ECL PORT TIMING DIAGRAM All times in nsec, typical. Note: This diagram does not define the logic state of the signals: low = OFF and high = ON.
  • Page 22 Figure 1.3: FERA SYSTEM CONNECTIONS...
  • Page 23 Figure 1.4: MODEL 4301 FERA DRIVER BLOCK DIAGRAM...
  • Page 24 Figure 1.5: LOCALIZATION OF REMOVABLE RESISTORS AND VGND-GND JUMPER...
  • Page 25 W16/R16 W15/R15 W14/R14 W13/R13 W12/R12 W11/R11 W10/R10 W9/R9 W8/R8 W1/R/1 Loaded by F(16) A(0) Read by F(0) A(0) Table 1.1.a: STATUS REGISTER FORMAT...
  • Page 26 Without Zero or Zero-and-Overflow Suppression: ECL port readout: EEN=1, ECE=0, OFS=X CAMAC readout: CSR=1, CCE=0, OFS=0 DATA CHANNEL 0 DATA DATA Always 16 words DATA DATA DATA CHANNEL 15 DATA: 8-bit resolution; 0 to 255; overflow=2047 9-bit resolution; 0 to 511; overflow=2047 10-bit resolution;...

  • Page 27: Operating Instructions

    OPERATING INSTRUCTIONS 2.1 GENERAL The circuitry of the LeCroy Model 4300B FERA can be divided into the following eleven basic parts: a. CLEAR and GATE functions b. Charge to time converters (16 channels) c. Test circuit d. Digital interpolators (16 channels) e.

  • Page 28: Charge To Time Converters

    Converters The charge-to-time conversion is provided for each channel by a mono- lithic integrated circuit, LeCroy Model MQT200F. This circuit is based on the dual ramp Wilkinson principle and the integration of the charge by a capacitor. This capacitor is charged during the entire duration of the GATE by the input current and discharged by a constant current after the closing of the GATE.

  • Page 29: Test Circuit

    2.6 Real Time Counters The 16 real time counters are packaged in four hybrid, LeCroy type ls408, circuits. Each circuit contains four independent, 8 bit scalers, each with latches and tri-state out buffers. The following description refers to Figure 2.3.

  • Page 30: Clock Generators

    2.8 Pedestal Memory The pedestal memory consists of two 16 x 4 bit memories. When the Model 4300B is in “ready” state, their select inputs are enabled. They may be loaded by the CAMAC function F(17).S1) or read by F(1)S2. The subaddress A(0 to 15) are applied to the internal address bus via a multiplexer.
  • Page 31 The command bits of the Status Register determine the operation mode of the readout logic. If the module is in the “ready” state, the Status register may be loaded with the function F(16) A(0).S1 or read with F.(0) A(0). The function Z.S2 clears the Status Register, setting the command bits in their true state.

  • Page 32: Ecl Port Readout Circuit

    Note: The valid channel address is also loaded in the Data Memory, but these 4 bits are maintained at zero for ECL port and CAMAC readout without compression or CAMAC random access. If the user wishes to read the channel address in these readout modes, the clear may be suppressed by disconnecting pin 13 of the integrated circuit located in position 17 (74 ALS 874).
  • Page 33 To adjust the FS monostable, apply alternately at approximately 10 kHz, the functions Z (or F(9) A(0), or C) and F(25) A(0) measuring the output width on pin 13 of the G2 integrated circuit (under the FS potentiometer). 4300B FERA Resolution FS Width...
  • Page 34 Figure 2.1: MODEL 4300B BLOCK DIAGRAM...
  • Page 35 Figure 2.2: CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING...
  • Page 36 Figure 2.3: TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING...
  • Page 37 APPENDIX 3.1: ECL DIFFERENTIAL I/O LEVELS...
  • Page 38 APPENDIX 3.2: ECL SINGLE-ENDED I/O LEVELS...

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