Figure 1 Pci5Ip Power Filtering - Dynamic Engineering PCI5IP User Manual

P C I P ow er
F1
L1
IP P ow er
FIGURE 1 PCI5IP POWER FILTERING
With the filter pin on each slot and bulk capacitor each IP is effectively isolated from the
other IP's mounted to the PCI5IP. Additional work was done in layout to minimize the
amount of cross-slot electronic noise. Each of the IP slots is also isolated from the PCI
interface by the power conditioning. The FPGA uses 3.3 and 2.5V power which is
derived from the 5V supply and bussed on mini-planes to the FPGA. The FPGA is
effectively isolated from the IP slots by the regulators and additional filtering.
PCI5IP is well behaved with low noise power provided to each of the slots. PCI5IP is
designed for analog and digital IP applications including data acquisition,
instrumentation, measurement, command and control, telemetry and other industrial
applications.
An 8 bit "dip switch" is provided on the PCI5IP. The switch configuration is readable via
a register. The switch is for user defined purposes. We envision the switch being used
for software configuration control, PCI board identification or test purposes.
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