Ip Module Logic Interface Pin Assignment; Figure 11 Pci5Ip Logic Interface - Dynamic Engineering PCI5IP User Manual

IP Module Logic Interface Pin Assignment

The figure below gives the pin assignments for the IP Module Logic Interface on
the PCI5IP slots A,C,E. Slots B, D have the upper half of the data bus in place of
D15-0 and the upper strobes BS3,2 in place of BS1,0. Also see the User Manual
for your IP board(s) for more information.
GND
CLK
Reset*
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
BS0*
BS1*
–12V
+12V
+5V
GND
NOTE 1: The error signals is defined by the IP Module Logic Interface Specification, but not used by this
Carrier. See the Specification for more information.
NOTE 2: The layout of the pin numbers in this table corresponds to the physical placement of pins on the
IP connector. Thus this table may be used to easily locate the physical pin corresponding to a desired
signal. Pin 1 is marked on the carrier. Please note that the PCI5IP revision 2 and later use SMT
connectors. Older PCI5IP boards have a slightly different mechanical configuration for the connectors.
FIGURE 11
GND
+5V
R/W*
IDSEL*
DMA-reserved
MEMSEL*
DMA-reserved
INTSEL*
DMA-reserved
IOSEL*
reserved
A1
DMA-reserved
A2
n/c
A3
INTREG0*
A4
INTREQ1*
A5
Strobe
A6
Ack*
reserved
GND
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PCI5IP LOGIC INTERFACE
Embedded Solutions