Dynamic Engineering PCI5IP User Manual page 6

with this mode of operation. Please note the non-data bytes should be masked, as
many IPs do not drive the "off byte".
For a long word access to a long word port the 32 bit IP data bus is utilized. Slots B/C
and D/E form 32 bit slots when 32 bit IPs are installed. The access type is automatic
based on the address space used to access the slots. You can use 16 and 32 bit
accesses intermixed without changing your control registers if the IP supports both.
Slot C and E control registers define the access when in 32 bit mode. It may be
necessary to match Slot B clock to slot C and Slot D clock to slot E if your IP uses both.
The address is shifted from long [32] to short [16] by hardware and the byte strobes
used to access the individual bytes or words. If your card has mixed addressing
requirements you may need dual defines to account for the 32 bit and 16 bit addressing.
The PCI bus is defined as little endian and many IPs have their register sets defined to
operate efficiently with a little endian interface. The default settings on the PCI5IP are
"straight through" byte for byte and D15-0 written to address 0x00 before D31-D16
written to address 0x02 when long words are written to 16 bit ports. Please note that
any long word address can be used. The lower data is written to the lower address first,
then the upper data to the upper address. Each slot has a BS and WS control bit to
allow Byte and Word Swapping to be performed to accommodate alternate IP and OS
requirements.
Byte Swapping
16 bit ports
D15-8 ó D7-0
D31-24 óD23-16
32 bit ports
D31-24 => D7-0
D23-16 => D15-8
D15-8 => D23-16
D7-0 => D31-24
Word Swapping will swap D31-16 with D15-0
If byte swapping is enabled and 0x1234 is written to an IP slot, then the IP will see
0x3412. If 0x12345678 is written to a 32-bit port then the IP will see 0x78563412. The
"is written" is defined by the data on the PCI bus. Your software/OS may do its own
conversion before the data gets to the PCI bus.
The byte and word swap controls are separated to allow the conversion to be used for
big-little endian and for register mapping purposes. Each slot has separate controls for
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