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Dynamic Engineering PCI5IP User Manual

Integrated pci to ip module carrier
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DYNAMIC ENGINEERING
150 DuBois St. Suite C, Calif. 95060
831-457-8891
Integrated PCI
Fast Access with integrated PCI
5 IP Positions with IO
8/32 MHz IP operation
8/16/32 bit accesses supported
16/32 bit IP module support
Data Alignment – Byte and Word Swapping
LED's - Power, IP Access, User
Multi-board support
Corresponding Hardware: Revision G
Fab Number 10-2002-0307
Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
PCI5IP
User Manual
ó
IP Module Carrier
Key Features
Watch Dog Timer
Manual Revision G1
FLASH revision G1
ó
IP Bridge

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  • Page 1 DYNAMIC ENGINEERING 150 DuBois St. Suite C, Calif. 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 PCI5IP User Manual Integrated PCI ó IP Module Carrier Key Features ó Fast Access with integrated PCI IP Bridge 5 IP Positions with IO...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION Theory of Operation INSTALLATION ADDRESS MAP PROGRAMMING pci5ip_intreg_base pci5ip_intreg_(a-e) pci5ip_intreg_int pci5ip_intreg_dswitch APPLICATIONS GUIDE Interfacing Engineering Kit IP Module Logic Interface Pin Assignment Construction and Reliability MTBF Thermal Considerations WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION...
  • Page 4 PCI5IP ADDRESS MAP FIGURE 5 PCI5IP CONTROL PORT FIGURE 6 PCI5IP SLOT CONTROL PORT FIGURE 7 PCI5IP 16 BIT BYTE SWAPPING FIGURE 8 PCI5IP 32 BIT BYTE SWAPPING FIGURE 9 PCI5IP INTERRUPT STATUS PORT FIGURE 10 PCI5IP USER SWITCH PORT...

  • Page 5: Product Description

    Rugged, Small, light .. just right for many applications. IndustryPack® Modules require a “carrier” to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. PCI5IP is designed to support PC computer based solutions. Other supported formats include PCIe, cPCI, PC104p, VPX.
  • Page 6 The PCI bus is defined as little endian and many IPs have their register sets defined to operate efficiently with a little endian interface. The default settings on the PCI5IP are “straight through” byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports.
  • Page 7 The power to each of the IP slots is individually filtered and fused for +5 and ±12. The fuses are rated at 2A on the 5V rail and 1.1A on the ±12V rails. PCI5IP is designed to route maximum power to each slot in parallel. The power supply capabilities for your chassis may provide additional constraints.

  • Page 8: Figure 1 Pci5Ip Power Filtering

    5V supply and bussed on mini-planes to the FPGA. The FPGA is effectively isolated from the IP slots by the regulators and additional filtering. PCI5IP is well behaved with low noise power provided to each of the slots. PCI5IP is designed for analog and digital IP applications including data acquisition, instrumentation, measurement, command and control, telemetry and other industrial applications.

  • Page 9: Figure 2 Pci5Ip Reset Circuit

    PCI5IP conforms to the VITA standard for IndustryPack Carriers. This guarantees compatibility with multiple IndustryPack compatible modules. PCI5IP conforms to the PCI 2.3 specification and supports both 3.3V and 5V signaling levels. PCI5IP is accessible in the memory space on the PCI bus. This guarantees compatibility with other PCI compliant hardware –...

  • Page 10: Figure 3 Pci5Ip Strobe Connection Table

    Xilinx Impact tool should you want to make use of a new feature. For example with the Revision G FLASH, the PCI Core is now a Dynamic Engineering design. This is important because we have corrected a defect in the core previously used which interfered with use in external chassis.

  • Page 11: Theory Of Operation

    Theory of Operation PCI5IP is used to bridge from PCI to IP bus specifications. The PCI bus will be the master in most cases with the IP's being accessed for read or write cycles. The PCI accesses are handled at the lowest level by the PCI core.

  • Page 12: Installation

    – screws and standoffs. http://www.dyneng.com/IPHardware.html If more than one PCI5IP is to be installed into the same system – visible on the PCI bus the dipswitch can be set to different positions on each card. Software can use the...

  • Page 13: Address Map

    0x03000000 // starting address of slot B/C MEM pci5ip_membc_en 0x037FFFFF // end address of slot B/C MEM pci5ip_memde_st 0x03800000 // starting address of slot D/E MEM pci5ip_memde_en 0x03FFFFFF // end address of slot D/E MEM FIGURE 4 PCI5IP ADDRESS MAP Page 13 of 32 Embedded Solutions...

  • Page 14: Programming

    We refer to this address as base0 in our software. The next step is to initialize the PCI5IP. The default of no interrupts enabled and 8 MHz. operation will be valid in many cases. The base register for the PCI5IP and specific slot registers A-E can be initialized to change the default parameters to suite your requirements.
  • Page 15 PCI5IP has individual clock selection for each of the IP modules. Access time is reduced when the IP clock rate is set to 32 MHz. PCI5IP can handle any mixture of clock requirements. Make sure that the IP can handle the higher rate. All Dynamic Engineering IP Modules are rated for both 8 and 32 MHz operation.
  • Page 16 Read the IP manual and see what strategy is best to communicate with that card then adapt the settings on the PCI5IP to optimize your accesses to that IP. With separate control registers for each installed IP you can run different strategies for each installed IP as appropriate.

  • Page 17: Pci5Ip_Intreg_Base

    LED1 LED0 FIGURE 5 PCI5IP CONTROL PORT Reset when set causes a reset to the IP slots. Reset is active as long as the Reset signal is asserted. Reset is synchronized to the IP clock per the IP interface specification. The duration is controlled by the user software. 200 mS is a suggested minimum time to enable for resetting purposes.
  • Page 18 can be useful for software debugging. Set this to simulate an IP interrupt when the hardware is not available. The master interrupt must be enabled to have an effect. Master Interrupt Enable must be set to allow the IP or other interrupt conditions to become an interrupt on the PCI bus.
  • Page 19 ISR operation. Please see the PCI5IP Interrupt Register description. Bus Error Status Master Clear when set ‘1’ causes the Bus Error Status bits in all of the channels to be cleared as well as the state-machine that manages the bus error interrupt.

  • Page 20: Pci5Ip_Intreg_(A-E)

    Speed Control 1 = 32 MHz, 0 = 8 Mhz FIGURE 6 PCI5IP SLOT CONTROL PORT Speed Control selects the slot clock speed. 1 = 32 MHz. 0 = 8 MHz. Clock selection change can be made at any time. Each slot has a separate speed control bit.

  • Page 21: Figure 7 Pci5Ip 16 Bit Byte Swapping

    Byte 0 Byte 1 First Access IP Bus Byte 0 Byte 1 Second Access FIGURE 7 PCI5IP 16 BIT BYTE SWAPPING 32 bit ports D31-24 ó D7-0 D23-16 ó D15-8 D15-8 ó D23-16 D7-0 ó D31-24 Byte 3 Byte 2...
  • Page 22 CBE byte lane strobes. The PCI5IP hardware will translate the data to D15-0 on the IP. Word swapping can be used effectively for big endian ó little endian translation and to accommodate IPs with registers that can be more effectively accessed in reverse order.

  • Page 23: Pci5Ip_Intreg_Int

    PCI interrupt masked off. When an interrupt is detected this register should be read to determine the source or sources and appropriate action taken to clear the interrupt at the IP or clear the mask on PCI5IP. Page 23 of 32...
  • Page 24 PCI5IP provides direct access to the interrupt space. If the IP causing the interrupt requires an interrupt vector fetch to clear the interrupt the appropriate INT space should be accessed. Address bit A1 selects between Int0 and Int1. A1 follows the word address to allow access to both INT0 and INT1 clearing addresses within the INT space.

  • Page 25: Pci5Ip_Intreg_Dswitch

    For example the switch figure below indicates a 0x12. The switch can be used for any user purpose or to identify a particular PCI5IP in a system with more than one card installed. Dynamic Engineering Driver software uses the switch for slot identification.

  • Page 26: Applications Guide

    Power all system power supplies from one switch. Connecting external voltages to the PCI5IP when it is not powered can damage it, as well as the rest of the host system. This problem may be avoided by turning all power supplies on and off at the same time.

  • Page 27: Ip Module Logic Interface Pin Assignment

    IP connector. Thus this table may be used to easily locate the physical pin corresponding to a desired signal. Pin 1 is marked on the carrier. Please note that the PCI5IP revision 2 and later use SMT connectors. Older PCI5IP boards have a slightly different mechanical configuration for the connectors.

  • Page 28: Construction And Reliability

    The IP Module can be secured against the carrier with the connectors. If more security against vibration is required then IP mounting kit can be used to attach the IP to the carrier. Dynamic Engineering has mounting kits available if your IP did not come with one.

  • Page 29: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty. Out of Warranty Repairs Out of warranty repairs will be billed on a material and labor basis.

  • Page 30: Specifications

    Specifications Logic Interfaces: IP Logic Interface, PCI Interface -33 MHz. 32 bit, universal signaling Access types: IO, ID, MEM, INT IP Spaces supported via PCI bus accesses CLK rates supported: 8 MHz or 32 MHz slot by slot selectable. 33 MHz. PCI Software Interface: Control Registers, and Installed IP.

  • Page 31: Order Information

    HDRterm50 http://www.dyneng.com/HDRterm50.html 50-pin header to 50 screw terminal converter with DIN rail mounting. HDRcabl50 50 pin ribbon cable compatible with PCI5IP and HDRterm50. Various lengths off-the-shelf, and custom All information provided is Copyright Dynamic Engineering Page 31 of 32 Embedded Solutions...

  • Page 32: Figure 12 Pci5Ip Location Reference

    The PCI5IP has 5 slots (A,B,C,D,E) and 5 header connectors associated with those slots. The wiring is 1:1 from the IP IO connector to the PCI5IP header connector. The connectors are numbered to match standard ribbon cable as shown in the figure to the right.

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