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2.24
Eth er net Con troller
The 82559 is part of Intel's second generation family of fully integrated 10BASE-T/100BASE-TX
LAN solutions. The 82559 consists of both the Media Access Controller (MAC) and the physical layer
(PHY) combined into a single component solution.
The 82559 is a 32-bit PCI controller that features enhanced scatter-gather bus mastering
capabilities which enables it to perform high-speed data transfers over the PCI bus. The 82559 bus
master capabilities enable the component to process high level commands and perform multiple
operations off-loading communication tasks from the system CPU. Two large transmit and receive
FIFOs of 3 Kbytes each help prevent data underuns and overruns, allowing the 82559 to transmit data
with minimum interframe spacing (IFS).
The 82559 can operate in either full duplex or half duplex mode. In full duplex mode the 82559
adheres to the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a
proprietary collision reduction mechanism.
The 82559 includes a simple PHY interface to the wire transformer at rates of 10BASE-T and 100
BASE-TX, and Auto-Negotiation capability for speed, duplex, and flow control. The 82559 also
includes an interface to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for
hardware and software configuration parameters. The 82559 is also 100% PnP compatible and is
configured through this interface. Ethernet connection to the EBC-LP is made through the connector at
J1.
There are Ethernet status LED's at D1, D2, and D3. The color and function of each LED is listed
below :
D1 = Eth er net 100 base TX (Red)
D2 = Eth er net ac tiv ity LED (Green)
D3 = Eth er net link LED (Yel low)
2.25
Fan Power Connector
J7
o 3
o 2
o 1
The EBC-LP has a connector located at J7 to supply power to the processor cooling fan. The pin
definitons are shown here for reference.
030530
WinSystems - "The Embedded Authority"
J7
GND
o 1
o 2
Fan Power
o 3
N/C
EBC-LP OPERATIONS MANUAL
Page 2-25
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