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2.21
Par al lel I/O
The EBC-LP util izes the WinSystems WS16C48 ASIC high- density I/O chip mapped at a base
ad dress of 120H. The first 24 lines are ca pa ble of fully latched event sens ing with sense po lar ity be ing
soft ware pro gram ma ble. Two, 50- pin con nec tors al low for easy mat ing with in dus try stan dard I/O
racks. The pin-out for the two connectors are shown on the next page.
2.21.1
Par al lel I/O En able
The par al lel fea tures of the EBC-LP can be en abled or dis abled us ing the jumper block at J31. When
J31 is jumpered the par al lel I/O is en abled at I/O ad dress 120H. When J31 is open, the 16 ad dresses
start ing at I/O ad dress 120H are free for use by other de vices.
2.21.2
Par al lel I/O Con nec tors
The 48 lines of par al lel I/O are ter mi nated through two, 50- pin con nec tors at J19 and J20. The J20
con nec tor han dles I/O ports 0-2 while J19 han dles ports 3-5. The pin defi ni tions for J19 and J20 are
shown on the fol low ing page.
030530
WinSystems - "The Embedded Authority"
EBC-LP OPERATIONS MANUAL
J22
3 o o 1
4 o o 2
J24
o 1
o 2
DiskOnChip Enable
jumpers J22 and J24
J26
o 1
o 2
J31
o 1
o 2
Parallel I/O configuration
Jumpers J26 and J31
Page 2-19
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