Table of Contents
Advertisement
8
APPENDIX B: USE OF MULTIPLEXED USER DEVICES
The FPGA configuration of the VM-USB may set up optionally various user devices, that are
beyond the scope of a VME controller, but which are intended to facilitate and reduce the
cost of a data acquisition setup. The "release" firmware of the VM-USB, (Firmware Id =
85000402) sets up two delay and gate generators, DGG_A and DGG_B and two 32-bit
scalers, SCLR_A and SCLR_B.
8.1 Characteristics and the Use of Delay and Gate Generators
The two user gate and delay generators allow one to generate delays and gates in the range of
12.5 ns – approx. 800 us, with the 12.5 ns granularity.
To make use of an DGG_A or DGG_B, one simply needs to select the desired trigger signal
by properly setting the respective selector code bits in the User Devices Register and set
write the desired delay and gate data (in units of 12.5 ns) into the respective DGG register, as
described in Sections 3.4.5 and 3.4.6.
8.2 Characteristics and the Use of Scalers
The two user scalers allow one to count various signals and read out the resulting numbers in
VME-like commands. The latter commands address the VME address space allocated to the
VM-USB and do not generate any activity on the VME bus. Both scalers are asynchronous
with respect to the VM-USB clock, each using a dedicated fast clock network driven by the
selected clock signal.
The use of the scalers is straightforward and entails selecting their respective input sources
and enabling their operation by setting the respective "enable" bits. Optionally, one may wish
to disable them by resetting the respective "enable" bits or clearing them by writing "1" to
the respective "reset" bits.
9
APPENDIX C: ENHANCMENTS IMPLEMENTED IN FIRMWARE 95000405
The following enhancements are implemented in firmware 95000405, as compared with the
earlier versions:
1. The internal Register File is accessed in an "invariant" way by setting bit 12 =1 of the
first VME command word (the AM/Options word).
2. Mixing of regular and scaler events in a common data buffer is possible, by setting bit
5 =1 in Global Register. In this mode of mixed buffering, scaler events are identified
by bit 15 =1 of the event header word (otherwise specifying the number of words in
the event).
3. Two new modes of triggering the scaler readout while in data acquisition mode are
implemented – interactive scaler readout by writing 1 to bit 4 of the Action Register
(not that one must, in fact write "17" to this register, to preserve the acquisition
mode), and timed readout. The latter is selected by writing a non-zero readout period
in units of ½ seconds into bits 8-15 of the Data Acquisition Settings register. All three
WIENER, Plein & Baus GmbH
56
www.wiener-d.com
Advertisement
Table of Contents
