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3.4.5 User Devices Source Selector - Read/Write
Offset = 16 0x10
There are six user devices set up within the FPGA resources of the VM-USB – two NIM
outputs, O1 and O2, two delay and gate generators or pulsers, DGG_1/P_1 and DGG_B/P_1,
and two 32-bit scalers, SCLR_A and SCLR_B. All of these devices may use various signals
as input/trigger signals, with the selection identified by respective code bits stored in the User
Devices Source Selector register. Additionally, this register accommodates bits that enable
and clear the two scalers. The bit composition of the User Devices source selector register is
shown in the table below.
Device
NIM O1
NIM O2
SCLR_A
SCLR_B
DGG_A
DGG_B
For the NIM outputs a 3-bit code identifies the (1 of 8) source of the signal. Like for LEDs,
the first four sources may differ for different NIM outputs, but the last four are shared., The
source codes are as follows
Code NIM O1
0
Busy
1
Event Trigger
2
Bus Request
3
Xfer Event to Data Buffer
4
DGG_A
5
DGG_B
6
End of Event
USB Trigger
7
Note 1. "Busy" signal indicates that stack processing is in progress, with VME operations not
being completed. "Busy" is asserted when event readout is triggered and removed as soon as
VME operations are completed.
Note 2. "Acquire" indicates that the data acquisition mode is active.
Note 3. "USB Trigger" is generated in response to writing to bit 1 of Action Register.
Note 4. "Event Trigger" indicates that event readout has been triggered.
Note 5. Invert bit causes the signal to be inverted
Note 6. Latch bit causes the signal to be latched. To release the latch one must toggle the bit.
The meaning of the input selector codes for scalers and delay and gate generators is shown in
the table below
WIENER, Plein & Baus GmbH
Reset
Enable
-
-
-
-
19
18
23
22
-
-
-
-
Latch Bit
Invert Bit
4
12
-
-
-
-
NIM O2
USB Trigger
Executing VME Command
VME Address Strobe AS
Xfer Data Buffer to USB FIFO
DGG_A
DGG_B
End of Event
USB Trigger
19
Code
3
0-2
11
8-10
-
16-17
-
20-21
24-26
-
28-30
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