Delay And Gate Generator / Pulser Registers - Read/Write - Wiener VM-USB User Manual

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3.4.6 Delay and Gate Generator / Pulser Registers – Read/Write
DGG _A Offset = 20 / 0x14
DGG _B Offset = 24 / 0x18
DGG _ Ext Offset =56/0x38
The two Delay and Gate Generator / Pulser Registers DGG_A and DGG_B as well as the
DGG_ Extend register store data defining the length of the delay and the length of the gate in
units of 12.5 ns (80 MHz clock) for either the gate and delay generator or for the pulser.
These values can be set for channel A and B independently. The pulser is re-triggering after
the defined delay time, i.e. the delay time + gate length defines the pulser repetition rate. The
value of the delay is a composite of a high resolution value (12.5ns) and a coarse range value
which was added with firmware 6.0 to increase the possible time range up to 53.5s . Earlier
firmware versions use only the fine (12.5ns) value.
Gate length
Delay
Pulser repetition period = Gate + Delay
DGG_A 16-31
DGG_B Offset = 24 / 0x18
DGG_B 16-31
DGG_ Ext Offset =56/0x38
DGG_B Ext (16-31)
Delay coarse
WIENER, Plein & Baus GmbH
SCLR_A
Disabled
NIM I1
NIM I2
Event
-
-
= 12.5ns * Gate
= 12.5ns * Delay_fine + 819.2
Gate
Gate
SCLR_B DGG_A/P_A
Disabled Disabled
NIM I1 NIM I1
NIM I2 NIM I2
Event Event Trigger
- End of Event
- USB Trigger
Pulser
DGG_A 0-15
Delay_fine
DGG_ B 0-15
Delay_fine
DGG_A Ext 0-15
Delay coarse
20
DGG_B/P_B
Disabled
NIM I1
NIM I2
Event Trigger
End of Event
USB Trigger
Pulser
µ
s* Delay_coarse
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