Motorola RAM104 User Manual page 56

Processor/memory mezzanine module, dram memory module
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Input/Output
I/O
PCI/ISA Bridge Controller
IBC
Intelligent Device Expansion
IDE
Institute of Electrical and Electronics Engineers
IEEE
A graphics system in which the even scanlines are refreshed in one
interlaced
vertical cycle (field), and the odd scanlines are refreshed in
another vertical cycle. The advantage is that the video bandwidth
is roughly half that required for a non-interlaced system of the
same resolution. This results in less costly hardware. It also may
make it possible to display a resolution that would otherwise be
impossible on given hardware. The disadvantage of an interlaced
system is flicker, especially when displaying objects that are only
a few scanlines high.
Similar to the color difference signals (R-Y) (B-Y) but using
IQ Signals
different vector axis for encoding or decoding. Used by some USA
TV and IC manufacturers for color decoding.
Industry Standard Architecture (bus). The de facto standard
ISA (bus)
system bus for IBM-compatible computers until the introduction
of VESA and PCI. Used in the reference platform specification.
(IBM)
ISA Super Input/Output device
ISASIO
Integrated Services Digital Network. A standard for digitally
ISDN
transmitting video, audio, and electronic data over public phone
networks.
Local Area Network
LAN
Light-Emitting Diode
LED
Linear Feet per Minute
LFM
A byte-ordering method in memory where the address n of a word
little-endian
corresponds to the least significant byte. In an addressed memory
word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being
the most significant byte.
Multiplexed BLock Transfer
MBLT
Micro Channel Architecture
MCA (bus)
Motorola Computer Group
MCG
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Glossary
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