Dram Size Register - Motorola RAM104 User Manual

Description
1
CKM1-CKM0 Clocking Configuration. These bits reflect the clocking
configuration of the PM603/PM604. The encoding for these bits is as
follows:
CPUTYPE

DRAM Size Register

The DRAM Size Register is an 8-bit register providing the DRAM size
information. Banks 0 and 1 are on the PM603/PM604; Banks 2 and 3
reside on the RAM104 DRAM add-on module. This register resides on the
PM603/PM604 module but the actual address decoding is done by the
MVME160x board.
1-10
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CKM1
0
0
1
1
CPU Type. These four bits reflect the CPU type
information. For the MVME160x, this field is hard wired
to 0001 (binary).
REG DRAM Size Register - 0804 (hex)
BIT
SD7 SD6
FIELD
B2/B3 B2/B3 B2/B3
ASYM_ SIZ2
OPER R R
RESET N/A N/A
CKM0 PCI Bus Clock CPU External
0 33 MHz
1 20 MHz
0 25 MHz
1 33 MHz
SD5 SD4 SD3 SD2
B2/B3 B0/B1 B0/B1
SIZ1 SIZ0 ASYM_ SIZ2
R R R
N/A N/A N/A N/A
Bus Clock
33 MHz
40 MHz
50 MHz
66 MHz
SD1 SD0
B0/B1 B0/B1
SIZ1 SIZ0
R R R
N/A N/A