Dram; Table 1-3. Minimum Romfal And Romnal Values - Motorola RAM104 User Manual

Description
1
Because 512Kx8 Flash and EEPROM PLCC devices have different
pinouts, zero-ohm resistors are provided for hard-wired configuration. The
default hard-wired configuration is for Flash. The onboard
monitor/debugger and diagnostic firmware, PPCBug, resides in the Flash
chips.
For EEPROM/Flash speed of 150 ns, software must not program
ROMFAL and ROMNAL in the MPC105 device with values lower than
the following minimum values for various processor external clock
frequencies (hardware does not support the burst which NAL is used for):

DRAM

The MVME160x supports 8MB to 128MB of non-interleaved DRAM.
8MB to 64MB of 64-bit DRAM is located on the same module (PM603 or
PM604) as the processor. It is in one bank (8MB or 32MB) or two banks
(16MB or 64MB), not interleaved, in 300 mil TSOP Type II packaging. An
additional 8MB to 64MB of DRAM may be added as a RAM104-xxx
memory mezzanine module that is plugged into the processor/memory
module. This second memory module stacks on the processor/memory
module and still fits in a single 0.8 inch VMEbus slot (on the PM603 only;
the PM604 has a double-wide front panel and takes two VMEbus slots
because of its heatsink). Locating all memory on mezzanine module(s)
allows for cost effective field upgrades.
No parity or ECC protection is presently provided for the DRAM.
The DRAM data bus is 64 bits wide, and its address bus is 32 bits wide.
Single cycle read or write accesses take 8 clock cycles each. Burst mode
read or write accesses, using a 66 MHz bus clock signal, take 8-4-4-4
cycles.
1-8
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Table 1-3. Minimum ROMFAL and ROMNAL Values

Processor
External Bus Speed
25 MHz
33 MHz
40 MHz
50 Mhz
66 MHz
ROMFAL
Minimum Value Minimum Value
4
5
6
8
10
ROMNAL
0
0
0
0
0