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SIZ2 - SIZ0
B0/B1 (B2/B3)
SIZ2 SIZ1 SIZ0
0
1
0
1
0
0
0
0
1
1
1
1
1
0
1
0
Note
This is for the new 192-MB DRAM mezzanine, used only on
the MVME1604-026 and -036 boards. When this mezzanine
is used, all six 32-MB banks are populated. It is available
only as a factory feature and not as an upgrade option.
ASYM_
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DRAM Size. These bits provide the DRAM size
information for the four banks of DRAM supported by the
PM603/PM604. The encoding for these size bits is as
follows:
DRAM Size
Bank 0 (Bank 2)
1
32 MB (See note)
0
8 MB
1
32 MB
0
128MB
1
Not Present
0
8 MB
1
32 MB
0
128 MB
Asymmetric Refresh Mode. When cleared, this bit
indicates that the DRAM devices installed for Bank 0 and
Bank 1 (Bank 2 and Bank 3) have more row address bits
than column address bits. This bit is used to determine
how to program the MPC105 chip appropriately. Note
that, at this time, only the 4M x 4 DRAM devices (32MB
banks) have this option. For 4M x4 DRAM, the
asymmetric refresh mode is also referred to as the 4K
refresh mode. For these devices, there would be 12 row
addresses and 10 column addresses.
Functional Description
Bank 1 (Bank 3)
32 MB (See note)
Not Present
Not Present
Not Present
Not Present
8 MB
32 MB
128 MB
1-11
1
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