Control And Status Registers; Cpu Configuration Register - Motorola RAM104 User Manual

Control and Status Registers

The CPU Configuration Register and the DRAM Size Register are on the
PM603/PM604 mezzanine modules. These registers are accessible in ISA
I/O space. Note that in the OPER row, R = read only bit, R/W = read or
write bit, and W = write only bit.
Resistors on the RAM104 DRAM Memory module are read as part of the
DRAM Size Register.
The other control and status registers are on the MVME160x main module.
These registers are accessible in ISA I/O space. Refer to the
MVME1603/MVME1604 Single Board Computer Programmer's
Reference Guide for further information.

CPU Configuration Register

The CPU Configuration Register provides the configuration information
about the PM603/PM604 module. This register resides on the
PM603/PM604 mezzanine module, but actual decoding is done by the
MVME160x board.
REG
BIT
FIELD
OPER
RESET
L2P1-L2P0L2 Cache Present. These bits are defined as follows:
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CPU Configuration Register - 0800 (hex)
SD7 SD6 SD5 SD4
CPUTYPE
R
0001 (binary)
L2P1 L2P0
0 0
0 1
1 0
1 1
Functional Description
SD3 DS2 SD1 SD0
CKM1 CKM0 L2P1 L2P0
R R R
N/A N/A N/A N/A
L2 Cache Size
512KB
256KB
1MB
L2 Cache Not Present
1
R
1-9