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Protecting the Controller Against Negative
Spikes
As with any controller built upon a CMOS technology, it
is the designer's duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between V
CC
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user unplugs the power supply, the controller is still
Figure 35. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 36). Please note that the negative
spike is clamped to –2 x Vf due to the diode bridge. Please
refer to AND8069 for power dissipation calculations.
1
+
Cbulk
2
3
4
Figure 36. A simple resistor in series avoids any
latchup in the controller
and GND. If the current sense
3
Rbulk
> 4.7 k
2
8
7
6
1
+
5
CV
CC
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NCP1201
fed by its V
capacitor and keeps activating the MOSFET
CC
ON and OFF with a peak current limited by Rsense.
Unfortunately, if the quality coefficient Q of the resonating
network formed by Lp and Cbulk is low (e.g. the MOSFET
Rdson + Rsense are small), conditions are met to make the
circuit resonate and thus negatively bias the controller. Since
we are talking about ms pulses, the amount of injected
charge (Q = I x t) immediately latches the controller which
brutally discharges its V
is of sufficient value, its stored energy damages the
controller. Figure 35 depicts a typical negative shot
occurring on the HV pin where the brutal V
testifies for latchup.
Another option (Figure 37) consists in wiring a diode from
V
to the bulk capacitor to force V
CC
sooner and thus stops the switching activity before the bulk
capacitor gets deeply discharged. For security reasons, two
diodes can be connected in series.
+
Cbulk
Figure 37. or a diode forces V
UVLOlow sooner
16
capacitor. If this V
CC
CC
discharge
CC
to reach UVLOlow
CC
3
1
8
D3
1N4007
2
7
3
6
1
+
4
5
CV
CC
to reach
CC
capacitor
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