Table of Contents
Advertisement
As shown below, the fault logic is armed once V
10 V after startup phase. When powering the device from an
auxiliary winding, meeting this condition can sometimes be
problematic since upon startup, V
not down as with a DSS. As a result, V
and the fault logic is not activated. If a short−circuit takes
place, the fault circuitry activates as soon as V
below 10 V (because of the coupling between V
12 V
10 V
Calculating the V
Capacitor
CC
As the above section describes, the fall down sequence
depends upon the V
level, i.e. how long does it take for the
CC
V
line to decrease from 12.5 V to 10.5 V. The required
CC
time depends on the powerup sequence of your system, i.e.
when you first apply the power to the device. The
corresponding transient fault duration due to the output
capacitor charging must be less than the time needed to
discharge from 12.5 V to 10.5 V, otherwise the supply will
not properly startup. The test consists in either simulating or
measuring in the laboratory to determine time required for
the system to reach the regulation at full load. Let's assume
crosses
CC
naturally goes up and
CC
never crosses 10 V
CC
collapses
CC
and
aux
V
CC
Regulation
occurs here
Overload is
Drv
not activated
Driver
Pulses
Open−loop
FB level
FB
Regulation
Figure 34. Fault Protection Timing Diagram
http://onsemi.com
NCP1201
V
), but in presence of a broken optocoupler, i.e. feedback
out
is open, V
increases and the fault will never triggered! To
CC
avoid this problem, the application note "Tips and Tricks
with NCP1200, AN8069/D" offers some possible solutions
where the DSS is kept for protection logic operation only but
all the driving power is derived from the auxiliary winding.
Some solutions even offer the ability to disable the DSS in
standby and benefit to low standby power.
No synchronization
between DSS and
fault event
Overload is
activated
Latched−off
Fault occurs here
that this time corresponds to 6.0 ms. Therefore a V
time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
capacitor using the following formula:
DV = 2.0 V. Then for a wanted Dt of 10 ms, C equals 9.0 mF
or 10 mF for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 575 mA typical. This explains the V
falling slope changes after latchoff in Figure 34.
15
Time
Time
Time
fall
CC
Dt + DV
C
, with
i
CC
Advertisement
Table of Contents
