Verifying Acr Configuration - Cisco ASR 900 Series Configuration Manual

Configuring DCR for SAToP

Verifying ACR Configuration

Use show recovered clock command to verify E1 ACR configuration:
#show recovered clock
Recovered clock status for subslot 0/4
----------------------------------------
Clock
1
(Port/au-4/tug3/tug2/e1)
Use show recovered clock command to verify E3 ACR configuration:
#show recovered clock
Recovered clock status for subslot 0/4
----------------------------------------
Clock
1
Configuring DCR for SAToP
Differential Clock Recovery (DCR) is another technique used for Circuit Emulation (CEM) to recover clocks
based on the difference between PE clocks. TDM clock frequency are tuned to receive differential timing
messages from the sending end to the receiving end. A traceable clock is used at each end, which ensures the
recovered clock is not affected by packet transfer.
To configure E1 DCR:
enable
configure terminal
controller sdh 0/4/0
rate STM1
no ais-shut
alarm-report all
clock source internal
overhead s1s0 0
aug mapping au-4
au-4 1
clock source internal
mode tug-3
tug-3 1
mode vc1x
tug-2 1 payload vc12
e1 1 cem-group 1 unframed
e1 1 clock source recovered 1
tug-2 2 payload vc11
tug-2 3 payload vc11
tug-2 4 payload vc11
end
To configure E3 DCR:
enable
configure terminal
controller sdh 0/4/0
rate STM1
no ais-shut
alarm-report all
clock source internal
overhead s1s0 0
aug mapping au-4
au-4 1
clock source internal
mode tug-3
tug-3 1
1-Port OC-192 or 8-Port Low Rate CEM Interface Module Configuration Guide, Cisco IOS XE Everest 16.7.x
(Cisco ASR 900 Series)
108
Configuring SDH on 1-Port OC-192/STM-64 or 8-Port OC-3/12/48/STM-1/-4/-16 Module
Type Mode CEM
STMx-E1 ADAPTIVE 1
Type Mode CEM
STMx-E3 ADAPTIVE 1
Status Frequency Offset(ppb)
ACQUIRED n/a
Status Frequency Offset(ppb)
ACQUIRED n/a
Circuit-No
0/1/1/1/1
Circuit-No
0/1/1 (Port/au-4/tug3)