Ericsson EF738 Service Manual page 168

Technical Description
Decoder
The decoder in GUSTAV is an address decoder which has outputs for both internal
functions and logic control signals such as chip selects (CS), write (W) and output
enable (OE).
Serial Interface
The serial interface in GUSTAV has a transmitter block and a receiver block.
The transmitter block consists of four write registers, a clock divider, and other
logic for generating interrupts and latch signals. Data is transmitted and received via
a serial interface data line.
The receiver block consists of three read registers in which the received data may be
read one byte at a time by the processor.
External Ports
This block manages the keyboard along with the handling of binary input/output
ports where some inputs are connected to the interrupt control block.
WatchDog On/Off
The Watchdog On/Off block in GUSTAV contains the watchdog block and the
Autonomous Time Out (ATO) block. This block consists of a four second counter,
which when overflown, activates a reset circuit and generates a 100ms reset.
The ATO is a supervising block that monitors the status of the received carrier
detect and the transmitter power. If the transmitted power is detected without the
received carrier detect for 30 seconds, the ATO initiates a hardware turn off of the
phone.
IFC
The IFC counter is used to count a predetermined number of periods of the IF from
the radio interface LSI.
BAR
The output from the bar generator is a continuous pulse train with program control-
led ON and OFF time. This makes it possible to vary signal parameters such as:
• tone frequency
• signal period
• signal on time
• volume
Clock Generator
The processor clock is generated from an external signal or crystal.
An 8.064 MHz clock gives a system clock frequency of 1.008 MHz (or 2.016 MHz
in Turbo mode). The serial interface clock will always be 1.008 MHz. The clock
generator block has many divider steps to generate all clock frequencies that are
required inside GUSTAV and on the logic PCB.
25