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VID_SCN_ITERFACECNTL
The Video Screen Interface Control register contains the control logic used to determine the
signal output characteristics to the video display.
VID_SCN_RESETS
The Video Screen Reset register contains the control logic for reset events, including the reset
pan and scan, horizontal filtering and DMA enabling functions. This register is set to 1 on reset.
VID_SCN_STATUS
The Video Screen Status register contains the status bits for the video section.
VID_SCN_OSD_HSTART
The OSD Video Screen Horizontal Start Address register contains the horizontal starting address
value for the OSD, as referenced from the active display window.
VID_SCN_OSD_HEND
The OSD Video Screen Horizontal End Address register contains the 13-bit horizontal ending
address value for the OSD, as referenced from the active video display.
VID_SCN_OSD_VSTART
The OSD Video Screen Vertical Start Address register contains the 13-bit vertical starting
address value for the OSD, as referenced from the active video display.
VID_SCN_OSD_VEND
The OSD Video Screen Vertical End Address register contains the 13-bit vertical ending address
value for the OSD, as referenced from the active video display.
VID_SCN_OSD_MISC
The OSD Video Screen Miscellaneous register contains the control logic and status bits for the
OSD controller.
VID_SCN_OSD_PALETTE
These 16 registers contain the OSD palette.
6 SDRAM M
EMORY
The memory bus interface generates all the control signals to interface with external memory.
The Vibratto supports different configurations using the memory configuration bits SDCFG[1:0]
(bits 12:11), the SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL
register. Configurations can be implemented in many ways. The following table lists the typical
SDRAM configurations used by the Vibratto.
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