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9 ATA/IDE
LOADER INTERFACE
The host interface can directly support ATAPI devices such as DVD drives or I/O
controllers. PIO modes 0 through 4 are supported. The ATA/IDE interface can directly control two
devices through the use of the HCS1FX# and HCS3FX# signals. The ATA/IDE interface of the
Vibratto uses a command execution protocol that allows the operation of audio-CD and DVD
loaders to coexist on the same type of interface cable that most computers use for CD loaders
and hard disk drives.
Note: The decoder board supports the standard ATAPI electrical connections, but the
software protocol within the drive is not always supported according to ATAPI specifications.
Custom software may need to be developed and tested to support ATAPI drives from different
manufacturers.
10 A
I
UDIO
NTERFACE
C
ONFIGURATION
The ES6008/18 Vibratto audio mode configuration is selectable, allowing it to interface
directly with low-cost audio DACs and ADCs. The audio port provides a standard I
input and output and S/PDIF (IEC958) audio output. Stereo mode is in I
channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The
S/PDIF interface consists of a bi-phase mark encoder, which has low skew. The transmit I
interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where sampling
frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the
2
I
S transmit interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the Vibratto supports 48 kHz and 96 kHz. Dolby
Digital audio only supports 48 kHz. The ES6008/18 Vibratto incorporates a built-in programmable
analog PLL in the device architecture in order to generate a master audio clock. The MCLK pin is
for the audio DAC clock and can either be an output from or an input to the ES6008/18 Vibratto.
Audio data out (TSD) and audio frame sync (TWS) are clocked out of the Vibratto based on the
audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is used to clock in audio data in
(RSD) and audio receive frame sync (RWS).
11 F
P
RONT
ANEL
11.1 VFD C
ONTROLLER
The VFD controller is a NEC uPD16311. This controller is not a processor, but does
include a simple state machine which scans the VFD and reads the front panel button matrix. The
16311 also includes RAM so it can store the current state of all the VFD icons and segments.
Therefore, the 16311 need only be accessed when the VFD status changes and when the button
status is read. The ES6008/ES6018 can control this chip directly using PIO pins or can allow the
front panel PIC to control the VFD.
12 M
ISCELLANEOUS
12.1 R
C
ESET
IRCUITRY
Two different chips are supported to provide the power-on-reset DS1811 or AAT3520.
12.2 V
R
OLTAGE
EGULATORS
A
S
UDIO
AMPLING
F
UNCTIONS
15
R
PLL C
ATE AND
2
S format while six
OMPONENT
2
S interface
2
S
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