No. 0153 HTDK170E HTDK170EUK SERVICE MANUAL MANUEL D'ENTRETIEN WARTUNGSHANDBUCH CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. Data contained within this Service manual is subject to alteration for improvement.
1. G ENERAL ESCRIPTION 1.1 ES60X8 The ES6008/ES6018 Vibratto DVD processor is a single-chip MPEG video decoding chip that integrates audio/video stream data processing, TV encoder, four video DACs with Macrovision. copy protection, DVD system navigation, system control and housekeeping functions.
• High-Definition Compatible Digital. (HDCD) decoding. • Dolby Digital Class A and HDCD certified. • CD-DA. • MP3. 1.2 M EMORY 1.2.1 System SRAM Interface The system SRAM interface controls access to optional external SRAM, which can be used for RISC code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus width and wait states.
2. S ES6008/18 P YSTEM LOCK IAGRAM and ESCRIPTION 2.1 ES6008/18 PIN DESCRIPTION...
2.1 SYSTEM BLOCK DIAGRAM System block diagram is shown in the following figure: 3. A UDIO UTPUT The ES6008 supports two-channel analog audio output while ES6018 supports six-channel analog audio output. In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround system.
IDEO NTERFACE 5.1 Video Display Output The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the Vibratto. The output section consists of a programmable CRT controller capable of operating either in Master or Slave mode. The video output section features internal line buffers which allow the outgoing luminance and chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion.
VID_SCN_HBLANK_STOP The write-only Video Screen Horizontal Blanking Interval End Address register contains the 13-bit ending address of the horizontal blanking stop interval for the active video display. VID_SCN_VBLANK_START The Video Screen Vertical Blanking Interval Start Address register contains the 13-bit starting address of the vertical blanking interval for the active video display.
VID_SCN_ITERFACECNTL The Video Screen Interface Control register contains the control logic used to determine the signal output characteristics to the video display. VID_SCN_RESETS The Video Screen Reset register contains the control logic for reset events, including the reset pan and scan, horizontal filtering and DMA enabling functions. This register is set to 1 on reset. VID_SCN_STATUS The Video Screen Status register contains the status bits for the video section.
Typical SDRAM Configurations: The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers. At high clock speeds, the Vibratto memory bus interface has sufficient bandwidth to support the decoding and displaying of CCIR601 resolution images at full frame rate.
9 ATA/IDE LOADER INTERFACE The host interface can directly support ATAPI devices such as DVD drives or I/O controllers. PIO modes 0 through 4 are supported. The ATA/IDE interface can directly control two devices through the use of the HCS1FX# and HCS3FX# signals. The ATA/IDE interface of the Vibratto uses a command execution protocol that allows the operation of audio-CD and DVD loaders to coexist on the same type of interface cable that most computers use for CD loaders and hard disk drives.
There are 7812, 7805 and LM317 linear regulator ICs on the power supply to generate +5V, -5V, +12V, -12V and +3.3V for the device. On the standby mode just +12Vst and +5V supplies are generating for standby power consumption. The ES6008/18 requires 2.5V to operate. This voltage is generated from +5V. 13 C ONNECTORS 13.1 ATAPI D...
IC500 8051 Micro Controller's Main Functions: There are 2 main functions of the IC500 8051 micro controller; signal switching and standby controlls. IC500 communicates with ES80X6 microcontroller by using I C bus. (AUX0, AUX1 signals) Multiplexer (MUX) control signals for signal switching supplied by IC500. These MUX signals are using the select signal sources and input-output signals.
• Voltages on the secondary side are as follows: +20 Volts at D811, +10 Volts at D808, +14V at D810, -22 Volts at D812, +12Vst at Q804. • Using the output of the D808, a photo diode inside of the IC803 generates feedback signal bu using optocoupler's photo transistor.
• There are 1 DOUBLE SCART connector PL300 (Scart1 is for input on Scart mode and Scart2 is for TV output), 3 pieces RCA audio jacks (L,R, Active Subwoofer) for audio output, 3 pieces RCA A/V jacks for CVBS,L,R inputs on AV mode, 1 RCA connector for CVBS out, 1 Connector for SVHS output.