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5 V
I
IDEO
NTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV
encoder of the Vibratto. The output section consists of a programmable CRT controller capable of
operating either in Master or Slave mode.
The video output section features internal line buffers which allow the outgoing luminance and
chrominance data to match the internal clock rates with external pixel clock rates, easily
facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter
achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in
CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels
per line as luminance (Y) pixels; there are as many chrominance lines as luminance.
Video Post-Processing
The Vibratto video post-processing circuitry provides support for the color conversion, scaling,
and filtering functions through a combination of special hardware and software. Horizontal up-
sampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in
accordance with the applicable scaling ratio.
Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel
clock. The double clock typically is used for TV displays, the single for computer displays.
Video Interface Registers
VID_SCN_HSTART
The write-only Video Screen Horizontal Start Address register contains the 13-bit horizontal pixel
starting address of the active video display.
VID_SCN_HEND
The write-only Video Screen Horizontal End Address register contains the 13-bit horizontal pixel
ending address of the active video display.
VID_SCN_VSTART
The write-only Video Screen Vertical Start Address register contains the 13-bit vertical scan line
starting address of the active video display.
VID_SCN_VEND
The write-only Video Screen Vertical End Address register contains the 13-bit vertical scan line
ending address of the active video display.
VID_SCN_VERTIRQ
The write-only Video Screen Vertical Line Interrupt register is selectable by software and contains
the line in which a vertical interrupt will occur. Line 0 is the top of the screen, as defined by the
leading edge of the VSYNC pin. Typically, an interrupt is set either just before or just after the
active video display.
VID_SCN_HBLANK_START
The write-only Video Screen Horizontal Blanking Interval Start Address register contains the 13-
bit starting address of the horizontal blanking interval for the active video display.
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